tests: virtio-9p: rename PCI configuration test
[qemu.git] / target / ppc / translate_init.c
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "qemu/osdep.h"
22 #include "disas/bfd.h"
23 #include "exec/gdbstub.h"
24 #include "sysemu/kvm.h"
25 #include "kvm_ppc.h"
26 #include "sysemu/arch_init.h"
27 #include "sysemu/cpus.h"
28 #include "cpu-models.h"
29 #include "mmu-hash32.h"
30 #include "mmu-hash64.h"
31 #include "qemu/error-report.h"
32 #include "qapi/visitor.h"
33 #include "hw/qdev-properties.h"
34 #include "hw/ppc/ppc.h"
35
36 //#define PPC_DUMP_CPU
37 //#define PPC_DEBUG_SPR
38 //#define PPC_DUMP_SPR_ACCESSES
39 /* #define USE_APPLE_GDB */
40
41 /* Generic callbacks:
42 * do nothing but store/retrieve spr value
43 */
44 static void spr_load_dump_spr(int sprn)
45 {
46 #ifdef PPC_DUMP_SPR_ACCESSES
47 TCGv_i32 t0 = tcg_const_i32(sprn);
48 gen_helper_load_dump_spr(cpu_env, t0);
49 tcg_temp_free_i32(t0);
50 #endif
51 }
52
53 static void spr_read_generic (DisasContext *ctx, int gprn, int sprn)
54 {
55 gen_load_spr(cpu_gpr[gprn], sprn);
56 spr_load_dump_spr(sprn);
57 }
58
59 static void spr_store_dump_spr(int sprn)
60 {
61 #ifdef PPC_DUMP_SPR_ACCESSES
62 TCGv_i32 t0 = tcg_const_i32(sprn);
63 gen_helper_store_dump_spr(cpu_env, t0);
64 tcg_temp_free_i32(t0);
65 #endif
66 }
67
68 static void spr_write_generic (DisasContext *ctx, int sprn, int gprn)
69 {
70 gen_store_spr(sprn, cpu_gpr[gprn]);
71 spr_store_dump_spr(sprn);
72 }
73
74 #if !defined(CONFIG_USER_ONLY)
75 static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
76 {
77 #ifdef TARGET_PPC64
78 TCGv t0 = tcg_temp_new();
79 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
80 gen_store_spr(sprn, t0);
81 tcg_temp_free(t0);
82 spr_store_dump_spr(sprn);
83 #else
84 spr_write_generic(ctx, sprn, gprn);
85 #endif
86 }
87
88 static void spr_write_clear (DisasContext *ctx, int sprn, int gprn)
89 {
90 TCGv t0 = tcg_temp_new();
91 TCGv t1 = tcg_temp_new();
92 gen_load_spr(t0, sprn);
93 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
94 tcg_gen_and_tl(t0, t0, t1);
95 gen_store_spr(sprn, t0);
96 tcg_temp_free(t0);
97 tcg_temp_free(t1);
98 }
99
100 static void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
101 {
102 }
103
104 #endif
105
106 /* SPR common to all PowerPC */
107 /* XER */
108 static void spr_read_xer (DisasContext *ctx, int gprn, int sprn)
109 {
110 gen_read_xer(cpu_gpr[gprn]);
111 }
112
113 static void spr_write_xer (DisasContext *ctx, int sprn, int gprn)
114 {
115 gen_write_xer(cpu_gpr[gprn]);
116 }
117
118 /* LR */
119 static void spr_read_lr (DisasContext *ctx, int gprn, int sprn)
120 {
121 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
122 }
123
124 static void spr_write_lr (DisasContext *ctx, int sprn, int gprn)
125 {
126 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
127 }
128
129 /* CFAR */
130 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
131 static void spr_read_cfar (DisasContext *ctx, int gprn, int sprn)
132 {
133 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
134 }
135
136 static void spr_write_cfar (DisasContext *ctx, int sprn, int gprn)
137 {
138 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
139 }
140 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
141
142 /* CTR */
143 static void spr_read_ctr (DisasContext *ctx, int gprn, int sprn)
144 {
145 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
146 }
147
148 static void spr_write_ctr (DisasContext *ctx, int sprn, int gprn)
149 {
150 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
151 }
152
153 /* User read access to SPR */
154 /* USPRx */
155 /* UMMCRx */
156 /* UPMCx */
157 /* USIA */
158 /* UDECR */
159 static void spr_read_ureg (DisasContext *ctx, int gprn, int sprn)
160 {
161 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
162 }
163
164 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
165 static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
166 {
167 gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
168 }
169 #endif
170
171 /* SPR common to all non-embedded PowerPC */
172 /* DECR */
173 #if !defined(CONFIG_USER_ONLY)
174 static void spr_read_decr (DisasContext *ctx, int gprn, int sprn)
175 {
176 if (ctx->tb->cflags & CF_USE_ICOUNT) {
177 gen_io_start();
178 }
179 gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
180 if (ctx->tb->cflags & CF_USE_ICOUNT) {
181 gen_io_end();
182 gen_stop_exception(ctx);
183 }
184 }
185
186 static void spr_write_decr (DisasContext *ctx, int sprn, int gprn)
187 {
188 if (ctx->tb->cflags & CF_USE_ICOUNT) {
189 gen_io_start();
190 }
191 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
192 if (ctx->tb->cflags & CF_USE_ICOUNT) {
193 gen_io_end();
194 gen_stop_exception(ctx);
195 }
196 }
197 #endif
198
199 /* SPR common to all non-embedded PowerPC, except 601 */
200 /* Time base */
201 static void spr_read_tbl (DisasContext *ctx, int gprn, int sprn)
202 {
203 if (ctx->tb->cflags & CF_USE_ICOUNT) {
204 gen_io_start();
205 }
206 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
207 if (ctx->tb->cflags & CF_USE_ICOUNT) {
208 gen_io_end();
209 gen_stop_exception(ctx);
210 }
211 }
212
213 static void spr_read_tbu (DisasContext *ctx, int gprn, int sprn)
214 {
215 if (ctx->tb->cflags & CF_USE_ICOUNT) {
216 gen_io_start();
217 }
218 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
219 if (ctx->tb->cflags & CF_USE_ICOUNT) {
220 gen_io_end();
221 gen_stop_exception(ctx);
222 }
223 }
224
225 __attribute__ (( unused ))
226 static void spr_read_atbl (DisasContext *ctx, int gprn, int sprn)
227 {
228 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
229 }
230
231 __attribute__ (( unused ))
232 static void spr_read_atbu (DisasContext *ctx, int gprn, int sprn)
233 {
234 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
235 }
236
237 #if !defined(CONFIG_USER_ONLY)
238 static void spr_write_tbl (DisasContext *ctx, int sprn, int gprn)
239 {
240 if (ctx->tb->cflags & CF_USE_ICOUNT) {
241 gen_io_start();
242 }
243 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
244 if (ctx->tb->cflags & CF_USE_ICOUNT) {
245 gen_io_end();
246 gen_stop_exception(ctx);
247 }
248 }
249
250 static void spr_write_tbu (DisasContext *ctx, int sprn, int gprn)
251 {
252 if (ctx->tb->cflags & CF_USE_ICOUNT) {
253 gen_io_start();
254 }
255 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
256 if (ctx->tb->cflags & CF_USE_ICOUNT) {
257 gen_io_end();
258 gen_stop_exception(ctx);
259 }
260 }
261
262 __attribute__ (( unused ))
263 static void spr_write_atbl (DisasContext *ctx, int sprn, int gprn)
264 {
265 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
266 }
267
268 __attribute__ (( unused ))
269 static void spr_write_atbu (DisasContext *ctx, int sprn, int gprn)
270 {
271 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
272 }
273
274 #if defined(TARGET_PPC64)
275 __attribute__ (( unused ))
276 static void spr_read_purr (DisasContext *ctx, int gprn, int sprn)
277 {
278 gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
279 }
280
281 /* HDECR */
282 static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
283 {
284 if (ctx->tb->cflags & CF_USE_ICOUNT) {
285 gen_io_start();
286 }
287 gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
288 if (ctx->tb->cflags & CF_USE_ICOUNT) {
289 gen_io_end();
290 gen_stop_exception(ctx);
291 }
292 }
293
294 static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
295 {
296 if (ctx->tb->cflags & CF_USE_ICOUNT) {
297 gen_io_start();
298 }
299 gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
300 if (ctx->tb->cflags & CF_USE_ICOUNT) {
301 gen_io_end();
302 gen_stop_exception(ctx);
303 }
304 }
305
306 #endif
307 #endif
308
309 #if !defined(CONFIG_USER_ONLY)
310 /* IBAT0U...IBAT0U */
311 /* IBAT0L...IBAT7L */
312 static void spr_read_ibat (DisasContext *ctx, int gprn, int sprn)
313 {
314 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
315 }
316
317 static void spr_read_ibat_h (DisasContext *ctx, int gprn, int sprn)
318 {
319 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
320 }
321
322 static void spr_write_ibatu (DisasContext *ctx, int sprn, int gprn)
323 {
324 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
325 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
326 tcg_temp_free_i32(t0);
327 }
328
329 static void spr_write_ibatu_h (DisasContext *ctx, int sprn, int gprn)
330 {
331 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
332 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
333 tcg_temp_free_i32(t0);
334 }
335
336 static void spr_write_ibatl (DisasContext *ctx, int sprn, int gprn)
337 {
338 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
339 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
340 tcg_temp_free_i32(t0);
341 }
342
343 static void spr_write_ibatl_h (DisasContext *ctx, int sprn, int gprn)
344 {
345 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
346 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
347 tcg_temp_free_i32(t0);
348 }
349
350 /* DBAT0U...DBAT7U */
351 /* DBAT0L...DBAT7L */
352 static void spr_read_dbat (DisasContext *ctx, int gprn, int sprn)
353 {
354 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
355 }
356
357 static void spr_read_dbat_h (DisasContext *ctx, int gprn, int sprn)
358 {
359 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
360 }
361
362 static void spr_write_dbatu (DisasContext *ctx, int sprn, int gprn)
363 {
364 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
365 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
366 tcg_temp_free_i32(t0);
367 }
368
369 static void spr_write_dbatu_h (DisasContext *ctx, int sprn, int gprn)
370 {
371 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
372 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
373 tcg_temp_free_i32(t0);
374 }
375
376 static void spr_write_dbatl (DisasContext *ctx, int sprn, int gprn)
377 {
378 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
379 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
380 tcg_temp_free_i32(t0);
381 }
382
383 static void spr_write_dbatl_h (DisasContext *ctx, int sprn, int gprn)
384 {
385 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
386 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
387 tcg_temp_free_i32(t0);
388 }
389
390 /* SDR1 */
391 static void spr_write_sdr1 (DisasContext *ctx, int sprn, int gprn)
392 {
393 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
394 }
395
396 /* 64 bits PowerPC specific SPRs */
397 #if defined(TARGET_PPC64)
398 static void spr_read_hior (DisasContext *ctx, int gprn, int sprn)
399 {
400 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
401 }
402
403 static void spr_write_hior (DisasContext *ctx, int sprn, int gprn)
404 {
405 TCGv t0 = tcg_temp_new();
406 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
407 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
408 tcg_temp_free(t0);
409 }
410 #endif
411 #endif
412
413 /* PowerPC 601 specific registers */
414 /* RTC */
415 static void spr_read_601_rtcl (DisasContext *ctx, int gprn, int sprn)
416 {
417 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
418 }
419
420 static void spr_read_601_rtcu (DisasContext *ctx, int gprn, int sprn)
421 {
422 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
423 }
424
425 #if !defined(CONFIG_USER_ONLY)
426 static void spr_write_601_rtcu (DisasContext *ctx, int sprn, int gprn)
427 {
428 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
429 }
430
431 static void spr_write_601_rtcl (DisasContext *ctx, int sprn, int gprn)
432 {
433 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
434 }
435
436 static void spr_write_hid0_601 (DisasContext *ctx, int sprn, int gprn)
437 {
438 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
439 /* Must stop the translation as endianness may have changed */
440 gen_stop_exception(ctx);
441 }
442 #endif
443
444 /* Unified bats */
445 #if !defined(CONFIG_USER_ONLY)
446 static void spr_read_601_ubat (DisasContext *ctx, int gprn, int sprn)
447 {
448 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
449 }
450
451 static void spr_write_601_ubatu (DisasContext *ctx, int sprn, int gprn)
452 {
453 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
454 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
455 tcg_temp_free_i32(t0);
456 }
457
458 static void spr_write_601_ubatl (DisasContext *ctx, int sprn, int gprn)
459 {
460 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
461 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
462 tcg_temp_free_i32(t0);
463 }
464 #endif
465
466 /* PowerPC 40x specific registers */
467 #if !defined(CONFIG_USER_ONLY)
468 static void spr_read_40x_pit (DisasContext *ctx, int gprn, int sprn)
469 {
470 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
471 }
472
473 static void spr_write_40x_pit (DisasContext *ctx, int sprn, int gprn)
474 {
475 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
476 }
477
478 static void spr_write_40x_dbcr0 (DisasContext *ctx, int sprn, int gprn)
479 {
480 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
481 /* We must stop translation as we may have rebooted */
482 gen_stop_exception(ctx);
483 }
484
485 static void spr_write_40x_sler (DisasContext *ctx, int sprn, int gprn)
486 {
487 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
488 }
489
490 static void spr_write_booke_tcr (DisasContext *ctx, int sprn, int gprn)
491 {
492 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
493 }
494
495 static void spr_write_booke_tsr (DisasContext *ctx, int sprn, int gprn)
496 {
497 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
498 }
499 #endif
500
501 /* PowerPC 403 specific registers */
502 /* PBL1 / PBU1 / PBL2 / PBU2 */
503 #if !defined(CONFIG_USER_ONLY)
504 static void spr_read_403_pbr (DisasContext *ctx, int gprn, int sprn)
505 {
506 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
507 }
508
509 static void spr_write_403_pbr (DisasContext *ctx, int sprn, int gprn)
510 {
511 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
512 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
513 tcg_temp_free_i32(t0);
514 }
515
516 static void spr_write_pir (DisasContext *ctx, int sprn, int gprn)
517 {
518 TCGv t0 = tcg_temp_new();
519 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
520 gen_store_spr(SPR_PIR, t0);
521 tcg_temp_free(t0);
522 }
523 #endif
524
525 /* SPE specific registers */
526 static void spr_read_spefscr (DisasContext *ctx, int gprn, int sprn)
527 {
528 TCGv_i32 t0 = tcg_temp_new_i32();
529 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
530 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
531 tcg_temp_free_i32(t0);
532 }
533
534 static void spr_write_spefscr (DisasContext *ctx, int sprn, int gprn)
535 {
536 TCGv_i32 t0 = tcg_temp_new_i32();
537 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
538 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
539 tcg_temp_free_i32(t0);
540 }
541
542 #if !defined(CONFIG_USER_ONLY)
543 /* Callback used to write the exception vector base */
544 static void spr_write_excp_prefix (DisasContext *ctx, int sprn, int gprn)
545 {
546 TCGv t0 = tcg_temp_new();
547 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
548 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
549 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
550 gen_store_spr(sprn, t0);
551 tcg_temp_free(t0);
552 }
553
554 static void spr_write_excp_vector (DisasContext *ctx, int sprn, int gprn)
555 {
556 int sprn_offs;
557
558 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
559 sprn_offs = sprn - SPR_BOOKE_IVOR0;
560 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
561 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
562 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
563 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
564 } else {
565 printf("Trying to write an unknown exception vector %d %03x\n",
566 sprn, sprn);
567 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
568 return;
569 }
570
571 TCGv t0 = tcg_temp_new();
572 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
573 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
574 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
575 gen_store_spr(sprn, t0);
576 tcg_temp_free(t0);
577 }
578 #endif
579
580 static inline void vscr_init (CPUPPCState *env, uint32_t val)
581 {
582 env->vscr = val;
583 /* Altivec always uses round-to-nearest */
584 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
585 set_flush_to_zero(vscr_nj, &env->vec_status);
586 }
587
588 #ifdef CONFIG_USER_ONLY
589 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
590 oea_read, oea_write, one_reg_id, initial_value) \
591 _spr_register(env, num, name, uea_read, uea_write, initial_value)
592 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
593 oea_read, oea_write, hea_read, hea_write, \
594 one_reg_id, initial_value) \
595 _spr_register(env, num, name, uea_read, uea_write, initial_value)
596 #else
597 #if !defined(CONFIG_KVM)
598 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
599 oea_read, oea_write, one_reg_id, initial_value) \
600 _spr_register(env, num, name, uea_read, uea_write, \
601 oea_read, oea_write, oea_read, oea_write, initial_value)
602 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
603 oea_read, oea_write, hea_read, hea_write, \
604 one_reg_id, initial_value) \
605 _spr_register(env, num, name, uea_read, uea_write, \
606 oea_read, oea_write, hea_read, hea_write, initial_value)
607 #else
608 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
609 oea_read, oea_write, one_reg_id, initial_value) \
610 _spr_register(env, num, name, uea_read, uea_write, \
611 oea_read, oea_write, oea_read, oea_write, \
612 one_reg_id, initial_value)
613 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
614 oea_read, oea_write, hea_read, hea_write, \
615 one_reg_id, initial_value) \
616 _spr_register(env, num, name, uea_read, uea_write, \
617 oea_read, oea_write, hea_read, hea_write, \
618 one_reg_id, initial_value)
619 #endif
620 #endif
621
622 #define spr_register(env, num, name, uea_read, uea_write, \
623 oea_read, oea_write, initial_value) \
624 spr_register_kvm(env, num, name, uea_read, uea_write, \
625 oea_read, oea_write, 0, initial_value)
626
627 #define spr_register_hv(env, num, name, uea_read, uea_write, \
628 oea_read, oea_write, hea_read, hea_write, \
629 initial_value) \
630 spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
631 oea_read, oea_write, hea_read, hea_write, \
632 0, initial_value)
633
634 static inline void _spr_register(CPUPPCState *env, int num,
635 const char *name,
636 void (*uea_read)(DisasContext *ctx, int gprn, int sprn),
637 void (*uea_write)(DisasContext *ctx, int sprn, int gprn),
638 #if !defined(CONFIG_USER_ONLY)
639
640 void (*oea_read)(DisasContext *ctx, int gprn, int sprn),
641 void (*oea_write)(DisasContext *ctx, int sprn, int gprn),
642 void (*hea_read)(DisasContext *opaque, int gprn, int sprn),
643 void (*hea_write)(DisasContext *opaque, int sprn, int gprn),
644 #endif
645 #if defined(CONFIG_KVM)
646 uint64_t one_reg_id,
647 #endif
648 target_ulong initial_value)
649 {
650 ppc_spr_t *spr;
651
652 spr = &env->spr_cb[num];
653 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
654 #if !defined(CONFIG_USER_ONLY)
655 spr->oea_read != NULL || spr->oea_write != NULL ||
656 #endif
657 spr->uea_read != NULL || spr->uea_write != NULL) {
658 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
659 exit(1);
660 }
661 #if defined(PPC_DEBUG_SPR)
662 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
663 name, initial_value);
664 #endif
665 spr->name = name;
666 spr->uea_read = uea_read;
667 spr->uea_write = uea_write;
668 #if !defined(CONFIG_USER_ONLY)
669 spr->oea_read = oea_read;
670 spr->oea_write = oea_write;
671 spr->hea_read = hea_read;
672 spr->hea_write = hea_write;
673 #endif
674 #if defined(CONFIG_KVM)
675 spr->one_reg_id = one_reg_id,
676 #endif
677 env->spr[num] = spr->default_value = initial_value;
678 }
679
680 /* Generic PowerPC SPRs */
681 static void gen_spr_generic (CPUPPCState *env)
682 {
683 /* Integer processing */
684 spr_register(env, SPR_XER, "XER",
685 &spr_read_xer, &spr_write_xer,
686 &spr_read_xer, &spr_write_xer,
687 0x00000000);
688 /* Branch contol */
689 spr_register(env, SPR_LR, "LR",
690 &spr_read_lr, &spr_write_lr,
691 &spr_read_lr, &spr_write_lr,
692 0x00000000);
693 spr_register(env, SPR_CTR, "CTR",
694 &spr_read_ctr, &spr_write_ctr,
695 &spr_read_ctr, &spr_write_ctr,
696 0x00000000);
697 /* Interrupt processing */
698 spr_register(env, SPR_SRR0, "SRR0",
699 SPR_NOACCESS, SPR_NOACCESS,
700 &spr_read_generic, &spr_write_generic,
701 0x00000000);
702 spr_register(env, SPR_SRR1, "SRR1",
703 SPR_NOACCESS, SPR_NOACCESS,
704 &spr_read_generic, &spr_write_generic,
705 0x00000000);
706 /* Processor control */
707 spr_register(env, SPR_SPRG0, "SPRG0",
708 SPR_NOACCESS, SPR_NOACCESS,
709 &spr_read_generic, &spr_write_generic,
710 0x00000000);
711 spr_register(env, SPR_SPRG1, "SPRG1",
712 SPR_NOACCESS, SPR_NOACCESS,
713 &spr_read_generic, &spr_write_generic,
714 0x00000000);
715 spr_register(env, SPR_SPRG2, "SPRG2",
716 SPR_NOACCESS, SPR_NOACCESS,
717 &spr_read_generic, &spr_write_generic,
718 0x00000000);
719 spr_register(env, SPR_SPRG3, "SPRG3",
720 SPR_NOACCESS, SPR_NOACCESS,
721 &spr_read_generic, &spr_write_generic,
722 0x00000000);
723 }
724
725 /* SPR common to all non-embedded PowerPC, including 601 */
726 static void gen_spr_ne_601 (CPUPPCState *env)
727 {
728 /* Exception processing */
729 spr_register_kvm(env, SPR_DSISR, "DSISR",
730 SPR_NOACCESS, SPR_NOACCESS,
731 &spr_read_generic, &spr_write_generic,
732 KVM_REG_PPC_DSISR, 0x00000000);
733 spr_register_kvm(env, SPR_DAR, "DAR",
734 SPR_NOACCESS, SPR_NOACCESS,
735 &spr_read_generic, &spr_write_generic,
736 KVM_REG_PPC_DAR, 0x00000000);
737 /* Timer */
738 spr_register(env, SPR_DECR, "DECR",
739 SPR_NOACCESS, SPR_NOACCESS,
740 &spr_read_decr, &spr_write_decr,
741 0x00000000);
742 /* Memory management */
743 spr_register(env, SPR_SDR1, "SDR1",
744 SPR_NOACCESS, SPR_NOACCESS,
745 &spr_read_generic, &spr_write_sdr1,
746 0x00000000);
747 }
748
749 /* BATs 0-3 */
750 static void gen_low_BATs (CPUPPCState *env)
751 {
752 #if !defined(CONFIG_USER_ONLY)
753 spr_register(env, SPR_IBAT0U, "IBAT0U",
754 SPR_NOACCESS, SPR_NOACCESS,
755 &spr_read_ibat, &spr_write_ibatu,
756 0x00000000);
757 spr_register(env, SPR_IBAT0L, "IBAT0L",
758 SPR_NOACCESS, SPR_NOACCESS,
759 &spr_read_ibat, &spr_write_ibatl,
760 0x00000000);
761 spr_register(env, SPR_IBAT1U, "IBAT1U",
762 SPR_NOACCESS, SPR_NOACCESS,
763 &spr_read_ibat, &spr_write_ibatu,
764 0x00000000);
765 spr_register(env, SPR_IBAT1L, "IBAT1L",
766 SPR_NOACCESS, SPR_NOACCESS,
767 &spr_read_ibat, &spr_write_ibatl,
768 0x00000000);
769 spr_register(env, SPR_IBAT2U, "IBAT2U",
770 SPR_NOACCESS, SPR_NOACCESS,
771 &spr_read_ibat, &spr_write_ibatu,
772 0x00000000);
773 spr_register(env, SPR_IBAT2L, "IBAT2L",
774 SPR_NOACCESS, SPR_NOACCESS,
775 &spr_read_ibat, &spr_write_ibatl,
776 0x00000000);
777 spr_register(env, SPR_IBAT3U, "IBAT3U",
778 SPR_NOACCESS, SPR_NOACCESS,
779 &spr_read_ibat, &spr_write_ibatu,
780 0x00000000);
781 spr_register(env, SPR_IBAT3L, "IBAT3L",
782 SPR_NOACCESS, SPR_NOACCESS,
783 &spr_read_ibat, &spr_write_ibatl,
784 0x00000000);
785 spr_register(env, SPR_DBAT0U, "DBAT0U",
786 SPR_NOACCESS, SPR_NOACCESS,
787 &spr_read_dbat, &spr_write_dbatu,
788 0x00000000);
789 spr_register(env, SPR_DBAT0L, "DBAT0L",
790 SPR_NOACCESS, SPR_NOACCESS,
791 &spr_read_dbat, &spr_write_dbatl,
792 0x00000000);
793 spr_register(env, SPR_DBAT1U, "DBAT1U",
794 SPR_NOACCESS, SPR_NOACCESS,
795 &spr_read_dbat, &spr_write_dbatu,
796 0x00000000);
797 spr_register(env, SPR_DBAT1L, "DBAT1L",
798 SPR_NOACCESS, SPR_NOACCESS,
799 &spr_read_dbat, &spr_write_dbatl,
800 0x00000000);
801 spr_register(env, SPR_DBAT2U, "DBAT2U",
802 SPR_NOACCESS, SPR_NOACCESS,
803 &spr_read_dbat, &spr_write_dbatu,
804 0x00000000);
805 spr_register(env, SPR_DBAT2L, "DBAT2L",
806 SPR_NOACCESS, SPR_NOACCESS,
807 &spr_read_dbat, &spr_write_dbatl,
808 0x00000000);
809 spr_register(env, SPR_DBAT3U, "DBAT3U",
810 SPR_NOACCESS, SPR_NOACCESS,
811 &spr_read_dbat, &spr_write_dbatu,
812 0x00000000);
813 spr_register(env, SPR_DBAT3L, "DBAT3L",
814 SPR_NOACCESS, SPR_NOACCESS,
815 &spr_read_dbat, &spr_write_dbatl,
816 0x00000000);
817 env->nb_BATs += 4;
818 #endif
819 }
820
821 /* BATs 4-7 */
822 static void gen_high_BATs (CPUPPCState *env)
823 {
824 #if !defined(CONFIG_USER_ONLY)
825 spr_register(env, SPR_IBAT4U, "IBAT4U",
826 SPR_NOACCESS, SPR_NOACCESS,
827 &spr_read_ibat_h, &spr_write_ibatu_h,
828 0x00000000);
829 spr_register(env, SPR_IBAT4L, "IBAT4L",
830 SPR_NOACCESS, SPR_NOACCESS,
831 &spr_read_ibat_h, &spr_write_ibatl_h,
832 0x00000000);
833 spr_register(env, SPR_IBAT5U, "IBAT5U",
834 SPR_NOACCESS, SPR_NOACCESS,
835 &spr_read_ibat_h, &spr_write_ibatu_h,
836 0x00000000);
837 spr_register(env, SPR_IBAT5L, "IBAT5L",
838 SPR_NOACCESS, SPR_NOACCESS,
839 &spr_read_ibat_h, &spr_write_ibatl_h,
840 0x00000000);
841 spr_register(env, SPR_IBAT6U, "IBAT6U",
842 SPR_NOACCESS, SPR_NOACCESS,
843 &spr_read_ibat_h, &spr_write_ibatu_h,
844 0x00000000);
845 spr_register(env, SPR_IBAT6L, "IBAT6L",
846 SPR_NOACCESS, SPR_NOACCESS,
847 &spr_read_ibat_h, &spr_write_ibatl_h,
848 0x00000000);
849 spr_register(env, SPR_IBAT7U, "IBAT7U",
850 SPR_NOACCESS, SPR_NOACCESS,
851 &spr_read_ibat_h, &spr_write_ibatu_h,
852 0x00000000);
853 spr_register(env, SPR_IBAT7L, "IBAT7L",
854 SPR_NOACCESS, SPR_NOACCESS,
855 &spr_read_ibat_h, &spr_write_ibatl_h,
856 0x00000000);
857 spr_register(env, SPR_DBAT4U, "DBAT4U",
858 SPR_NOACCESS, SPR_NOACCESS,
859 &spr_read_dbat_h, &spr_write_dbatu_h,
860 0x00000000);
861 spr_register(env, SPR_DBAT4L, "DBAT4L",
862 SPR_NOACCESS, SPR_NOACCESS,
863 &spr_read_dbat_h, &spr_write_dbatl_h,
864 0x00000000);
865 spr_register(env, SPR_DBAT5U, "DBAT5U",
866 SPR_NOACCESS, SPR_NOACCESS,
867 &spr_read_dbat_h, &spr_write_dbatu_h,
868 0x00000000);
869 spr_register(env, SPR_DBAT5L, "DBAT5L",
870 SPR_NOACCESS, SPR_NOACCESS,
871 &spr_read_dbat_h, &spr_write_dbatl_h,
872 0x00000000);
873 spr_register(env, SPR_DBAT6U, "DBAT6U",
874 SPR_NOACCESS, SPR_NOACCESS,
875 &spr_read_dbat_h, &spr_write_dbatu_h,
876 0x00000000);
877 spr_register(env, SPR_DBAT6L, "DBAT6L",
878 SPR_NOACCESS, SPR_NOACCESS,
879 &spr_read_dbat_h, &spr_write_dbatl_h,
880 0x00000000);
881 spr_register(env, SPR_DBAT7U, "DBAT7U",
882 SPR_NOACCESS, SPR_NOACCESS,
883 &spr_read_dbat_h, &spr_write_dbatu_h,
884 0x00000000);
885 spr_register(env, SPR_DBAT7L, "DBAT7L",
886 SPR_NOACCESS, SPR_NOACCESS,
887 &spr_read_dbat_h, &spr_write_dbatl_h,
888 0x00000000);
889 env->nb_BATs += 4;
890 #endif
891 }
892
893 /* Generic PowerPC time base */
894 static void gen_tbl (CPUPPCState *env)
895 {
896 spr_register(env, SPR_VTBL, "TBL",
897 &spr_read_tbl, SPR_NOACCESS,
898 &spr_read_tbl, SPR_NOACCESS,
899 0x00000000);
900 spr_register(env, SPR_TBL, "TBL",
901 &spr_read_tbl, SPR_NOACCESS,
902 &spr_read_tbl, &spr_write_tbl,
903 0x00000000);
904 spr_register(env, SPR_VTBU, "TBU",
905 &spr_read_tbu, SPR_NOACCESS,
906 &spr_read_tbu, SPR_NOACCESS,
907 0x00000000);
908 spr_register(env, SPR_TBU, "TBU",
909 &spr_read_tbu, SPR_NOACCESS,
910 &spr_read_tbu, &spr_write_tbu,
911 0x00000000);
912 }
913
914 /* Softare table search registers */
915 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
916 {
917 #if !defined(CONFIG_USER_ONLY)
918 env->nb_tlb = nb_tlbs;
919 env->nb_ways = nb_ways;
920 env->id_tlbs = 1;
921 env->tlb_type = TLB_6XX;
922 spr_register(env, SPR_DMISS, "DMISS",
923 SPR_NOACCESS, SPR_NOACCESS,
924 &spr_read_generic, SPR_NOACCESS,
925 0x00000000);
926 spr_register(env, SPR_DCMP, "DCMP",
927 SPR_NOACCESS, SPR_NOACCESS,
928 &spr_read_generic, SPR_NOACCESS,
929 0x00000000);
930 spr_register(env, SPR_HASH1, "HASH1",
931 SPR_NOACCESS, SPR_NOACCESS,
932 &spr_read_generic, SPR_NOACCESS,
933 0x00000000);
934 spr_register(env, SPR_HASH2, "HASH2",
935 SPR_NOACCESS, SPR_NOACCESS,
936 &spr_read_generic, SPR_NOACCESS,
937 0x00000000);
938 spr_register(env, SPR_IMISS, "IMISS",
939 SPR_NOACCESS, SPR_NOACCESS,
940 &spr_read_generic, SPR_NOACCESS,
941 0x00000000);
942 spr_register(env, SPR_ICMP, "ICMP",
943 SPR_NOACCESS, SPR_NOACCESS,
944 &spr_read_generic, SPR_NOACCESS,
945 0x00000000);
946 spr_register(env, SPR_RPA, "RPA",
947 SPR_NOACCESS, SPR_NOACCESS,
948 &spr_read_generic, &spr_write_generic,
949 0x00000000);
950 #endif
951 }
952
953 /* SPR common to MPC755 and G2 */
954 static void gen_spr_G2_755 (CPUPPCState *env)
955 {
956 /* SGPRs */
957 spr_register(env, SPR_SPRG4, "SPRG4",
958 SPR_NOACCESS, SPR_NOACCESS,
959 &spr_read_generic, &spr_write_generic,
960 0x00000000);
961 spr_register(env, SPR_SPRG5, "SPRG5",
962 SPR_NOACCESS, SPR_NOACCESS,
963 &spr_read_generic, &spr_write_generic,
964 0x00000000);
965 spr_register(env, SPR_SPRG6, "SPRG6",
966 SPR_NOACCESS, SPR_NOACCESS,
967 &spr_read_generic, &spr_write_generic,
968 0x00000000);
969 spr_register(env, SPR_SPRG7, "SPRG7",
970 SPR_NOACCESS, SPR_NOACCESS,
971 &spr_read_generic, &spr_write_generic,
972 0x00000000);
973 }
974
975 /* SPR common to all 7xx PowerPC implementations */
976 static void gen_spr_7xx (CPUPPCState *env)
977 {
978 /* Breakpoints */
979 /* XXX : not implemented */
980 spr_register_kvm(env, SPR_DABR, "DABR",
981 SPR_NOACCESS, SPR_NOACCESS,
982 &spr_read_generic, &spr_write_generic,
983 KVM_REG_PPC_DABR, 0x00000000);
984 /* XXX : not implemented */
985 spr_register(env, SPR_IABR, "IABR",
986 SPR_NOACCESS, SPR_NOACCESS,
987 &spr_read_generic, &spr_write_generic,
988 0x00000000);
989 /* Cache management */
990 /* XXX : not implemented */
991 spr_register(env, SPR_ICTC, "ICTC",
992 SPR_NOACCESS, SPR_NOACCESS,
993 &spr_read_generic, &spr_write_generic,
994 0x00000000);
995 /* Performance monitors */
996 /* XXX : not implemented */
997 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
998 SPR_NOACCESS, SPR_NOACCESS,
999 &spr_read_generic, &spr_write_generic,
1000 0x00000000);
1001 /* XXX : not implemented */
1002 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
1003 SPR_NOACCESS, SPR_NOACCESS,
1004 &spr_read_generic, &spr_write_generic,
1005 0x00000000);
1006 /* XXX : not implemented */
1007 spr_register(env, SPR_7XX_PMC1, "PMC1",
1008 SPR_NOACCESS, SPR_NOACCESS,
1009 &spr_read_generic, &spr_write_generic,
1010 0x00000000);
1011 /* XXX : not implemented */
1012 spr_register(env, SPR_7XX_PMC2, "PMC2",
1013 SPR_NOACCESS, SPR_NOACCESS,
1014 &spr_read_generic, &spr_write_generic,
1015 0x00000000);
1016 /* XXX : not implemented */
1017 spr_register(env, SPR_7XX_PMC3, "PMC3",
1018 SPR_NOACCESS, SPR_NOACCESS,
1019 &spr_read_generic, &spr_write_generic,
1020 0x00000000);
1021 /* XXX : not implemented */
1022 spr_register(env, SPR_7XX_PMC4, "PMC4",
1023 SPR_NOACCESS, SPR_NOACCESS,
1024 &spr_read_generic, &spr_write_generic,
1025 0x00000000);
1026 /* XXX : not implemented */
1027 spr_register(env, SPR_7XX_SIAR, "SIAR",
1028 SPR_NOACCESS, SPR_NOACCESS,
1029 &spr_read_generic, SPR_NOACCESS,
1030 0x00000000);
1031 /* XXX : not implemented */
1032 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
1033 &spr_read_ureg, SPR_NOACCESS,
1034 &spr_read_ureg, SPR_NOACCESS,
1035 0x00000000);
1036 /* XXX : not implemented */
1037 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
1038 &spr_read_ureg, SPR_NOACCESS,
1039 &spr_read_ureg, SPR_NOACCESS,
1040 0x00000000);
1041 /* XXX : not implemented */
1042 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
1043 &spr_read_ureg, SPR_NOACCESS,
1044 &spr_read_ureg, SPR_NOACCESS,
1045 0x00000000);
1046 /* XXX : not implemented */
1047 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
1048 &spr_read_ureg, SPR_NOACCESS,
1049 &spr_read_ureg, SPR_NOACCESS,
1050 0x00000000);
1051 /* XXX : not implemented */
1052 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
1053 &spr_read_ureg, SPR_NOACCESS,
1054 &spr_read_ureg, SPR_NOACCESS,
1055 0x00000000);
1056 /* XXX : not implemented */
1057 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
1058 &spr_read_ureg, SPR_NOACCESS,
1059 &spr_read_ureg, SPR_NOACCESS,
1060 0x00000000);
1061 /* XXX : not implemented */
1062 spr_register(env, SPR_7XX_USIAR, "USIAR",
1063 &spr_read_ureg, SPR_NOACCESS,
1064 &spr_read_ureg, SPR_NOACCESS,
1065 0x00000000);
1066 /* External access control */
1067 /* XXX : not implemented */
1068 spr_register(env, SPR_EAR, "EAR",
1069 SPR_NOACCESS, SPR_NOACCESS,
1070 &spr_read_generic, &spr_write_generic,
1071 0x00000000);
1072 }
1073
1074 #ifdef TARGET_PPC64
1075 #ifndef CONFIG_USER_ONLY
1076 static void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
1077 {
1078 TCGv t0 = tcg_temp_new();
1079 TCGv t1 = tcg_temp_new();
1080 TCGv t2 = tcg_temp_new();
1081
1082 /* Note, the HV=1 PR=0 case is handled earlier by simply using
1083 * spr_write_generic for HV mode in the SPR table
1084 */
1085
1086 /* Build insertion mask into t1 based on context */
1087 if (ctx->pr) {
1088 gen_load_spr(t1, SPR_UAMOR);
1089 } else {
1090 gen_load_spr(t1, SPR_AMOR);
1091 }
1092
1093 /* Mask new bits into t2 */
1094 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1095
1096 /* Load AMR and clear new bits in t0 */
1097 gen_load_spr(t0, SPR_AMR);
1098 tcg_gen_andc_tl(t0, t0, t1);
1099
1100 /* Or'in new bits and write it out */
1101 tcg_gen_or_tl(t0, t0, t2);
1102 gen_store_spr(SPR_AMR, t0);
1103 spr_store_dump_spr(SPR_AMR);
1104
1105 tcg_temp_free(t0);
1106 tcg_temp_free(t1);
1107 tcg_temp_free(t2);
1108 }
1109
1110 static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
1111 {
1112 TCGv t0 = tcg_temp_new();
1113 TCGv t1 = tcg_temp_new();
1114 TCGv t2 = tcg_temp_new();
1115
1116 /* Note, the HV=1 case is handled earlier by simply using
1117 * spr_write_generic for HV mode in the SPR table
1118 */
1119
1120 /* Build insertion mask into t1 based on context */
1121 gen_load_spr(t1, SPR_AMOR);
1122
1123 /* Mask new bits into t2 */
1124 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1125
1126 /* Load AMR and clear new bits in t0 */
1127 gen_load_spr(t0, SPR_UAMOR);
1128 tcg_gen_andc_tl(t0, t0, t1);
1129
1130 /* Or'in new bits and write it out */
1131 tcg_gen_or_tl(t0, t0, t2);
1132 gen_store_spr(SPR_UAMOR, t0);
1133 spr_store_dump_spr(SPR_UAMOR);
1134
1135 tcg_temp_free(t0);
1136 tcg_temp_free(t1);
1137 tcg_temp_free(t2);
1138 }
1139
1140 static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
1141 {
1142 TCGv t0 = tcg_temp_new();
1143 TCGv t1 = tcg_temp_new();
1144 TCGv t2 = tcg_temp_new();
1145
1146 /* Note, the HV=1 case is handled earlier by simply using
1147 * spr_write_generic for HV mode in the SPR table
1148 */
1149
1150 /* Build insertion mask into t1 based on context */
1151 gen_load_spr(t1, SPR_AMOR);
1152
1153 /* Mask new bits into t2 */
1154 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1155
1156 /* Load AMR and clear new bits in t0 */
1157 gen_load_spr(t0, SPR_IAMR);
1158 tcg_gen_andc_tl(t0, t0, t1);
1159
1160 /* Or'in new bits and write it out */
1161 tcg_gen_or_tl(t0, t0, t2);
1162 gen_store_spr(SPR_IAMR, t0);
1163 spr_store_dump_spr(SPR_IAMR);
1164
1165 tcg_temp_free(t0);
1166 tcg_temp_free(t1);
1167 tcg_temp_free(t2);
1168 }
1169 #endif /* CONFIG_USER_ONLY */
1170
1171 static void gen_spr_amr(CPUPPCState *env, bool has_iamr)
1172 {
1173 #ifndef CONFIG_USER_ONLY
1174 /* Virtual Page Class Key protection */
1175 /* The AMR is accessible either via SPR 13 or SPR 29. 13 is
1176 * userspace accessible, 29 is privileged. So we only need to set
1177 * the kvm ONE_REG id on one of them, we use 29 */
1178 spr_register(env, SPR_UAMR, "UAMR",
1179 &spr_read_generic, &spr_write_amr,
1180 &spr_read_generic, &spr_write_amr,
1181 0);
1182 spr_register_kvm_hv(env, SPR_AMR, "AMR",
1183 SPR_NOACCESS, SPR_NOACCESS,
1184 &spr_read_generic, &spr_write_amr,
1185 &spr_read_generic, &spr_write_generic,
1186 KVM_REG_PPC_AMR, 0);
1187 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
1188 SPR_NOACCESS, SPR_NOACCESS,
1189 &spr_read_generic, &spr_write_uamor,
1190 &spr_read_generic, &spr_write_generic,
1191 KVM_REG_PPC_UAMOR, 0);
1192 spr_register_hv(env, SPR_AMOR, "AMOR",
1193 SPR_NOACCESS, SPR_NOACCESS,
1194 SPR_NOACCESS, SPR_NOACCESS,
1195 &spr_read_generic, &spr_write_generic,
1196 0);
1197 if (has_iamr) {
1198 spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
1199 SPR_NOACCESS, SPR_NOACCESS,
1200 &spr_read_generic, &spr_write_iamr,
1201 &spr_read_generic, &spr_write_generic,
1202 KVM_REG_PPC_IAMR, 0);
1203 }
1204 #endif /* !CONFIG_USER_ONLY */
1205 }
1206 #endif /* TARGET_PPC64 */
1207
1208 #ifndef CONFIG_USER_ONLY
1209 static void spr_read_thrm(DisasContext *ctx, int gprn, int sprn)
1210 {
1211 gen_helper_fixup_thrm(cpu_env);
1212 gen_load_spr(cpu_gpr[gprn], sprn);
1213 spr_load_dump_spr(sprn);
1214 }
1215 #endif /* !CONFIG_USER_ONLY */
1216
1217 static void gen_spr_thrm (CPUPPCState *env)
1218 {
1219 /* Thermal management */
1220 /* XXX : not implemented */
1221 spr_register(env, SPR_THRM1, "THRM1",
1222 SPR_NOACCESS, SPR_NOACCESS,
1223 &spr_read_thrm, &spr_write_generic,
1224 0x00000000);
1225 /* XXX : not implemented */
1226 spr_register(env, SPR_THRM2, "THRM2",
1227 SPR_NOACCESS, SPR_NOACCESS,
1228 &spr_read_thrm, &spr_write_generic,
1229 0x00000000);
1230 /* XXX : not implemented */
1231 spr_register(env, SPR_THRM3, "THRM3",
1232 SPR_NOACCESS, SPR_NOACCESS,
1233 &spr_read_thrm, &spr_write_generic,
1234 0x00000000);
1235 }
1236
1237 /* SPR specific to PowerPC 604 implementation */
1238 static void gen_spr_604 (CPUPPCState *env)
1239 {
1240 /* Processor identification */
1241 spr_register(env, SPR_PIR, "PIR",
1242 SPR_NOACCESS, SPR_NOACCESS,
1243 &spr_read_generic, &spr_write_pir,
1244 0x00000000);
1245 /* Breakpoints */
1246 /* XXX : not implemented */
1247 spr_register(env, SPR_IABR, "IABR",
1248 SPR_NOACCESS, SPR_NOACCESS,
1249 &spr_read_generic, &spr_write_generic,
1250 0x00000000);
1251 /* XXX : not implemented */
1252 spr_register_kvm(env, SPR_DABR, "DABR",
1253 SPR_NOACCESS, SPR_NOACCESS,
1254 &spr_read_generic, &spr_write_generic,
1255 KVM_REG_PPC_DABR, 0x00000000);
1256 /* Performance counters */
1257 /* XXX : not implemented */
1258 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
1259 SPR_NOACCESS, SPR_NOACCESS,
1260 &spr_read_generic, &spr_write_generic,
1261 0x00000000);
1262 /* XXX : not implemented */
1263 spr_register(env, SPR_7XX_PMC1, "PMC1",
1264 SPR_NOACCESS, SPR_NOACCESS,
1265 &spr_read_generic, &spr_write_generic,
1266 0x00000000);
1267 /* XXX : not implemented */
1268 spr_register(env, SPR_7XX_PMC2, "PMC2",
1269 SPR_NOACCESS, SPR_NOACCESS,
1270 &spr_read_generic, &spr_write_generic,
1271 0x00000000);
1272 /* XXX : not implemented */
1273 spr_register(env, SPR_7XX_SIAR, "SIAR",
1274 SPR_NOACCESS, SPR_NOACCESS,
1275 &spr_read_generic, SPR_NOACCESS,
1276 0x00000000);
1277 /* XXX : not implemented */
1278 spr_register(env, SPR_SDA, "SDA",
1279 SPR_NOACCESS, SPR_NOACCESS,
1280 &spr_read_generic, SPR_NOACCESS,
1281 0x00000000);
1282 /* External access control */
1283 /* XXX : not implemented */
1284 spr_register(env, SPR_EAR, "EAR",
1285 SPR_NOACCESS, SPR_NOACCESS,
1286 &spr_read_generic, &spr_write_generic,
1287 0x00000000);
1288 }
1289
1290 /* SPR specific to PowerPC 603 implementation */
1291 static void gen_spr_603 (CPUPPCState *env)
1292 {
1293 /* External access control */
1294 /* XXX : not implemented */
1295 spr_register(env, SPR_EAR, "EAR",
1296 SPR_NOACCESS, SPR_NOACCESS,
1297 &spr_read_generic, &spr_write_generic,
1298 0x00000000);
1299 /* Breakpoints */
1300 /* XXX : not implemented */
1301 spr_register(env, SPR_IABR, "IABR",
1302 SPR_NOACCESS, SPR_NOACCESS,
1303 &spr_read_generic, &spr_write_generic,
1304 0x00000000);
1305
1306 }
1307
1308 /* SPR specific to PowerPC G2 implementation */
1309 static void gen_spr_G2 (CPUPPCState *env)
1310 {
1311 /* Memory base address */
1312 /* MBAR */
1313 /* XXX : not implemented */
1314 spr_register(env, SPR_MBAR, "MBAR",
1315 SPR_NOACCESS, SPR_NOACCESS,
1316 &spr_read_generic, &spr_write_generic,
1317 0x00000000);
1318 /* Exception processing */
1319 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1320 SPR_NOACCESS, SPR_NOACCESS,
1321 &spr_read_generic, &spr_write_generic,
1322 0x00000000);
1323 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1324 SPR_NOACCESS, SPR_NOACCESS,
1325 &spr_read_generic, &spr_write_generic,
1326 0x00000000);
1327 /* Breakpoints */
1328 /* XXX : not implemented */
1329 spr_register(env, SPR_DABR, "DABR",
1330 SPR_NOACCESS, SPR_NOACCESS,
1331 &spr_read_generic, &spr_write_generic,
1332 0x00000000);
1333 /* XXX : not implemented */
1334 spr_register(env, SPR_DABR2, "DABR2",
1335 SPR_NOACCESS, SPR_NOACCESS,
1336 &spr_read_generic, &spr_write_generic,
1337 0x00000000);
1338 /* XXX : not implemented */
1339 spr_register(env, SPR_IABR, "IABR",
1340 SPR_NOACCESS, SPR_NOACCESS,
1341 &spr_read_generic, &spr_write_generic,
1342 0x00000000);
1343 /* XXX : not implemented */
1344 spr_register(env, SPR_IABR2, "IABR2",
1345 SPR_NOACCESS, SPR_NOACCESS,
1346 &spr_read_generic, &spr_write_generic,
1347 0x00000000);
1348 /* XXX : not implemented */
1349 spr_register(env, SPR_IBCR, "IBCR",
1350 SPR_NOACCESS, SPR_NOACCESS,
1351 &spr_read_generic, &spr_write_generic,
1352 0x00000000);
1353 /* XXX : not implemented */
1354 spr_register(env, SPR_DBCR, "DBCR",
1355 SPR_NOACCESS, SPR_NOACCESS,
1356 &spr_read_generic, &spr_write_generic,
1357 0x00000000);
1358 }
1359
1360 /* SPR specific to PowerPC 602 implementation */
1361 static void gen_spr_602 (CPUPPCState *env)
1362 {
1363 /* ESA registers */
1364 /* XXX : not implemented */
1365 spr_register(env, SPR_SER, "SER",
1366 SPR_NOACCESS, SPR_NOACCESS,
1367 &spr_read_generic, &spr_write_generic,
1368 0x00000000);
1369 /* XXX : not implemented */
1370 spr_register(env, SPR_SEBR, "SEBR",
1371 SPR_NOACCESS, SPR_NOACCESS,
1372 &spr_read_generic, &spr_write_generic,
1373 0x00000000);
1374 /* XXX : not implemented */
1375 spr_register(env, SPR_ESASRR, "ESASRR",
1376 SPR_NOACCESS, SPR_NOACCESS,
1377 &spr_read_generic, &spr_write_generic,
1378 0x00000000);
1379 /* Floating point status */
1380 /* XXX : not implemented */
1381 spr_register(env, SPR_SP, "SP",
1382 SPR_NOACCESS, SPR_NOACCESS,
1383 &spr_read_generic, &spr_write_generic,
1384 0x00000000);
1385 /* XXX : not implemented */
1386 spr_register(env, SPR_LT, "LT",
1387 SPR_NOACCESS, SPR_NOACCESS,
1388 &spr_read_generic, &spr_write_generic,
1389 0x00000000);
1390 /* Watchdog timer */
1391 /* XXX : not implemented */
1392 spr_register(env, SPR_TCR, "TCR",
1393 SPR_NOACCESS, SPR_NOACCESS,
1394 &spr_read_generic, &spr_write_generic,
1395 0x00000000);
1396 /* Interrupt base */
1397 spr_register(env, SPR_IBR, "IBR",
1398 SPR_NOACCESS, SPR_NOACCESS,
1399 &spr_read_generic, &spr_write_generic,
1400 0x00000000);
1401 /* XXX : not implemented */
1402 spr_register(env, SPR_IABR, "IABR",
1403 SPR_NOACCESS, SPR_NOACCESS,
1404 &spr_read_generic, &spr_write_generic,
1405 0x00000000);
1406 }
1407
1408 /* SPR specific to PowerPC 601 implementation */
1409 static void gen_spr_601 (CPUPPCState *env)
1410 {
1411 /* Multiplication/division register */
1412 /* MQ */
1413 spr_register(env, SPR_MQ, "MQ",
1414 &spr_read_generic, &spr_write_generic,
1415 &spr_read_generic, &spr_write_generic,
1416 0x00000000);
1417 /* RTC registers */
1418 spr_register(env, SPR_601_RTCU, "RTCU",
1419 SPR_NOACCESS, SPR_NOACCESS,
1420 SPR_NOACCESS, &spr_write_601_rtcu,
1421 0x00000000);
1422 spr_register(env, SPR_601_VRTCU, "RTCU",
1423 &spr_read_601_rtcu, SPR_NOACCESS,
1424 &spr_read_601_rtcu, SPR_NOACCESS,
1425 0x00000000);
1426 spr_register(env, SPR_601_RTCL, "RTCL",
1427 SPR_NOACCESS, SPR_NOACCESS,
1428 SPR_NOACCESS, &spr_write_601_rtcl,
1429 0x00000000);
1430 spr_register(env, SPR_601_VRTCL, "RTCL",
1431 &spr_read_601_rtcl, SPR_NOACCESS,
1432 &spr_read_601_rtcl, SPR_NOACCESS,
1433 0x00000000);
1434 /* Timer */
1435 #if 0 /* ? */
1436 spr_register(env, SPR_601_UDECR, "UDECR",
1437 &spr_read_decr, SPR_NOACCESS,
1438 &spr_read_decr, SPR_NOACCESS,
1439 0x00000000);
1440 #endif
1441 /* External access control */
1442 /* XXX : not implemented */
1443 spr_register(env, SPR_EAR, "EAR",
1444 SPR_NOACCESS, SPR_NOACCESS,
1445 &spr_read_generic, &spr_write_generic,
1446 0x00000000);
1447 /* Memory management */
1448 #if !defined(CONFIG_USER_ONLY)
1449 spr_register(env, SPR_IBAT0U, "IBAT0U",
1450 SPR_NOACCESS, SPR_NOACCESS,
1451 &spr_read_601_ubat, &spr_write_601_ubatu,
1452 0x00000000);
1453 spr_register(env, SPR_IBAT0L, "IBAT0L",
1454 SPR_NOACCESS, SPR_NOACCESS,
1455 &spr_read_601_ubat, &spr_write_601_ubatl,
1456 0x00000000);
1457 spr_register(env, SPR_IBAT1U, "IBAT1U",
1458 SPR_NOACCESS, SPR_NOACCESS,
1459 &spr_read_601_ubat, &spr_write_601_ubatu,
1460 0x00000000);
1461 spr_register(env, SPR_IBAT1L, "IBAT1L",
1462 SPR_NOACCESS, SPR_NOACCESS,
1463 &spr_read_601_ubat, &spr_write_601_ubatl,
1464 0x00000000);
1465 spr_register(env, SPR_IBAT2U, "IBAT2U",
1466 SPR_NOACCESS, SPR_NOACCESS,
1467 &spr_read_601_ubat, &spr_write_601_ubatu,
1468 0x00000000);
1469 spr_register(env, SPR_IBAT2L, "IBAT2L",
1470 SPR_NOACCESS, SPR_NOACCESS,
1471 &spr_read_601_ubat, &spr_write_601_ubatl,
1472 0x00000000);
1473 spr_register(env, SPR_IBAT3U, "IBAT3U",
1474 SPR_NOACCESS, SPR_NOACCESS,
1475 &spr_read_601_ubat, &spr_write_601_ubatu,
1476 0x00000000);
1477 spr_register(env, SPR_IBAT3L, "IBAT3L",
1478 SPR_NOACCESS, SPR_NOACCESS,
1479 &spr_read_601_ubat, &spr_write_601_ubatl,
1480 0x00000000);
1481 env->nb_BATs = 4;
1482 #endif
1483 }
1484
1485 static void gen_spr_74xx (CPUPPCState *env)
1486 {
1487 /* Processor identification */
1488 spr_register(env, SPR_PIR, "PIR",
1489 SPR_NOACCESS, SPR_NOACCESS,
1490 &spr_read_generic, &spr_write_pir,
1491 0x00000000);
1492 /* XXX : not implemented */
1493 spr_register(env, SPR_74XX_MMCR2, "MMCR2",
1494 SPR_NOACCESS, SPR_NOACCESS,
1495 &spr_read_generic, &spr_write_generic,
1496 0x00000000);
1497 /* XXX : not implemented */
1498 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
1499 &spr_read_ureg, SPR_NOACCESS,
1500 &spr_read_ureg, SPR_NOACCESS,
1501 0x00000000);
1502 /* XXX: not implemented */
1503 spr_register(env, SPR_BAMR, "BAMR",
1504 SPR_NOACCESS, SPR_NOACCESS,
1505 &spr_read_generic, &spr_write_generic,
1506 0x00000000);
1507 /* XXX : not implemented */
1508 spr_register(env, SPR_MSSCR0, "MSSCR0",
1509 SPR_NOACCESS, SPR_NOACCESS,
1510 &spr_read_generic, &spr_write_generic,
1511 0x00000000);
1512 /* Hardware implementation registers */
1513 /* XXX : not implemented */
1514 spr_register(env, SPR_HID0, "HID0",
1515 SPR_NOACCESS, SPR_NOACCESS,
1516 &spr_read_generic, &spr_write_generic,
1517 0x00000000);
1518 /* XXX : not implemented */
1519 spr_register(env, SPR_HID1, "HID1",
1520 SPR_NOACCESS, SPR_NOACCESS,
1521 &spr_read_generic, &spr_write_generic,
1522 0x00000000);
1523 /* Altivec */
1524 spr_register(env, SPR_VRSAVE, "VRSAVE",
1525 &spr_read_generic, &spr_write_generic,
1526 &spr_read_generic, &spr_write_generic,
1527 0x00000000);
1528 /* XXX : not implemented */
1529 spr_register(env, SPR_L2CR, "L2CR",
1530 SPR_NOACCESS, SPR_NOACCESS,
1531 &spr_read_generic, spr_access_nop,
1532 0x00000000);
1533 /* Not strictly an SPR */
1534 vscr_init(env, 0x00010000);
1535 }
1536
1537 static void gen_l3_ctrl (CPUPPCState *env)
1538 {
1539 /* L3CR */
1540 /* XXX : not implemented */
1541 spr_register(env, SPR_L3CR, "L3CR",
1542 SPR_NOACCESS, SPR_NOACCESS,
1543 &spr_read_generic, &spr_write_generic,
1544 0x00000000);
1545 /* L3ITCR0 */
1546 /* XXX : not implemented */
1547 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1548 SPR_NOACCESS, SPR_NOACCESS,
1549 &spr_read_generic, &spr_write_generic,
1550 0x00000000);
1551 /* L3PM */
1552 /* XXX : not implemented */
1553 spr_register(env, SPR_L3PM, "L3PM",
1554 SPR_NOACCESS, SPR_NOACCESS,
1555 &spr_read_generic, &spr_write_generic,
1556 0x00000000);
1557 }
1558
1559 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1560 {
1561 #if !defined(CONFIG_USER_ONLY)
1562 env->nb_tlb = nb_tlbs;
1563 env->nb_ways = nb_ways;
1564 env->id_tlbs = 1;
1565 env->tlb_type = TLB_6XX;
1566 /* XXX : not implemented */
1567 spr_register(env, SPR_PTEHI, "PTEHI",
1568 SPR_NOACCESS, SPR_NOACCESS,
1569 &spr_read_generic, &spr_write_generic,
1570 0x00000000);
1571 /* XXX : not implemented */
1572 spr_register(env, SPR_PTELO, "PTELO",
1573 SPR_NOACCESS, SPR_NOACCESS,
1574 &spr_read_generic, &spr_write_generic,
1575 0x00000000);
1576 /* XXX : not implemented */
1577 spr_register(env, SPR_TLBMISS, "TLBMISS",
1578 SPR_NOACCESS, SPR_NOACCESS,
1579 &spr_read_generic, &spr_write_generic,
1580 0x00000000);
1581 #endif
1582 }
1583
1584 #if !defined(CONFIG_USER_ONLY)
1585 static void spr_write_e500_l1csr0 (DisasContext *ctx, int sprn, int gprn)
1586 {
1587 TCGv t0 = tcg_temp_new();
1588
1589 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
1590 gen_store_spr(sprn, t0);
1591 tcg_temp_free(t0);
1592 }
1593
1594 static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
1595 {
1596 TCGv t0 = tcg_temp_new();
1597
1598 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
1599 gen_store_spr(sprn, t0);
1600 tcg_temp_free(t0);
1601 }
1602
1603 static void spr_write_booke206_mmucsr0 (DisasContext *ctx, int sprn, int gprn)
1604 {
1605 gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
1606 }
1607
1608 static void spr_write_booke_pid (DisasContext *ctx, int sprn, int gprn)
1609 {
1610 TCGv_i32 t0 = tcg_const_i32(sprn);
1611 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1612 tcg_temp_free_i32(t0);
1613 }
1614 #endif
1615
1616 static void gen_spr_usprgh (CPUPPCState *env)
1617 {
1618 spr_register(env, SPR_USPRG4, "USPRG4",
1619 &spr_read_ureg, SPR_NOACCESS,
1620 &spr_read_ureg, SPR_NOACCESS,
1621 0x00000000);
1622 spr_register(env, SPR_USPRG5, "USPRG5",
1623 &spr_read_ureg, SPR_NOACCESS,
1624 &spr_read_ureg, SPR_NOACCESS,
1625 0x00000000);
1626 spr_register(env, SPR_USPRG6, "USPRG6",
1627 &spr_read_ureg, SPR_NOACCESS,
1628 &spr_read_ureg, SPR_NOACCESS,
1629 0x00000000);
1630 spr_register(env, SPR_USPRG7, "USPRG7",
1631 &spr_read_ureg, SPR_NOACCESS,
1632 &spr_read_ureg, SPR_NOACCESS,
1633 0x00000000);
1634 }
1635
1636 /* PowerPC BookE SPR */
1637 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1638 {
1639 const char *ivor_names[64] = {
1640 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1641 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1642 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1643 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1644 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1645 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1646 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1647 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1648 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1649 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1650 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1651 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1652 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1653 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1654 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1655 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1656 };
1657 #define SPR_BOOKE_IVORxx (-1)
1658 int ivor_sprn[64] = {
1659 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1660 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1661 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1662 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1663 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1664 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1665 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1666 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1667 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1668 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1669 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1670 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1671 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1672 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1673 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1674 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1675 };
1676 int i;
1677
1678 /* Interrupt processing */
1679 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1680 SPR_NOACCESS, SPR_NOACCESS,
1681 &spr_read_generic, &spr_write_generic,
1682 0x00000000);
1683 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1684 SPR_NOACCESS, SPR_NOACCESS,
1685 &spr_read_generic, &spr_write_generic,
1686 0x00000000);
1687 /* Debug */
1688 /* XXX : not implemented */
1689 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1690 SPR_NOACCESS, SPR_NOACCESS,
1691 &spr_read_generic, &spr_write_generic,
1692 0x00000000);
1693 /* XXX : not implemented */
1694 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1695 SPR_NOACCESS, SPR_NOACCESS,
1696 &spr_read_generic, &spr_write_generic,
1697 0x00000000);
1698 /* XXX : not implemented */
1699 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1700 SPR_NOACCESS, SPR_NOACCESS,
1701 &spr_read_generic, &spr_write_generic,
1702 0x00000000);
1703 /* XXX : not implemented */
1704 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1705 SPR_NOACCESS, SPR_NOACCESS,
1706 &spr_read_generic, &spr_write_generic,
1707 0x00000000);
1708 /* XXX : not implemented */
1709 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1710 SPR_NOACCESS, SPR_NOACCESS,
1711 &spr_read_generic, &spr_write_40x_dbcr0,
1712 0x00000000);
1713 /* XXX : not implemented */
1714 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1715 SPR_NOACCESS, SPR_NOACCESS,
1716 &spr_read_generic, &spr_write_generic,
1717 0x00000000);
1718 /* XXX : not implemented */
1719 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1720 SPR_NOACCESS, SPR_NOACCESS,
1721 &spr_read_generic, &spr_write_generic,
1722 0x00000000);
1723 /* XXX : not implemented */
1724 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1725 SPR_NOACCESS, SPR_NOACCESS,
1726 &spr_read_generic, &spr_write_clear,
1727 0x00000000);
1728 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1729 SPR_NOACCESS, SPR_NOACCESS,
1730 &spr_read_generic, &spr_write_generic,
1731 0x00000000);
1732 spr_register(env, SPR_BOOKE_ESR, "ESR",
1733 SPR_NOACCESS, SPR_NOACCESS,
1734 &spr_read_generic, &spr_write_generic,
1735 0x00000000);
1736 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1737 SPR_NOACCESS, SPR_NOACCESS,
1738 &spr_read_generic, &spr_write_excp_prefix,
1739 0x00000000);
1740 /* Exception vectors */
1741 for (i = 0; i < 64; i++) {
1742 if (ivor_mask & (1ULL << i)) {
1743 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1744 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1745 exit(1);
1746 }
1747 spr_register(env, ivor_sprn[i], ivor_names[i],
1748 SPR_NOACCESS, SPR_NOACCESS,
1749 &spr_read_generic, &spr_write_excp_vector,
1750 0x00000000);
1751 }
1752 }
1753 spr_register(env, SPR_BOOKE_PID, "PID",
1754 SPR_NOACCESS, SPR_NOACCESS,
1755 &spr_read_generic, &spr_write_booke_pid,
1756 0x00000000);
1757 spr_register(env, SPR_BOOKE_TCR, "TCR",
1758 SPR_NOACCESS, SPR_NOACCESS,
1759 &spr_read_generic, &spr_write_booke_tcr,
1760 0x00000000);
1761 spr_register(env, SPR_BOOKE_TSR, "TSR",
1762 SPR_NOACCESS, SPR_NOACCESS,
1763 &spr_read_generic, &spr_write_booke_tsr,
1764 0x00000000);
1765 /* Timer */
1766 spr_register(env, SPR_DECR, "DECR",
1767 SPR_NOACCESS, SPR_NOACCESS,
1768 &spr_read_decr, &spr_write_decr,
1769 0x00000000);
1770 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1771 SPR_NOACCESS, SPR_NOACCESS,
1772 SPR_NOACCESS, &spr_write_generic,
1773 0x00000000);
1774 /* SPRGs */
1775 spr_register(env, SPR_USPRG0, "USPRG0",
1776 &spr_read_generic, &spr_write_generic,
1777 &spr_read_generic, &spr_write_generic,
1778 0x00000000);
1779 spr_register(env, SPR_SPRG4, "SPRG4",
1780 SPR_NOACCESS, SPR_NOACCESS,
1781 &spr_read_generic, &spr_write_generic,
1782 0x00000000);
1783 spr_register(env, SPR_SPRG5, "SPRG5",
1784 SPR_NOACCESS, SPR_NOACCESS,
1785 &spr_read_generic, &spr_write_generic,
1786 0x00000000);
1787 spr_register(env, SPR_SPRG6, "SPRG6",
1788 SPR_NOACCESS, SPR_NOACCESS,
1789 &spr_read_generic, &spr_write_generic,
1790 0x00000000);
1791 spr_register(env, SPR_SPRG7, "SPRG7",
1792 SPR_NOACCESS, SPR_NOACCESS,
1793 &spr_read_generic, &spr_write_generic,
1794 0x00000000);
1795 }
1796
1797 static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1798 uint32_t maxsize, uint32_t flags,
1799 uint32_t nentries)
1800 {
1801 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1802 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1803 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1804 flags | nentries;
1805 }
1806
1807 /* BookE 2.06 storage control registers */
1808 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1809 uint32_t *tlbncfg)
1810 {
1811 #if !defined(CONFIG_USER_ONLY)
1812 const char *mas_names[8] = {
1813 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1814 };
1815 int mas_sprn[8] = {
1816 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1817 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1818 };
1819 int i;
1820
1821 /* TLB assist registers */
1822 /* XXX : not implemented */
1823 for (i = 0; i < 8; i++) {
1824 void (*uea_write)(DisasContext *ctx, int sprn, int gprn) = &spr_write_generic32;
1825 if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1826 uea_write = &spr_write_generic;
1827 }
1828 if (mas_mask & (1 << i)) {
1829 spr_register(env, mas_sprn[i], mas_names[i],
1830 SPR_NOACCESS, SPR_NOACCESS,
1831 &spr_read_generic, uea_write,
1832 0x00000000);
1833 }
1834 }
1835 if (env->nb_pids > 1) {
1836 /* XXX : not implemented */
1837 spr_register(env, SPR_BOOKE_PID1, "PID1",
1838 SPR_NOACCESS, SPR_NOACCESS,
1839 &spr_read_generic, &spr_write_booke_pid,
1840 0x00000000);
1841 }
1842 if (env->nb_pids > 2) {
1843 /* XXX : not implemented */
1844 spr_register(env, SPR_BOOKE_PID2, "PID2",
1845 SPR_NOACCESS, SPR_NOACCESS,
1846 &spr_read_generic, &spr_write_booke_pid,
1847 0x00000000);
1848 }
1849 /* XXX : not implemented */
1850 spr_register(env, SPR_MMUCFG, "MMUCFG",
1851 SPR_NOACCESS, SPR_NOACCESS,
1852 &spr_read_generic, SPR_NOACCESS,
1853 0x00000000); /* TOFIX */
1854 switch (env->nb_ways) {
1855 case 4:
1856 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1857 SPR_NOACCESS, SPR_NOACCESS,
1858 &spr_read_generic, SPR_NOACCESS,
1859 tlbncfg[3]);
1860 /* Fallthru */
1861 case 3:
1862 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1863 SPR_NOACCESS, SPR_NOACCESS,
1864 &spr_read_generic, SPR_NOACCESS,
1865 tlbncfg[2]);
1866 /* Fallthru */
1867 case 2:
1868 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1869 SPR_NOACCESS, SPR_NOACCESS,
1870 &spr_read_generic, SPR_NOACCESS,
1871 tlbncfg[1]);
1872 /* Fallthru */
1873 case 1:
1874 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1875 SPR_NOACCESS, SPR_NOACCESS,
1876 &spr_read_generic, SPR_NOACCESS,
1877 tlbncfg[0]);
1878 /* Fallthru */
1879 case 0:
1880 default:
1881 break;
1882 }
1883 #endif
1884
1885 gen_spr_usprgh(env);
1886 }
1887
1888 /* SPR specific to PowerPC 440 implementation */
1889 static void gen_spr_440 (CPUPPCState *env)
1890 {
1891 /* Cache control */
1892 /* XXX : not implemented */
1893 spr_register(env, SPR_440_DNV0, "DNV0",
1894 SPR_NOACCESS, SPR_NOACCESS,
1895 &spr_read_generic, &spr_write_generic,
1896 0x00000000);
1897 /* XXX : not implemented */
1898 spr_register(env, SPR_440_DNV1, "DNV1",
1899 SPR_NOACCESS, SPR_NOACCESS,
1900 &spr_read_generic, &spr_write_generic,
1901 0x00000000);
1902 /* XXX : not implemented */
1903 spr_register(env, SPR_440_DNV2, "DNV2",
1904 SPR_NOACCESS, SPR_NOACCESS,
1905 &spr_read_generic, &spr_write_generic,
1906 0x00000000);
1907 /* XXX : not implemented */
1908 spr_register(env, SPR_440_DNV3, "DNV3",
1909 SPR_NOACCESS, SPR_NOACCESS,
1910 &spr_read_generic, &spr_write_generic,
1911 0x00000000);
1912 /* XXX : not implemented */
1913 spr_register(env, SPR_440_DTV0, "DTV0",
1914 SPR_NOACCESS, SPR_NOACCESS,
1915 &spr_read_generic, &spr_write_generic,
1916 0x00000000);
1917 /* XXX : not implemented */
1918 spr_register(env, SPR_440_DTV1, "DTV1",
1919 SPR_NOACCESS, SPR_NOACCESS,
1920 &spr_read_generic, &spr_write_generic,
1921 0x00000000);
1922 /* XXX : not implemented */
1923 spr_register(env, SPR_440_DTV2, "DTV2",
1924 SPR_NOACCESS, SPR_NOACCESS,
1925 &spr_read_generic, &spr_write_generic,
1926 0x00000000);
1927 /* XXX : not implemented */
1928 spr_register(env, SPR_440_DTV3, "DTV3",
1929 SPR_NOACCESS, SPR_NOACCESS,
1930 &spr_read_generic, &spr_write_generic,
1931 0x00000000);
1932 /* XXX : not implemented */
1933 spr_register(env, SPR_440_DVLIM, "DVLIM",
1934 SPR_NOACCESS, SPR_NOACCESS,
1935 &spr_read_generic, &spr_write_generic,
1936 0x00000000);
1937 /* XXX : not implemented */
1938 spr_register(env, SPR_440_INV0, "INV0",
1939 SPR_NOACCESS, SPR_NOACCESS,
1940 &spr_read_generic, &spr_write_generic,
1941 0x00000000);
1942 /* XXX : not implemented */
1943 spr_register(env, SPR_440_INV1, "INV1",
1944 SPR_NOACCESS, SPR_NOACCESS,
1945 &spr_read_generic, &spr_write_generic,
1946 0x00000000);
1947 /* XXX : not implemented */
1948 spr_register(env, SPR_440_INV2, "INV2",
1949 SPR_NOACCESS, SPR_NOACCESS,
1950 &spr_read_generic, &spr_write_generic,
1951 0x00000000);
1952 /* XXX : not implemented */
1953 spr_register(env, SPR_440_INV3, "INV3",
1954 SPR_NOACCESS, SPR_NOACCESS,
1955 &spr_read_generic, &spr_write_generic,
1956 0x00000000);
1957 /* XXX : not implemented */
1958 spr_register(env, SPR_440_ITV0, "ITV0",
1959 SPR_NOACCESS, SPR_NOACCESS,
1960 &spr_read_generic, &spr_write_generic,
1961 0x00000000);
1962 /* XXX : not implemented */
1963 spr_register(env, SPR_440_ITV1, "ITV1",
1964 SPR_NOACCESS, SPR_NOACCESS,
1965 &spr_read_generic, &spr_write_generic,
1966 0x00000000);
1967 /* XXX : not implemented */
1968 spr_register(env, SPR_440_ITV2, "ITV2",
1969 SPR_NOACCESS, SPR_NOACCESS,
1970 &spr_read_generic, &spr_write_generic,
1971 0x00000000);
1972 /* XXX : not implemented */
1973 spr_register(env, SPR_440_ITV3, "ITV3",
1974 SPR_NOACCESS, SPR_NOACCESS,
1975 &spr_read_generic, &spr_write_generic,
1976 0x00000000);
1977 /* XXX : not implemented */
1978 spr_register(env, SPR_440_IVLIM, "IVLIM",
1979 SPR_NOACCESS, SPR_NOACCESS,
1980 &spr_read_generic, &spr_write_generic,
1981 0x00000000);
1982 /* Cache debug */
1983 /* XXX : not implemented */
1984 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1985 SPR_NOACCESS, SPR_NOACCESS,
1986 &spr_read_generic, SPR_NOACCESS,
1987 0x00000000);
1988 /* XXX : not implemented */
1989 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1990 SPR_NOACCESS, SPR_NOACCESS,
1991 &spr_read_generic, SPR_NOACCESS,
1992 0x00000000);
1993 /* XXX : not implemented */
1994 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1995 SPR_NOACCESS, SPR_NOACCESS,
1996 &spr_read_generic, SPR_NOACCESS,
1997 0x00000000);
1998 /* XXX : not implemented */
1999 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
2000 SPR_NOACCESS, SPR_NOACCESS,
2001 &spr_read_generic, SPR_NOACCESS,
2002 0x00000000);
2003 /* XXX : not implemented */
2004 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
2005 SPR_NOACCESS, SPR_NOACCESS,
2006 &spr_read_generic, SPR_NOACCESS,
2007 0x00000000);
2008 /* XXX : not implemented */
2009 spr_register(env, SPR_440_DBDR, "DBDR",
2010 SPR_NOACCESS, SPR_NOACCESS,
2011 &spr_read_generic, &spr_write_generic,
2012 0x00000000);
2013 /* Processor control */
2014 spr_register(env, SPR_4xx_CCR0, "CCR0",
2015 SPR_NOACCESS, SPR_NOACCESS,
2016 &spr_read_generic, &spr_write_generic,
2017 0x00000000);
2018 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
2019 SPR_NOACCESS, SPR_NOACCESS,
2020 &spr_read_generic, SPR_NOACCESS,
2021 0x00000000);
2022 /* Storage control */
2023 spr_register(env, SPR_440_MMUCR, "MMUCR",
2024 SPR_NOACCESS, SPR_NOACCESS,
2025 &spr_read_generic, &spr_write_generic,
2026 0x00000000);
2027 }
2028
2029 /* SPR shared between PowerPC 40x implementations */
2030 static void gen_spr_40x (CPUPPCState *env)
2031 {
2032 /* Cache */
2033 /* not emulated, as QEMU do not emulate caches */
2034 spr_register(env, SPR_40x_DCCR, "DCCR",
2035 SPR_NOACCESS, SPR_NOACCESS,
2036 &spr_read_generic, &spr_write_generic,
2037 0x00000000);
2038 /* not emulated, as QEMU do not emulate caches */
2039 spr_register(env, SPR_40x_ICCR, "ICCR",
2040 SPR_NOACCESS, SPR_NOACCESS,
2041 &spr_read_generic, &spr_write_generic,
2042 0x00000000);
2043 /* not emulated, as QEMU do not emulate caches */
2044 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
2045 SPR_NOACCESS, SPR_NOACCESS,
2046 &spr_read_generic, SPR_NOACCESS,
2047 0x00000000);
2048 /* Exception */
2049 spr_register(env, SPR_40x_DEAR, "DEAR",
2050 SPR_NOACCESS, SPR_NOACCESS,
2051 &spr_read_generic, &spr_write_generic,
2052 0x00000000);
2053 spr_register(env, SPR_40x_ESR, "ESR",
2054 SPR_NOACCESS, SPR_NOACCESS,
2055 &spr_read_generic, &spr_write_generic,
2056 0x00000000);
2057 spr_register(env, SPR_40x_EVPR, "EVPR",
2058 SPR_NOACCESS, SPR_NOACCESS,
2059 &spr_read_generic, &spr_write_excp_prefix,
2060 0x00000000);
2061 spr_register(env, SPR_40x_SRR2, "SRR2",
2062 &spr_read_generic, &spr_write_generic,
2063 &spr_read_generic, &spr_write_generic,
2064 0x00000000);
2065 spr_register(env, SPR_40x_SRR3, "SRR3",
2066 &spr_read_generic, &spr_write_generic,
2067 &spr_read_generic, &spr_write_generic,
2068 0x00000000);
2069 /* Timers */
2070 spr_register(env, SPR_40x_PIT, "PIT",
2071 SPR_NOACCESS, SPR_NOACCESS,
2072 &spr_read_40x_pit, &spr_write_40x_pit,
2073 0x00000000);
2074 spr_register(env, SPR_40x_TCR, "TCR",
2075 SPR_NOACCESS, SPR_NOACCESS,
2076 &spr_read_generic, &spr_write_booke_tcr,
2077 0x00000000);
2078 spr_register(env, SPR_40x_TSR, "TSR",
2079 SPR_NOACCESS, SPR_NOACCESS,
2080 &spr_read_generic, &spr_write_booke_tsr,
2081 0x00000000);
2082 }
2083
2084 /* SPR specific to PowerPC 405 implementation */
2085 static void gen_spr_405 (CPUPPCState *env)
2086 {
2087 /* MMU */
2088 spr_register(env, SPR_40x_PID, "PID",
2089 SPR_NOACCESS, SPR_NOACCESS,
2090 &spr_read_generic, &spr_write_generic,
2091 0x00000000);
2092 spr_register(env, SPR_4xx_CCR0, "CCR0",
2093 SPR_NOACCESS, SPR_NOACCESS,
2094 &spr_read_generic, &spr_write_generic,
2095 0x00700000);
2096 /* Debug interface */
2097 /* XXX : not implemented */
2098 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2099 SPR_NOACCESS, SPR_NOACCESS,
2100 &spr_read_generic, &spr_write_40x_dbcr0,
2101 0x00000000);
2102 /* XXX : not implemented */
2103 spr_register(env, SPR_405_DBCR1, "DBCR1",
2104 SPR_NOACCESS, SPR_NOACCESS,
2105 &spr_read_generic, &spr_write_generic,
2106 0x00000000);
2107 /* XXX : not implemented */
2108 spr_register(env, SPR_40x_DBSR, "DBSR",
2109 SPR_NOACCESS, SPR_NOACCESS,
2110 &spr_read_generic, &spr_write_clear,
2111 /* Last reset was system reset */
2112 0x00000300);
2113 /* XXX : not implemented */
2114 spr_register(env, SPR_40x_DAC1, "DAC1",
2115 SPR_NOACCESS, SPR_NOACCESS,
2116 &spr_read_generic, &spr_write_generic,
2117 0x00000000);
2118 spr_register(env, SPR_40x_DAC2, "DAC2",
2119 SPR_NOACCESS, SPR_NOACCESS,
2120 &spr_read_generic, &spr_write_generic,
2121 0x00000000);
2122 /* XXX : not implemented */
2123 spr_register(env, SPR_405_DVC1, "DVC1",
2124 SPR_NOACCESS, SPR_NOACCESS,
2125 &spr_read_generic, &spr_write_generic,
2126 0x00000000);
2127 /* XXX : not implemented */
2128 spr_register(env, SPR_405_DVC2, "DVC2",
2129 SPR_NOACCESS, SPR_NOACCESS,
2130 &spr_read_generic, &spr_write_generic,
2131 0x00000000);
2132 /* XXX : not implemented */
2133 spr_register(env, SPR_40x_IAC1, "IAC1",
2134 SPR_NOACCESS, SPR_NOACCESS,
2135 &spr_read_generic, &spr_write_generic,
2136 0x00000000);
2137 spr_register(env, SPR_40x_IAC2, "IAC2",
2138 SPR_NOACCESS, SPR_NOACCESS,
2139 &spr_read_generic, &spr_write_generic,
2140 0x00000000);
2141 /* XXX : not implemented */
2142 spr_register(env, SPR_405_IAC3, "IAC3",
2143 SPR_NOACCESS, SPR_NOACCESS,
2144 &spr_read_generic, &spr_write_generic,
2145 0x00000000);
2146 /* XXX : not implemented */
2147 spr_register(env, SPR_405_IAC4, "IAC4",
2148 SPR_NOACCESS, SPR_NOACCESS,
2149 &spr_read_generic, &spr_write_generic,
2150 0x00000000);
2151 /* Storage control */
2152 /* XXX: TODO: not implemented */
2153 spr_register(env, SPR_405_SLER, "SLER",
2154 SPR_NOACCESS, SPR_NOACCESS,
2155 &spr_read_generic, &spr_write_40x_sler,
2156 0x00000000);
2157 spr_register(env, SPR_40x_ZPR, "ZPR",
2158 SPR_NOACCESS, SPR_NOACCESS,
2159 &spr_read_generic, &spr_write_generic,
2160 0x00000000);
2161 /* XXX : not implemented */
2162 spr_register(env, SPR_405_SU0R, "SU0R",
2163 SPR_NOACCESS, SPR_NOACCESS,
2164 &spr_read_generic, &spr_write_generic,
2165 0x00000000);
2166 /* SPRG */
2167 spr_register(env, SPR_USPRG0, "USPRG0",
2168 &spr_read_ureg, SPR_NOACCESS,
2169 &spr_read_ureg, SPR_NOACCESS,
2170 0x00000000);
2171 spr_register(env, SPR_SPRG4, "SPRG4",
2172 SPR_NOACCESS, SPR_NOACCESS,
2173 &spr_read_generic, &spr_write_generic,
2174 0x00000000);
2175 spr_register(env, SPR_SPRG5, "SPRG5",
2176 SPR_NOACCESS, SPR_NOACCESS,
2177 spr_read_generic, &spr_write_generic,
2178 0x00000000);
2179 spr_register(env, SPR_SPRG6, "SPRG6",
2180 SPR_NOACCESS, SPR_NOACCESS,
2181 spr_read_generic, &spr_write_generic,
2182 0x00000000);
2183 spr_register(env, SPR_SPRG7, "SPRG7",
2184 SPR_NOACCESS, SPR_NOACCESS,
2185 spr_read_generic, &spr_write_generic,
2186 0x00000000);
2187 gen_spr_usprgh(env);
2188 }
2189
2190 /* SPR shared between PowerPC 401 & 403 implementations */
2191 static void gen_spr_401_403 (CPUPPCState *env)
2192 {
2193 /* Time base */
2194 spr_register(env, SPR_403_VTBL, "TBL",
2195 &spr_read_tbl, SPR_NOACCESS,
2196 &spr_read_tbl, SPR_NOACCESS,
2197 0x00000000);
2198 spr_register(env, SPR_403_TBL, "TBL",
2199 SPR_NOACCESS, SPR_NOACCESS,
2200 SPR_NOACCESS, &spr_write_tbl,
2201 0x00000000);
2202 spr_register(env, SPR_403_VTBU, "TBU",
2203 &spr_read_tbu, SPR_NOACCESS,
2204 &spr_read_tbu, SPR_NOACCESS,
2205 0x00000000);
2206 spr_register(env, SPR_403_TBU, "TBU",
2207 SPR_NOACCESS, SPR_NOACCESS,
2208 SPR_NOACCESS, &spr_write_tbu,
2209 0x00000000);
2210 /* Debug */
2211 /* not emulated, as QEMU do not emulate caches */
2212 spr_register(env, SPR_403_CDBCR, "CDBCR",
2213 SPR_NOACCESS, SPR_NOACCESS,
2214 &spr_read_generic, &spr_write_generic,
2215 0x00000000);
2216 }
2217
2218 /* SPR specific to PowerPC 401 implementation */
2219 static void gen_spr_401 (CPUPPCState *env)
2220 {
2221 /* Debug interface */
2222 /* XXX : not implemented */
2223 spr_register(env, SPR_40x_DBCR0, "DBCR",
2224 SPR_NOACCESS, SPR_NOACCESS,
2225 &spr_read_generic, &spr_write_40x_dbcr0,
2226 0x00000000);
2227 /* XXX : not implemented */
2228 spr_register(env, SPR_40x_DBSR, "DBSR",
2229 SPR_NOACCESS, SPR_NOACCESS,
2230 &spr_read_generic, &spr_write_clear,
2231 /* Last reset was system reset */
2232 0x00000300);
2233 /* XXX : not implemented */
2234 spr_register(env, SPR_40x_DAC1, "DAC",
2235 SPR_NOACCESS, SPR_NOACCESS,
2236 &spr_read_generic, &spr_write_generic,
2237 0x00000000);
2238 /* XXX : not implemented */
2239 spr_register(env, SPR_40x_IAC1, "IAC",
2240 SPR_NOACCESS, SPR_NOACCESS,
2241 &spr_read_generic, &spr_write_generic,
2242 0x00000000);
2243 /* Storage control */
2244 /* XXX: TODO: not implemented */
2245 spr_register(env, SPR_405_SLER, "SLER",
2246 SPR_NOACCESS, SPR_NOACCESS,
2247 &spr_read_generic, &spr_write_40x_sler,
2248 0x00000000);
2249 /* not emulated, as QEMU never does speculative access */
2250 spr_register(env, SPR_40x_SGR, "SGR",
2251 SPR_NOACCESS, SPR_NOACCESS,
2252 &spr_read_generic, &spr_write_generic,
2253 0xFFFFFFFF);
2254 /* not emulated, as QEMU do not emulate caches */
2255 spr_register(env, SPR_40x_DCWR, "DCWR",
2256 SPR_NOACCESS, SPR_NOACCESS,
2257 &spr_read_generic, &spr_write_generic,
2258 0x00000000);
2259 }
2260
2261 static void gen_spr_401x2 (CPUPPCState *env)
2262 {
2263 gen_spr_401(env);
2264 spr_register(env, SPR_40x_PID, "PID",
2265 SPR_NOACCESS, SPR_NOACCESS,
2266 &spr_read_generic, &spr_write_generic,
2267 0x00000000);
2268 spr_register(env, SPR_40x_ZPR, "ZPR",
2269 SPR_NOACCESS, SPR_NOACCESS,
2270 &spr_read_generic, &spr_write_generic,
2271 0x00000000);
2272 }
2273
2274 /* SPR specific to PowerPC 403 implementation */
2275 static void gen_spr_403 (CPUPPCState *env)
2276 {
2277 /* Debug interface */
2278 /* XXX : not implemented */
2279 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2280 SPR_NOACCESS, SPR_NOACCESS,
2281 &spr_read_generic, &spr_write_40x_dbcr0,
2282 0x00000000);
2283 /* XXX : not implemented */
2284 spr_register(env, SPR_40x_DBSR, "DBSR",
2285 SPR_NOACCESS, SPR_NOACCESS,
2286 &spr_read_generic, &spr_write_clear,
2287 /* Last reset was system reset */
2288 0x00000300);
2289 /* XXX : not implemented */
2290 spr_register(env, SPR_40x_DAC1, "DAC1",
2291 SPR_NOACCESS, SPR_NOACCESS,
2292 &spr_read_generic, &spr_write_generic,
2293 0x00000000);
2294 /* XXX : not implemented */
2295 spr_register(env, SPR_40x_DAC2, "DAC2",
2296 SPR_NOACCESS, SPR_NOACCESS,
2297 &spr_read_generic, &spr_write_generic,
2298 0x00000000);
2299 /* XXX : not implemented */
2300 spr_register(env, SPR_40x_IAC1, "IAC1",
2301 SPR_NOACCESS, SPR_NOACCESS,
2302 &spr_read_generic, &spr_write_generic,
2303 0x00000000);
2304 /* XXX : not implemented */
2305 spr_register(env, SPR_40x_IAC2, "IAC2",
2306 SPR_NOACCESS, SPR_NOACCESS,
2307 &spr_read_generic, &spr_write_generic,
2308 0x00000000);
2309 }
2310
2311 static void gen_spr_403_real (CPUPPCState *env)
2312 {
2313 spr_register(env, SPR_403_PBL1, "PBL1",
2314 SPR_NOACCESS, SPR_NOACCESS,
2315 &spr_read_403_pbr, &spr_write_403_pbr,
2316 0x00000000);
2317 spr_register(env, SPR_403_PBU1, "PBU1",
2318 SPR_NOACCESS, SPR_NOACCESS,
2319 &spr_read_403_pbr, &spr_write_403_pbr,
2320 0x00000000);
2321 spr_register(env, SPR_403_PBL2, "PBL2",
2322 SPR_NOACCESS, SPR_NOACCESS,
2323 &spr_read_403_pbr, &spr_write_403_pbr,
2324 0x00000000);
2325 spr_register(env, SPR_403_PBU2, "PBU2",
2326 SPR_NOACCESS, SPR_NOACCESS,
2327 &spr_read_403_pbr, &spr_write_403_pbr,
2328 0x00000000);
2329 }
2330
2331 static void gen_spr_403_mmu (CPUPPCState *env)
2332 {
2333 /* MMU */
2334 spr_register(env, SPR_40x_PID, "PID",
2335 SPR_NOACCESS, SPR_NOACCESS,
2336 &spr_read_generic, &spr_write_generic,
2337 0x00000000);
2338 spr_register(env, SPR_40x_ZPR, "ZPR",
2339 SPR_NOACCESS, SPR_NOACCESS,
2340 &spr_read_generic, &spr_write_generic,
2341 0x00000000);
2342 }
2343
2344 /* SPR specific to PowerPC compression coprocessor extension */
2345 static void gen_spr_compress (CPUPPCState *env)
2346 {
2347 /* XXX : not implemented */
2348 spr_register(env, SPR_401_SKR, "SKR",
2349 SPR_NOACCESS, SPR_NOACCESS,
2350 &spr_read_generic, &spr_write_generic,
2351 0x00000000);
2352 }
2353
2354 static void gen_spr_5xx_8xx (CPUPPCState *env)
2355 {
2356 /* Exception processing */
2357 spr_register_kvm(env, SPR_DSISR, "DSISR",
2358 SPR_NOACCESS, SPR_NOACCESS,
2359 &spr_read_generic, &spr_write_generic,
2360 KVM_REG_PPC_DSISR, 0x00000000);
2361 spr_register_kvm(env, SPR_DAR, "DAR",
2362 SPR_NOACCESS, SPR_NOACCESS,
2363 &spr_read_generic, &spr_write_generic,
2364 KVM_REG_PPC_DAR, 0x00000000);
2365 /* Timer */
2366 spr_register(env, SPR_DECR, "DECR",
2367 SPR_NOACCESS, SPR_NOACCESS,
2368 &spr_read_decr, &spr_write_decr,
2369 0x00000000);
2370 /* XXX : not implemented */
2371 spr_register(env, SPR_MPC_EIE, "EIE",
2372 SPR_NOACCESS, SPR_NOACCESS,
2373 &spr_read_generic, &spr_write_generic,
2374 0x00000000);
2375 /* XXX : not implemented */
2376 spr_register(env, SPR_MPC_EID, "EID",
2377 SPR_NOACCESS, SPR_NOACCESS,
2378 &spr_read_generic, &spr_write_generic,
2379 0x00000000);
2380 /* XXX : not implemented */
2381 spr_register(env, SPR_MPC_NRI, "NRI",
2382 SPR_NOACCESS, SPR_NOACCESS,
2383 &spr_read_generic, &spr_write_generic,
2384 0x00000000);
2385 /* XXX : not implemented */
2386 spr_register(env, SPR_MPC_CMPA, "CMPA",
2387 SPR_NOACCESS, SPR_NOACCESS,
2388 &spr_read_generic, &spr_write_generic,
2389 0x00000000);
2390 /* XXX : not implemented */
2391 spr_register(env, SPR_MPC_CMPB, "CMPB",
2392 SPR_NOACCESS, SPR_NOACCESS,
2393 &spr_read_generic, &spr_write_generic,
2394 0x00000000);
2395 /* XXX : not implemented */
2396 spr_register(env, SPR_MPC_CMPC, "CMPC",
2397 SPR_NOACCESS, SPR_NOACCESS,
2398 &spr_read_generic, &spr_write_generic,
2399 0x00000000);
2400 /* XXX : not implemented */
2401 spr_register(env, SPR_MPC_CMPD, "CMPD",
2402 SPR_NOACCESS, SPR_NOACCESS,
2403 &spr_read_generic, &spr_write_generic,
2404 0x00000000);
2405 /* XXX : not implemented */
2406 spr_register(env, SPR_MPC_ECR, "ECR",
2407 SPR_NOACCESS, SPR_NOACCESS,
2408 &spr_read_generic, &spr_write_generic,
2409 0x00000000);
2410 /* XXX : not implemented */
2411 spr_register(env, SPR_MPC_DER, "DER",
2412 SPR_NOACCESS, SPR_NOACCESS,
2413 &spr_read_generic, &spr_write_generic,
2414 0x00000000);
2415 /* XXX : not implemented */
2416 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2417 SPR_NOACCESS, SPR_NOACCESS,
2418 &spr_read_generic, &spr_write_generic,
2419 0x00000000);
2420 /* XXX : not implemented */
2421 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2422 SPR_NOACCESS, SPR_NOACCESS,
2423 &spr_read_generic, &spr_write_generic,
2424 0x00000000);
2425 /* XXX : not implemented */
2426 spr_register(env, SPR_MPC_CMPE, "CMPE",
2427 SPR_NOACCESS, SPR_NOACCESS,
2428 &spr_read_generic, &spr_write_generic,
2429 0x00000000);
2430 /* XXX : not implemented */
2431 spr_register(env, SPR_MPC_CMPF, "CMPF",
2432 SPR_NOACCESS, SPR_NOACCESS,
2433 &spr_read_generic, &spr_write_generic,
2434 0x00000000);
2435 /* XXX : not implemented */
2436 spr_register(env, SPR_MPC_CMPG, "CMPG",
2437 SPR_NOACCESS, SPR_NOACCESS,
2438 &spr_read_generic, &spr_write_generic,
2439 0x00000000);
2440 /* XXX : not implemented */
2441 spr_register(env, SPR_MPC_CMPH, "CMPH",
2442 SPR_NOACCESS, SPR_NOACCESS,
2443 &spr_read_generic, &spr_write_generic,
2444 0x00000000);
2445 /* XXX : not implemented */
2446 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2447 SPR_NOACCESS, SPR_NOACCESS,
2448 &spr_read_generic, &spr_write_generic,
2449 0x00000000);
2450 /* XXX : not implemented */
2451 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2452 SPR_NOACCESS, SPR_NOACCESS,
2453 &spr_read_generic, &spr_write_generic,
2454 0x00000000);
2455 /* XXX : not implemented */
2456 spr_register(env, SPR_MPC_BAR, "BAR",
2457 SPR_NOACCESS, SPR_NOACCESS,
2458 &spr_read_generic, &spr_write_generic,
2459 0x00000000);
2460 /* XXX : not implemented */
2461 spr_register(env, SPR_MPC_DPDR, "DPDR",
2462 SPR_NOACCESS, SPR_NOACCESS,
2463 &spr_read_generic, &spr_write_generic,
2464 0x00000000);
2465 /* XXX : not implemented */
2466 spr_register(env, SPR_MPC_IMMR, "IMMR",
2467 SPR_NOACCESS, SPR_NOACCESS,
2468 &spr_read_generic, &spr_write_generic,
2469 0x00000000);
2470 }
2471
2472 static void gen_spr_5xx (CPUPPCState *env)
2473 {
2474 /* XXX : not implemented */
2475 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2476 SPR_NOACCESS, SPR_NOACCESS,
2477 &spr_read_generic, &spr_write_generic,
2478 0x00000000);
2479 /* XXX : not implemented */
2480 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2481 SPR_NOACCESS, SPR_NOACCESS,
2482 &spr_read_generic, &spr_write_generic,
2483 0x00000000);
2484 /* XXX : not implemented */
2485 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2486 SPR_NOACCESS, SPR_NOACCESS,
2487 &spr_read_generic, &spr_write_generic,
2488 0x00000000);
2489 /* XXX : not implemented */
2490 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2491 SPR_NOACCESS, SPR_NOACCESS,
2492 &spr_read_generic, &spr_write_generic,
2493 0x00000000);
2494 /* XXX : not implemented */
2495 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2496 SPR_NOACCESS, SPR_NOACCESS,
2497 &spr_read_generic, &spr_write_generic,
2498 0x00000000);
2499 /* XXX : not implemented */
2500 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2501 SPR_NOACCESS, SPR_NOACCESS,
2502 &spr_read_generic, &spr_write_generic,
2503 0x00000000);
2504 /* XXX : not implemented */
2505 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2506 SPR_NOACCESS, SPR_NOACCESS,
2507 &spr_read_generic, &spr_write_generic,
2508 0x00000000);
2509 /* XXX : not implemented */
2510 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2511 SPR_NOACCESS, SPR_NOACCESS,
2512 &spr_read_generic, &spr_write_generic,
2513 0x00000000);
2514 /* XXX : not implemented */
2515 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2516 SPR_NOACCESS, SPR_NOACCESS,
2517 &spr_read_generic, &spr_write_generic,
2518 0x00000000);
2519 /* XXX : not implemented */
2520 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2521 SPR_NOACCESS, SPR_NOACCESS,
2522 &spr_read_generic, &spr_write_generic,
2523 0x00000000);
2524 /* XXX : not implemented */
2525 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2526 SPR_NOACCESS, SPR_NOACCESS,
2527 &spr_read_generic, &spr_write_generic,
2528 0x00000000);
2529 /* XXX : not implemented */
2530 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2531 SPR_NOACCESS, SPR_NOACCESS,
2532 &spr_read_generic, &spr_write_generic,
2533 0x00000000);
2534 /* XXX : not implemented */
2535 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2536 SPR_NOACCESS, SPR_NOACCESS,
2537 &spr_read_generic, &spr_write_generic,
2538 0x00000000);
2539 /* XXX : not implemented */
2540 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2541 SPR_NOACCESS, SPR_NOACCESS,
2542 &spr_read_generic, &spr_write_generic,
2543 0x00000000);
2544 /* XXX : not implemented */
2545 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2546 SPR_NOACCESS, SPR_NOACCESS,
2547 &spr_read_generic, &spr_write_generic,
2548 0x00000000);
2549 /* XXX : not implemented */
2550 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2551 SPR_NOACCESS, SPR_NOACCESS,
2552 &spr_read_generic, &spr_write_generic,
2553 0x00000000);
2554 /* XXX : not implemented */
2555 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2556 SPR_NOACCESS, SPR_NOACCESS,
2557 &spr_read_generic, &spr_write_generic,
2558 0x00000000);
2559 /* XXX : not implemented */
2560 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2561 SPR_NOACCESS, SPR_NOACCESS,
2562 &spr_read_generic, &spr_write_generic,
2563 0x00000000);
2564 /* XXX : not implemented */
2565 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2566 SPR_NOACCESS, SPR_NOACCESS,
2567 &spr_read_generic, &spr_write_generic,
2568 0x00000000);
2569 /* XXX : not implemented */
2570 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2571 SPR_NOACCESS, SPR_NOACCESS,
2572 &spr_read_generic, &spr_write_generic,
2573 0x00000000);
2574 /* XXX : not implemented */
2575 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2576 SPR_NOACCESS, SPR_NOACCESS,
2577 &spr_read_generic, &spr_write_generic,
2578 0x00000000);
2579 }
2580
2581 static void gen_spr_8xx (CPUPPCState *env)
2582 {
2583 /* XXX : not implemented */
2584 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2585 SPR_NOACCESS, SPR_NOACCESS,
2586 &spr_read_generic, &spr_write_generic,
2587 0x00000000);
2588 /* XXX : not implemented */
2589 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2590 SPR_NOACCESS, SPR_NOACCESS,
2591 &spr_read_generic, &spr_write_generic,
2592 0x00000000);
2593 /* XXX : not implemented */
2594 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2595 SPR_NOACCESS, SPR_NOACCESS,
2596 &spr_read_generic, &spr_write_generic,
2597 0x00000000);
2598 /* XXX : not implemented */
2599 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2600 SPR_NOACCESS, SPR_NOACCESS,
2601 &spr_read_generic, &spr_write_generic,
2602 0x00000000);
2603 /* XXX : not implemented */
2604 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2605 SPR_NOACCESS, SPR_NOACCESS,
2606 &spr_read_generic, &spr_write_generic,
2607 0x00000000);
2608 /* XXX : not implemented */
2609 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2610 SPR_NOACCESS, SPR_NOACCESS,
2611 &spr_read_generic, &spr_write_generic,
2612 0x00000000);
2613 /* XXX : not implemented */
2614 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2615 SPR_NOACCESS, SPR_NOACCESS,
2616 &spr_read_generic, &spr_write_generic,
2617 0x00000000);
2618 /* XXX : not implemented */
2619 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2620 SPR_NOACCESS, SPR_NOACCESS,
2621 &spr_read_generic, &spr_write_generic,
2622 0x00000000);
2623 /* XXX : not implemented */
2624 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2625 SPR_NOACCESS, SPR_NOACCESS,
2626 &spr_read_generic, &spr_write_generic,
2627 0x00000000);
2628 /* XXX : not implemented */
2629 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2630 SPR_NOACCESS, SPR_NOACCESS,
2631 &spr_read_generic, &spr_write_generic,
2632 0x00000000);
2633 /* XXX : not implemented */
2634 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2635 SPR_NOACCESS, SPR_NOACCESS,
2636 &spr_read_generic, &spr_write_generic,
2637 0x00000000);
2638 /* XXX : not implemented */
2639 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2640 SPR_NOACCESS, SPR_NOACCESS,
2641 &spr_read_generic, &spr_write_generic,
2642 0x00000000);
2643 /* XXX : not implemented */
2644 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2645 SPR_NOACCESS, SPR_NOACCESS,
2646 &spr_read_generic, &spr_write_generic,
2647 0x00000000);
2648 /* XXX : not implemented */
2649 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2650 SPR_NOACCESS, SPR_NOACCESS,
2651 &spr_read_generic, &spr_write_generic,
2652 0x00000000);
2653 /* XXX : not implemented */
2654 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2655 SPR_NOACCESS, SPR_NOACCESS,
2656 &spr_read_generic, &spr_write_generic,
2657 0x00000000);
2658 /* XXX : not implemented */
2659 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2660 SPR_NOACCESS, SPR_NOACCESS,
2661 &spr_read_generic, &spr_write_generic,
2662 0x00000000);
2663 /* XXX : not implemented */
2664 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2665 SPR_NOACCESS, SPR_NOACCESS,
2666 &spr_read_generic, &spr_write_generic,
2667 0x00000000);
2668 /* XXX : not implemented */
2669 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2670 SPR_NOACCESS, SPR_NOACCESS,
2671 &spr_read_generic, &spr_write_generic,
2672 0x00000000);
2673 /* XXX : not implemented */
2674 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2675 SPR_NOACCESS, SPR_NOACCESS,
2676 &spr_read_generic, &spr_write_generic,
2677 0x00000000);
2678 /* XXX : not implemented */
2679 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2680 SPR_NOACCESS, SPR_NOACCESS,
2681 &spr_read_generic, &spr_write_generic,
2682 0x00000000);
2683 /* XXX : not implemented */
2684 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2685 SPR_NOACCESS, SPR_NOACCESS,
2686 &spr_read_generic, &spr_write_generic,
2687 0x00000000);
2688 /* XXX : not implemented */
2689 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2690 SPR_NOACCESS, SPR_NOACCESS,
2691 &spr_read_generic, &spr_write_generic,
2692 0x00000000);
2693 /* XXX : not implemented */
2694 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2695 SPR_NOACCESS, SPR_NOACCESS,
2696 &spr_read_generic, &spr_write_generic,
2697 0x00000000);
2698 /* XXX : not implemented */
2699 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2700 SPR_NOACCESS, SPR_NOACCESS,
2701 &spr_read_generic, &spr_write_generic,
2702 0x00000000);
2703 /* XXX : not implemented */
2704 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2705 SPR_NOACCESS, SPR_NOACCESS,
2706 &spr_read_generic, &spr_write_generic,
2707 0x00000000);
2708 }
2709
2710 // XXX: TODO
2711 /*
2712 * AMR => SPR 29 (Power 2.04)
2713 * CTRL => SPR 136 (Power 2.04)
2714 * CTRL => SPR 152 (Power 2.04)
2715 * SCOMC => SPR 276 (64 bits ?)
2716 * SCOMD => SPR 277 (64 bits ?)
2717 * TBU40 => SPR 286 (Power 2.04 hypv)
2718 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2719 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2720 * HDSISR => SPR 306 (Power 2.04 hypv)
2721 * HDAR => SPR 307 (Power 2.04 hypv)
2722 * PURR => SPR 309 (Power 2.04 hypv)
2723 * HDEC => SPR 310 (Power 2.04 hypv)
2724 * HIOR => SPR 311 (hypv)
2725 * RMOR => SPR 312 (970)
2726 * HRMOR => SPR 313 (Power 2.04 hypv)
2727 * HSRR0 => SPR 314 (Power 2.04 hypv)
2728 * HSRR1 => SPR 315 (Power 2.04 hypv)
2729 * LPIDR => SPR 317 (970)
2730 * EPR => SPR 702 (Power 2.04 emb)
2731 * perf => 768-783 (Power 2.04)
2732 * perf => 784-799 (Power 2.04)
2733 * PPR => SPR 896 (Power 2.04)
2734 * EPLC => SPR 947 (Power 2.04 emb)
2735 * EPSC => SPR 948 (Power 2.04 emb)
2736 * DABRX => 1015 (Power 2.04 hypv)
2737 * FPECR => SPR 1022 (?)
2738 * ... and more (thermal management, performance counters, ...)
2739 */
2740
2741 /*****************************************************************************/
2742 /* Exception vectors models */
2743 static void init_excp_4xx_real (CPUPPCState *env)
2744 {
2745 #if !defined(CONFIG_USER_ONLY)
2746 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2747 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2748 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2749 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2750 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2751 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2752 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2753 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2754 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2755 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2756 env->ivor_mask = 0x0000FFF0UL;
2757 env->ivpr_mask = 0xFFFF0000UL;
2758 /* Hardware reset vector */
2759 env->hreset_vector = 0xFFFFFFFCUL;
2760 #endif
2761 }
2762
2763 static void init_excp_4xx_softmmu (CPUPPCState *env)
2764 {
2765 #if !defined(CONFIG_USER_ONLY)
2766 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2767 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2768 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2769 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2770 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2771 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2772 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2773 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2774 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2775 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2776 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2777 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2778 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2779 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2780 env->ivor_mask = 0x0000FFF0UL;
2781 env->ivpr_mask = 0xFFFF0000UL;
2782 /* Hardware reset vector */
2783 env->hreset_vector = 0xFFFFFFFCUL;
2784 #endif
2785 }
2786
2787 static void init_excp_MPC5xx (CPUPPCState *env)
2788 {
2789 #if !defined(CONFIG_USER_ONLY)
2790 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2791 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2792 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2793 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2794 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2795 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2796 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2797 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2798 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2799 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2800 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2801 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2802 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2803 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2804 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2805 env->ivor_mask = 0x0000FFF0UL;
2806 env->ivpr_mask = 0xFFFF0000UL;
2807 /* Hardware reset vector */
2808 env->hreset_vector = 0x00000100UL;
2809 #endif
2810 }
2811
2812 static void init_excp_MPC8xx (CPUPPCState *env)
2813 {
2814 #if !defined(CONFIG_USER_ONLY)
2815 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2816 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2817 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2818 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2819 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2820 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2821 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2822 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2823 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2824 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2825 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2826 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2827 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2828 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2829 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2830 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2831 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2832 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2833 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2834 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2835 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2836 env->ivor_mask = 0x0000FFF0UL;
2837 env->ivpr_mask = 0xFFFF0000UL;
2838 /* Hardware reset vector */
2839 env->hreset_vector = 0x00000100UL;
2840 #endif
2841 }
2842
2843 static void init_excp_G2 (CPUPPCState *env)
2844 {
2845 #if !defined(CONFIG_USER_ONLY)
2846 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2847 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2848 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2849 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2850 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2851 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2852 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2853 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2854 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2855 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2856 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2857 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2858 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2859 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2860 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2861 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2862 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2863 /* Hardware reset vector */
2864 env->hreset_vector = 0x00000100UL;
2865 #endif
2866 }
2867
2868 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2869 {
2870 #if !defined(CONFIG_USER_ONLY)
2871 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2872 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2873 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2874 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2875 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2876 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2877 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2878 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2879 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2880 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2881 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2882 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2883 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2884 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2885 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2886 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2887 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2888 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2889 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2890 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2891 env->ivor_mask = 0x0000FFF7UL;
2892 env->ivpr_mask = ivpr_mask;
2893 /* Hardware reset vector */
2894 env->hreset_vector = 0xFFFFFFFCUL;
2895 #endif
2896 }
2897
2898 static void init_excp_BookE (CPUPPCState *env)
2899 {
2900 #if !defined(CONFIG_USER_ONLY)
2901 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2902 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2903 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2904 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2905 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2906 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2907 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2908 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2909 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2910 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2911 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2912 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2913 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2914 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2915 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2916 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2917 env->ivor_mask = 0x0000FFF0UL;
2918 env->ivpr_mask = 0xFFFF0000UL;
2919 /* Hardware reset vector */
2920 env->hreset_vector = 0xFFFFFFFCUL;
2921 #endif
2922 }
2923
2924 static void init_excp_601 (CPUPPCState *env)
2925 {
2926 #if !defined(CONFIG_USER_ONLY)
2927 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2928 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2929 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2930 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2931 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2932 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2933 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2934 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2935 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2936 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2937 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2938 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2939 /* Hardware reset vector */
2940 env->hreset_vector = 0x00000100UL;
2941 #endif
2942 }
2943
2944 static void init_excp_602 (CPUPPCState *env)
2945 {
2946 #if !defined(CONFIG_USER_ONLY)
2947 /* XXX: exception prefix has a special behavior on 602 */
2948 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2949 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2950 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2951 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2952 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2953 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2954 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2955 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2956 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2957 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2958 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2959 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2960 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2961 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2962 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2963 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2964 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2965 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2966 /* Hardware reset vector */
2967 env->hreset_vector = 0x00000100UL;
2968 #endif
2969 }
2970
2971 static void init_excp_603 (CPUPPCState *env)
2972 {
2973 #if !defined(CONFIG_USER_ONLY)
2974 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2975 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2976 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2977 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2978 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2979 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2980 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2981 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2982 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2983 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2984 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2985 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2986 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2987 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2988 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2989 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2990 /* Hardware reset vector */
2991 env->hreset_vector = 0x00000100UL;
2992 #endif
2993 }
2994
2995 static void init_excp_604 (CPUPPCState *env)
2996 {
2997 #if !defined(CONFIG_USER_ONLY)
2998 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2999 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3000 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3001 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3002 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3003 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3004 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3005 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3006 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3007 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3008 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3009 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3010 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3011 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3012 /* Hardware reset vector */
3013 env->hreset_vector = 0x00000100UL;
3014 #endif
3015 }
3016
3017 static void init_excp_7x0 (CPUPPCState *env)
3018 {
3019 #if !defined(CONFIG_USER_ONLY)
3020 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3021 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3022 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3023 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3024 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3025 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3026 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3027 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3028 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3029 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3030 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3031 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3032 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3033 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3034 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3035 /* Hardware reset vector */
3036 env->hreset_vector = 0x00000100UL;
3037 #endif
3038 }
3039
3040 static void init_excp_750cl (CPUPPCState *env)
3041 {
3042 #if !defined(CONFIG_USER_ONLY)
3043 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3044 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3045 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3046 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3047 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3048 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3049 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3050 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3051 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3052 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3053 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3054 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3055 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3056 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3057 /* Hardware reset vector */
3058 env->hreset_vector = 0x00000100UL;
3059 #endif
3060 }
3061
3062 static void init_excp_750cx (CPUPPCState *env)
3063 {
3064 #if !defined(CONFIG_USER_ONLY)
3065 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3066 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3067 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3068 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3069 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3070 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3071 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3072 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3073 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3074 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3075 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3076 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3077 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3078 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3079 /* Hardware reset vector */
3080 env->hreset_vector = 0x00000100UL;
3081 #endif
3082 }
3083
3084 /* XXX: Check if this is correct */
3085 static void init_excp_7x5 (CPUPPCState *env)
3086 {
3087 #if !defined(CONFIG_USER_ONLY)
3088 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3089 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3090 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3091 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3092 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3093 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3094 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3095 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3096 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3097 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3098 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3099 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3100 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3101 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3102 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3103 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3104 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3105 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3106 /* Hardware reset vector */
3107 env->hreset_vector = 0x00000100UL;
3108 #endif
3109 }
3110
3111 static void init_excp_7400 (CPUPPCState *env)
3112 {
3113 #if !defined(CONFIG_USER_ONLY)
3114 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3115 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3116 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3117 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3118 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3119 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3120 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3121 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3122 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3123 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3124 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3125 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3126 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3127 env-><