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target/ppc: Add do_unaligned_access hook
[qemu.git] / target / ppc / translate_init.inc.c
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "disas/bfd.h"
22 #include "exec/gdbstub.h"
23 #include "kvm_ppc.h"
24 #include "sysemu/arch_init.h"
25 #include "sysemu/cpus.h"
26 #include "sysemu/hw_accel.h"
27 #include "cpu-models.h"
28 #include "mmu-hash32.h"
29 #include "mmu-hash64.h"
30 #include "qemu/error-report.h"
31 #include "qapi/error.h"
32 #include "qapi/qmp/qnull.h"
33 #include "qapi/visitor.h"
34 #include "hw/qdev-properties.h"
35 #include "hw/ppc/ppc.h"
36 #include "mmu-book3s-v3.h"
37 #include "sysemu/qtest.h"
38 #include "qemu/cutils.h"
39 #include "disas/capstone.h"
40 #include "fpu/softfloat.h"
41
42 //#define PPC_DUMP_CPU
43 //#define PPC_DEBUG_SPR
44 //#define PPC_DUMP_SPR_ACCESSES
45 /* #define USE_APPLE_GDB */
46
47 /* Generic callbacks:
48 * do nothing but store/retrieve spr value
49 */
50 static void spr_load_dump_spr(int sprn)
51 {
52 #ifdef PPC_DUMP_SPR_ACCESSES
53 TCGv_i32 t0 = tcg_const_i32(sprn);
54 gen_helper_load_dump_spr(cpu_env, t0);
55 tcg_temp_free_i32(t0);
56 #endif
57 }
58
59 static void spr_read_generic (DisasContext *ctx, int gprn, int sprn)
60 {
61 gen_load_spr(cpu_gpr[gprn], sprn);
62 spr_load_dump_spr(sprn);
63 }
64
65 static void spr_store_dump_spr(int sprn)
66 {
67 #ifdef PPC_DUMP_SPR_ACCESSES
68 TCGv_i32 t0 = tcg_const_i32(sprn);
69 gen_helper_store_dump_spr(cpu_env, t0);
70 tcg_temp_free_i32(t0);
71 #endif
72 }
73
74 static void spr_write_generic(DisasContext *ctx, int sprn, int gprn)
75 {
76 gen_store_spr(sprn, cpu_gpr[gprn]);
77 spr_store_dump_spr(sprn);
78 }
79
80 #if !defined(CONFIG_USER_ONLY)
81 static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
82 {
83 #ifdef TARGET_PPC64
84 TCGv t0 = tcg_temp_new();
85 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
86 gen_store_spr(sprn, t0);
87 tcg_temp_free(t0);
88 spr_store_dump_spr(sprn);
89 #else
90 spr_write_generic(ctx, sprn, gprn);
91 #endif
92 }
93
94 static void spr_write_clear(DisasContext *ctx, int sprn, int gprn)
95 {
96 TCGv t0 = tcg_temp_new();
97 TCGv t1 = tcg_temp_new();
98 gen_load_spr(t0, sprn);
99 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
100 tcg_gen_and_tl(t0, t0, t1);
101 gen_store_spr(sprn, t0);
102 tcg_temp_free(t0);
103 tcg_temp_free(t1);
104 }
105
106 static void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
107 {
108 }
109
110 #endif
111
112 /* SPR common to all PowerPC */
113 /* XER */
114 static void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
115 {
116 gen_read_xer(ctx, cpu_gpr[gprn]);
117 }
118
119 static void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
120 {
121 gen_write_xer(cpu_gpr[gprn]);
122 }
123
124 /* LR */
125 static void spr_read_lr(DisasContext *ctx, int gprn, int sprn)
126 {
127 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
128 }
129
130 static void spr_write_lr(DisasContext *ctx, int sprn, int gprn)
131 {
132 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
133 }
134
135 /* CFAR */
136 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
137 static void spr_read_cfar(DisasContext *ctx, int gprn, int sprn)
138 {
139 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
140 }
141
142 static void spr_write_cfar(DisasContext *ctx, int sprn, int gprn)
143 {
144 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
145 }
146 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
147
148 /* CTR */
149 static void spr_read_ctr(DisasContext *ctx, int gprn, int sprn)
150 {
151 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
152 }
153
154 static void spr_write_ctr(DisasContext *ctx, int sprn, int gprn)
155 {
156 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
157 }
158
159 /* User read access to SPR */
160 /* USPRx */
161 /* UMMCRx */
162 /* UPMCx */
163 /* USIA */
164 /* UDECR */
165 static void spr_read_ureg(DisasContext *ctx, int gprn, int sprn)
166 {
167 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
168 }
169
170 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
171 static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
172 {
173 gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
174 }
175 #endif
176
177 /* SPR common to all non-embedded PowerPC */
178 /* DECR */
179 #if !defined(CONFIG_USER_ONLY)
180 static void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
181 {
182 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
183 gen_io_start();
184 }
185 gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
186 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
187 gen_io_end();
188 gen_stop_exception(ctx);
189 }
190 }
191
192 static void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
193 {
194 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
195 gen_io_start();
196 }
197 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
198 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
199 gen_io_end();
200 gen_stop_exception(ctx);
201 }
202 }
203 #endif
204
205 /* SPR common to all non-embedded PowerPC, except 601 */
206 /* Time base */
207 static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
208 {
209 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
210 gen_io_start();
211 }
212 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
213 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
214 gen_io_end();
215 gen_stop_exception(ctx);
216 }
217 }
218
219 static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
220 {
221 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
222 gen_io_start();
223 }
224 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
225 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
226 gen_io_end();
227 gen_stop_exception(ctx);
228 }
229 }
230
231 __attribute__ (( unused ))
232 static void spr_read_atbl(DisasContext *ctx, int gprn, int sprn)
233 {
234 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
235 }
236
237 __attribute__ (( unused ))
238 static void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
239 {
240 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
241 }
242
243 #if !defined(CONFIG_USER_ONLY)
244 static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
245 {
246 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
247 gen_io_start();
248 }
249 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
250 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
251 gen_io_end();
252 gen_stop_exception(ctx);
253 }
254 }
255
256 static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
257 {
258 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
259 gen_io_start();
260 }
261 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
262 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
263 gen_io_end();
264 gen_stop_exception(ctx);
265 }
266 }
267
268 __attribute__ (( unused ))
269 static void spr_write_atbl(DisasContext *ctx, int sprn, int gprn)
270 {
271 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
272 }
273
274 __attribute__ (( unused ))
275 static void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
276 {
277 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
278 }
279
280 #if defined(TARGET_PPC64)
281 __attribute__ (( unused ))
282 static void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
283 {
284 gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
285 }
286
287 /* HDECR */
288 static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
289 {
290 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
291 gen_io_start();
292 }
293 gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
294 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
295 gen_io_end();
296 gen_stop_exception(ctx);
297 }
298 }
299
300 static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
301 {
302 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
303 gen_io_start();
304 }
305 gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
306 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
307 gen_io_end();
308 gen_stop_exception(ctx);
309 }
310 }
311
312 #endif
313 #endif
314
315 #if !defined(CONFIG_USER_ONLY)
316 /* IBAT0U...IBAT0U */
317 /* IBAT0L...IBAT7L */
318 static void spr_read_ibat(DisasContext *ctx, int gprn, int sprn)
319 {
320 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
321 }
322
323 static void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn)
324 {
325 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
326 }
327
328 static void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn)
329 {
330 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
331 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
332 tcg_temp_free_i32(t0);
333 }
334
335 static void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn)
336 {
337 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
338 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
339 tcg_temp_free_i32(t0);
340 }
341
342 static void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn)
343 {
344 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
345 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
346 tcg_temp_free_i32(t0);
347 }
348
349 static void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
350 {
351 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
352 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
353 tcg_temp_free_i32(t0);
354 }
355
356 /* DBAT0U...DBAT7U */
357 /* DBAT0L...DBAT7L */
358 static void spr_read_dbat(DisasContext *ctx, int gprn, int sprn)
359 {
360 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
361 }
362
363 static void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn)
364 {
365 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
366 }
367
368 static void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn)
369 {
370 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
371 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
372 tcg_temp_free_i32(t0);
373 }
374
375 static void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn)
376 {
377 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
378 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
379 tcg_temp_free_i32(t0);
380 }
381
382 static void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn)
383 {
384 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
385 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
386 tcg_temp_free_i32(t0);
387 }
388
389 static void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn)
390 {
391 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
392 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
393 tcg_temp_free_i32(t0);
394 }
395
396 /* SDR1 */
397 static void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn)
398 {
399 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
400 }
401
402 #if defined(TARGET_PPC64)
403 /* 64 bits PowerPC specific SPRs */
404 /* PIDR */
405 static void spr_write_pidr(DisasContext *ctx, int sprn, int gprn)
406 {
407 gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]);
408 }
409
410 static void spr_read_hior(DisasContext *ctx, int gprn, int sprn)
411 {
412 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
413 }
414
415 static void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
416 {
417 TCGv t0 = tcg_temp_new();
418 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
419 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
420 tcg_temp_free(t0);
421 }
422 static void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
423 {
424 gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]);
425 }
426
427 static void spr_write_pcr(DisasContext *ctx, int sprn, int gprn)
428 {
429 gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]);
430 }
431 #endif
432 #endif
433
434 /* PowerPC 601 specific registers */
435 /* RTC */
436 static void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn)
437 {
438 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
439 }
440
441 static void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn)
442 {
443 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
444 }
445
446 #if !defined(CONFIG_USER_ONLY)
447 static void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn)
448 {
449 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
450 }
451
452 static void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn)
453 {
454 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
455 }
456
457 static void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn)
458 {
459 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
460 /* Must stop the translation as endianness may have changed */
461 gen_stop_exception(ctx);
462 }
463 #endif
464
465 /* Unified bats */
466 #if !defined(CONFIG_USER_ONLY)
467 static void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn)
468 {
469 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
470 }
471
472 static void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn)
473 {
474 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
475 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
476 tcg_temp_free_i32(t0);
477 }
478
479 static void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn)
480 {
481 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
482 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
483 tcg_temp_free_i32(t0);
484 }
485 #endif
486
487 /* PowerPC 40x specific registers */
488 #if !defined(CONFIG_USER_ONLY)
489 static void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
490 {
491 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
492 }
493
494 static void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
495 {
496 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
497 }
498
499 static void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
500 {
501 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
502 /* We must stop translation as we may have rebooted */
503 gen_stop_exception(ctx);
504 }
505
506 static void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
507 {
508 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
509 }
510
511 static void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
512 {
513 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
514 }
515
516 static void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
517 {
518 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
519 }
520 #endif
521
522 /* PowerPC 403 specific registers */
523 /* PBL1 / PBU1 / PBL2 / PBU2 */
524 #if !defined(CONFIG_USER_ONLY)
525 static void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn)
526 {
527 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
528 }
529
530 static void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn)
531 {
532 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
533 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
534 tcg_temp_free_i32(t0);
535 }
536
537 static void spr_write_pir(DisasContext *ctx, int sprn, int gprn)
538 {
539 TCGv t0 = tcg_temp_new();
540 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
541 gen_store_spr(SPR_PIR, t0);
542 tcg_temp_free(t0);
543 }
544 #endif
545
546 /* SPE specific registers */
547 static void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn)
548 {
549 TCGv_i32 t0 = tcg_temp_new_i32();
550 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
551 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
552 tcg_temp_free_i32(t0);
553 }
554
555 static void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn)
556 {
557 TCGv_i32 t0 = tcg_temp_new_i32();
558 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
559 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
560 tcg_temp_free_i32(t0);
561 }
562
563 #if !defined(CONFIG_USER_ONLY)
564 /* Callback used to write the exception vector base */
565 static void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn)
566 {
567 TCGv t0 = tcg_temp_new();
568 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
569 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
570 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
571 gen_store_spr(sprn, t0);
572 tcg_temp_free(t0);
573 }
574
575 static void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn)
576 {
577 int sprn_offs;
578
579 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
580 sprn_offs = sprn - SPR_BOOKE_IVOR0;
581 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
582 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
583 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
584 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
585 } else {
586 printf("Trying to write an unknown exception vector %d %03x\n",
587 sprn, sprn);
588 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
589 return;
590 }
591
592 TCGv t0 = tcg_temp_new();
593 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
594 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
595 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
596 gen_store_spr(sprn, t0);
597 tcg_temp_free(t0);
598 }
599 #endif
600
601 static inline void vscr_init(CPUPPCState *env, uint32_t val)
602 {
603 env->vscr = val;
604 /* Altivec always uses round-to-nearest */
605 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
606 set_flush_to_zero(vscr_nj, &env->vec_status);
607 }
608
609 #ifdef CONFIG_USER_ONLY
610 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
611 oea_read, oea_write, one_reg_id, initial_value) \
612 _spr_register(env, num, name, uea_read, uea_write, initial_value)
613 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
614 oea_read, oea_write, hea_read, hea_write, \
615 one_reg_id, initial_value) \
616 _spr_register(env, num, name, uea_read, uea_write, initial_value)
617 #else
618 #if !defined(CONFIG_KVM)
619 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
620 oea_read, oea_write, one_reg_id, initial_value) \
621 _spr_register(env, num, name, uea_read, uea_write, \
622 oea_read, oea_write, oea_read, oea_write, initial_value)
623 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
624 oea_read, oea_write, hea_read, hea_write, \
625 one_reg_id, initial_value) \
626 _spr_register(env, num, name, uea_read, uea_write, \
627 oea_read, oea_write, hea_read, hea_write, initial_value)
628 #else
629 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
630 oea_read, oea_write, one_reg_id, initial_value) \
631 _spr_register(env, num, name, uea_read, uea_write, \
632 oea_read, oea_write, oea_read, oea_write, \
633 one_reg_id, initial_value)
634 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
635 oea_read, oea_write, hea_read, hea_write, \
636 one_reg_id, initial_value) \
637 _spr_register(env, num, name, uea_read, uea_write, \
638 oea_read, oea_write, hea_read, hea_write, \
639 one_reg_id, initial_value)
640 #endif
641 #endif
642
643 #define spr_register(env, num, name, uea_read, uea_write, \
644 oea_read, oea_write, initial_value) \
645 spr_register_kvm(env, num, name, uea_read, uea_write, \
646 oea_read, oea_write, 0, initial_value)
647
648 #define spr_register_hv(env, num, name, uea_read, uea_write, \
649 oea_read, oea_write, hea_read, hea_write, \
650 initial_value) \
651 spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
652 oea_read, oea_write, hea_read, hea_write, \
653 0, initial_value)
654
655 static inline void _spr_register(CPUPPCState *env, int num,
656 const char *name,
657 void (*uea_read)(DisasContext *ctx, int gprn, int sprn),
658 void (*uea_write)(DisasContext *ctx, int sprn, int gprn),
659 #if !defined(CONFIG_USER_ONLY)
660
661 void (*oea_read)(DisasContext *ctx, int gprn, int sprn),
662 void (*oea_write)(DisasContext *ctx, int sprn, int gprn),
663 void (*hea_read)(DisasContext *opaque, int gprn, int sprn),
664 void (*hea_write)(DisasContext *opaque, int sprn, int gprn),
665 #endif
666 #if defined(CONFIG_KVM)
667 uint64_t one_reg_id,
668 #endif
669 target_ulong initial_value)
670 {
671 ppc_spr_t *spr;
672
673 spr = &env->spr_cb[num];
674 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
675 #if !defined(CONFIG_USER_ONLY)
676 spr->oea_read != NULL || spr->oea_write != NULL ||
677 #endif
678 spr->uea_read != NULL || spr->uea_write != NULL) {
679 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
680 exit(1);
681 }
682 #if defined(PPC_DEBUG_SPR)
683 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
684 name, initial_value);
685 #endif
686 spr->name = name;
687 spr->uea_read = uea_read;
688 spr->uea_write = uea_write;
689 #if !defined(CONFIG_USER_ONLY)
690 spr->oea_read = oea_read;
691 spr->oea_write = oea_write;
692 spr->hea_read = hea_read;
693 spr->hea_write = hea_write;
694 #endif
695 #if defined(CONFIG_KVM)
696 spr->one_reg_id = one_reg_id,
697 #endif
698 env->spr[num] = spr->default_value = initial_value;
699 }
700
701 /* Generic PowerPC SPRs */
702 static void gen_spr_generic(CPUPPCState *env)
703 {
704 /* Integer processing */
705 spr_register(env, SPR_XER, "XER",
706 &spr_read_xer, &spr_write_xer,
707 &spr_read_xer, &spr_write_xer,
708 0x00000000);
709 /* Branch contol */
710 spr_register(env, SPR_LR, "LR",
711 &spr_read_lr, &spr_write_lr,
712 &spr_read_lr, &spr_write_lr,
713 0x00000000);
714 spr_register(env, SPR_CTR, "CTR",
715 &spr_read_ctr, &spr_write_ctr,
716 &spr_read_ctr, &spr_write_ctr,
717 0x00000000);
718 /* Interrupt processing */
719 spr_register(env, SPR_SRR0, "SRR0",
720 SPR_NOACCESS, SPR_NOACCESS,
721 &spr_read_generic, &spr_write_generic,
722 0x00000000);
723 spr_register(env, SPR_SRR1, "SRR1",
724 SPR_NOACCESS, SPR_NOACCESS,
725 &spr_read_generic, &spr_write_generic,
726 0x00000000);
727 /* Processor control */
728 spr_register(env, SPR_SPRG0, "SPRG0",
729 SPR_NOACCESS, SPR_NOACCESS,
730 &spr_read_generic, &spr_write_generic,
731 0x00000000);
732 spr_register(env, SPR_SPRG1, "SPRG1",
733 SPR_NOACCESS, SPR_NOACCESS,
734 &spr_read_generic, &spr_write_generic,
735 0x00000000);
736 spr_register(env, SPR_SPRG2, "SPRG2",
737 SPR_NOACCESS, SPR_NOACCESS,
738 &spr_read_generic, &spr_write_generic,
739 0x00000000);
740 spr_register(env, SPR_SPRG3, "SPRG3",
741 SPR_NOACCESS, SPR_NOACCESS,
742 &spr_read_generic, &spr_write_generic,
743 0x00000000);
744 }
745
746 /* SPR common to all non-embedded PowerPC, including 601 */
747 static void gen_spr_ne_601(CPUPPCState *env)
748 {
749 /* Exception processing */
750 spr_register_kvm(env, SPR_DSISR, "DSISR",
751 SPR_NOACCESS, SPR_NOACCESS,
752 &spr_read_generic, &spr_write_generic,
753 KVM_REG_PPC_DSISR, 0x00000000);
754 spr_register_kvm(env, SPR_DAR, "DAR",
755 SPR_NOACCESS, SPR_NOACCESS,
756 &spr_read_generic, &spr_write_generic,
757 KVM_REG_PPC_DAR, 0x00000000);
758 /* Timer */
759 spr_register(env, SPR_DECR, "DECR",
760 SPR_NOACCESS, SPR_NOACCESS,
761 &spr_read_decr, &spr_write_decr,
762 0x00000000);
763 }
764
765 /* Storage Description Register 1 */
766 static void gen_spr_sdr1(CPUPPCState *env)
767 {
768 #ifndef CONFIG_USER_ONLY
769 if (env->has_hv_mode) {
770 /* SDR1 is a hypervisor resource on CPUs which have a
771 * hypervisor mode */
772 spr_register_hv(env, SPR_SDR1, "SDR1",
773 SPR_NOACCESS, SPR_NOACCESS,
774 SPR_NOACCESS, SPR_NOACCESS,
775 &spr_read_generic, &spr_write_sdr1,
776 0x00000000);
777 } else {
778 spr_register(env, SPR_SDR1, "SDR1",
779 SPR_NOACCESS, SPR_NOACCESS,
780 &spr_read_generic, &spr_write_sdr1,
781 0x00000000);
782 }
783 #endif
784 }
785
786 /* BATs 0-3 */
787 static void gen_low_BATs(CPUPPCState *env)
788 {
789 #if !defined(CONFIG_USER_ONLY)
790 spr_register(env, SPR_IBAT0U, "IBAT0U",
791 SPR_NOACCESS, SPR_NOACCESS,
792 &spr_read_ibat, &spr_write_ibatu,
793 0x00000000);
794 spr_register(env, SPR_IBAT0L, "IBAT0L",
795 SPR_NOACCESS, SPR_NOACCESS,
796 &spr_read_ibat, &spr_write_ibatl,
797 0x00000000);
798 spr_register(env, SPR_IBAT1U, "IBAT1U",
799 SPR_NOACCESS, SPR_NOACCESS,
800 &spr_read_ibat, &spr_write_ibatu,
801 0x00000000);
802 spr_register(env, SPR_IBAT1L, "IBAT1L",
803 SPR_NOACCESS, SPR_NOACCESS,
804 &spr_read_ibat, &spr_write_ibatl,
805 0x00000000);
806 spr_register(env, SPR_IBAT2U, "IBAT2U",
807 SPR_NOACCESS, SPR_NOACCESS,
808 &spr_read_ibat, &spr_write_ibatu,
809 0x00000000);
810 spr_register(env, SPR_IBAT2L, "IBAT2L",
811 SPR_NOACCESS, SPR_NOACCESS,
812 &spr_read_ibat, &spr_write_ibatl,
813 0x00000000);
814 spr_register(env, SPR_IBAT3U, "IBAT3U",
815 SPR_NOACCESS, SPR_NOACCESS,
816 &spr_read_ibat, &spr_write_ibatu,
817 0x00000000);
818 spr_register(env, SPR_IBAT3L, "IBAT3L",
819 SPR_NOACCESS, SPR_NOACCESS,
820 &spr_read_ibat, &spr_write_ibatl,
821 0x00000000);
822 spr_register(env, SPR_DBAT0U, "DBAT0U",
823 SPR_NOACCESS, SPR_NOACCESS,
824 &spr_read_dbat, &spr_write_dbatu,
825 0x00000000);
826 spr_register(env, SPR_DBAT0L, "DBAT0L",
827 SPR_NOACCESS, SPR_NOACCESS,
828 &spr_read_dbat, &spr_write_dbatl,
829 0x00000000);
830 spr_register(env, SPR_DBAT1U, "DBAT1U",
831 SPR_NOACCESS, SPR_NOACCESS,
832 &spr_read_dbat, &spr_write_dbatu,
833 0x00000000);
834 spr_register(env, SPR_DBAT1L, "DBAT1L",
835 SPR_NOACCESS, SPR_NOACCESS,
836 &spr_read_dbat, &spr_write_dbatl,
837 0x00000000);
838 spr_register(env, SPR_DBAT2U, "DBAT2U",
839 SPR_NOACCESS, SPR_NOACCESS,
840 &spr_read_dbat, &spr_write_dbatu,
841 0x00000000);
842 spr_register(env, SPR_DBAT2L, "DBAT2L",
843 SPR_NOACCESS, SPR_NOACCESS,
844 &spr_read_dbat, &spr_write_dbatl,
845 0x00000000);
846 spr_register(env, SPR_DBAT3U, "DBAT3U",
847 SPR_NOACCESS, SPR_NOACCESS,
848 &spr_read_dbat, &spr_write_dbatu,
849 0x00000000);
850 spr_register(env, SPR_DBAT3L, "DBAT3L",
851 SPR_NOACCESS, SPR_NOACCESS,
852 &spr_read_dbat, &spr_write_dbatl,
853 0x00000000);
854 env->nb_BATs += 4;
855 #endif
856 }
857
858 /* BATs 4-7 */
859 static void gen_high_BATs(CPUPPCState *env)
860 {
861 #if !defined(CONFIG_USER_ONLY)
862 spr_register(env, SPR_IBAT4U, "IBAT4U",
863 SPR_NOACCESS, SPR_NOACCESS,
864 &spr_read_ibat_h, &spr_write_ibatu_h,
865 0x00000000);
866 spr_register(env, SPR_IBAT4L, "IBAT4L",
867 SPR_NOACCESS, SPR_NOACCESS,
868 &spr_read_ibat_h, &spr_write_ibatl_h,
869 0x00000000);
870 spr_register(env, SPR_IBAT5U, "IBAT5U",
871 SPR_NOACCESS, SPR_NOACCESS,
872 &spr_read_ibat_h, &spr_write_ibatu_h,
873 0x00000000);
874 spr_register(env, SPR_IBAT5L, "IBAT5L",
875 SPR_NOACCESS, SPR_NOACCESS,
876 &spr_read_ibat_h, &spr_write_ibatl_h,
877 0x00000000);
878 spr_register(env, SPR_IBAT6U, "IBAT6U",
879 SPR_NOACCESS, SPR_NOACCESS,
880 &spr_read_ibat_h, &spr_write_ibatu_h,
881 0x00000000);
882 spr_register(env, SPR_IBAT6L, "IBAT6L",
883 SPR_NOACCESS, SPR_NOACCESS,
884 &spr_read_ibat_h, &spr_write_ibatl_h,
885 0x00000000);
886 spr_register(env, SPR_IBAT7U, "IBAT7U",
887 SPR_NOACCESS, SPR_NOACCESS,
888 &spr_read_ibat_h, &spr_write_ibatu_h,
889 0x00000000);
890 spr_register(env, SPR_IBAT7L, "IBAT7L",
891 SPR_NOACCESS, SPR_NOACCESS,
892 &spr_read_ibat_h, &spr_write_ibatl_h,
893 0x00000000);
894 spr_register(env, SPR_DBAT4U, "DBAT4U",
895 SPR_NOACCESS, SPR_NOACCESS,
896 &spr_read_dbat_h, &spr_write_dbatu_h,
897 0x00000000);
898 spr_register(env, SPR_DBAT4L, "DBAT4L",
899 SPR_NOACCESS, SPR_NOACCESS,
900 &spr_read_dbat_h, &spr_write_dbatl_h,
901 0x00000000);
902 spr_register(env, SPR_DBAT5U, "DBAT5U",
903 SPR_NOACCESS, SPR_NOACCESS,
904 &spr_read_dbat_h, &spr_write_dbatu_h,
905 0x00000000);
906 spr_register(env, SPR_DBAT5L, "DBAT5L",
907 SPR_NOACCESS, SPR_NOACCESS,
908 &spr_read_dbat_h, &spr_write_dbatl_h,
909 0x00000000);
910 spr_register(env, SPR_DBAT6U, "DBAT6U",
911 SPR_NOACCESS, SPR_NOACCESS,
912 &spr_read_dbat_h, &spr_write_dbatu_h,
913 0x00000000);
914 spr_register(env, SPR_DBAT6L, "DBAT6L",
915 SPR_NOACCESS, SPR_NOACCESS,
916 &spr_read_dbat_h, &spr_write_dbatl_h,
917 0x00000000);
918 spr_register(env, SPR_DBAT7U, "DBAT7U",
919 SPR_NOACCESS, SPR_NOACCESS,
920 &spr_read_dbat_h, &spr_write_dbatu_h,
921 0x00000000);
922 spr_register(env, SPR_DBAT7L, "DBAT7L",
923 SPR_NOACCESS, SPR_NOACCESS,
924 &spr_read_dbat_h, &spr_write_dbatl_h,
925 0x00000000);
926 env->nb_BATs += 4;
927 #endif
928 }
929
930 /* Generic PowerPC time base */
931 static void gen_tbl(CPUPPCState *env)
932 {
933 spr_register(env, SPR_VTBL, "TBL",
934 &spr_read_tbl, SPR_NOACCESS,
935 &spr_read_tbl, SPR_NOACCESS,
936 0x00000000);
937 spr_register(env, SPR_TBL, "TBL",
938 &spr_read_tbl, SPR_NOACCESS,
939 &spr_read_tbl, &spr_write_tbl,
940 0x00000000);
941 spr_register(env, SPR_VTBU, "TBU",
942 &spr_read_tbu, SPR_NOACCESS,
943 &spr_read_tbu, SPR_NOACCESS,
944 0x00000000);
945 spr_register(env, SPR_TBU, "TBU",
946 &spr_read_tbu, SPR_NOACCESS,
947 &spr_read_tbu, &spr_write_tbu,
948 0x00000000);
949 }
950
951 /* Softare table search registers */
952 static void gen_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
953 {
954 #if !defined(CONFIG_USER_ONLY)
955 env->nb_tlb = nb_tlbs;
956 env->nb_ways = nb_ways;
957 env->id_tlbs = 1;
958 env->tlb_type = TLB_6XX;
959 spr_register(env, SPR_DMISS, "DMISS",
960 SPR_NOACCESS, SPR_NOACCESS,
961 &spr_read_generic, SPR_NOACCESS,
962 0x00000000);
963 spr_register(env, SPR_DCMP, "DCMP",
964 SPR_NOACCESS, SPR_NOACCESS,
965 &spr_read_generic, SPR_NOACCESS,
966 0x00000000);
967 spr_register(env, SPR_HASH1, "HASH1",
968 SPR_NOACCESS, SPR_NOACCESS,
969 &spr_read_generic, SPR_NOACCESS,
970 0x00000000);
971 spr_register(env, SPR_HASH2, "HASH2",
972 SPR_NOACCESS, SPR_NOACCESS,
973 &spr_read_generic, SPR_NOACCESS,
974 0x00000000);
975 spr_register(env, SPR_IMISS, "IMISS",
976 SPR_NOACCESS, SPR_NOACCESS,
977 &spr_read_generic, SPR_NOACCESS,
978 0x00000000);
979 spr_register(env, SPR_ICMP, "ICMP",
980 SPR_NOACCESS, SPR_NOACCESS,
981 &spr_read_generic, SPR_NOACCESS,
982 0x00000000);
983 spr_register(env, SPR_RPA, "RPA",
984 SPR_NOACCESS, SPR_NOACCESS,
985 &spr_read_generic, &spr_write_generic,
986 0x00000000);
987 #endif
988 }
989
990 /* SPR common to MPC755 and G2 */
991 static void gen_spr_G2_755(CPUPPCState *env)
992 {
993 /* SGPRs */
994 spr_register(env, SPR_SPRG4, "SPRG4",
995 SPR_NOACCESS, SPR_NOACCESS,
996 &spr_read_generic, &spr_write_generic,
997 0x00000000);
998 spr_register(env, SPR_SPRG5, "SPRG5",
999 SPR_NOACCESS, SPR_NOACCESS,
1000 &spr_read_generic, &spr_write_generic,
1001 0x00000000);
1002 spr_register(env, SPR_SPRG6, "SPRG6",
1003 SPR_NOACCESS, SPR_NOACCESS,
1004 &spr_read_generic, &spr_write_generic,
1005 0x00000000);
1006 spr_register(env, SPR_SPRG7, "SPRG7",
1007 SPR_NOACCESS, SPR_NOACCESS,
1008 &spr_read_generic, &spr_write_generic,
1009 0x00000000);
1010 }
1011
1012 /* SPR common to all 7xx PowerPC implementations */
1013 static void gen_spr_7xx(CPUPPCState *env)
1014 {
1015 /* Breakpoints */
1016 /* XXX : not implemented */
1017 spr_register_kvm(env, SPR_DABR, "DABR",
1018 SPR_NOACCESS, SPR_NOACCESS,
1019 &spr_read_generic, &spr_write_generic,
1020 KVM_REG_PPC_DABR, 0x00000000);
1021 /* XXX : not implemented */
1022 spr_register(env, SPR_IABR, "IABR",
1023 SPR_NOACCESS, SPR_NOACCESS,
1024 &spr_read_generic, &spr_write_generic,
1025 0x00000000);
1026 /* Cache management */
1027 /* XXX : not implemented */
1028 spr_register(env, SPR_ICTC, "ICTC",
1029 SPR_NOACCESS, SPR_NOACCESS,
1030 &spr_read_generic, &spr_write_generic,
1031 0x00000000);
1032 /* Performance monitors */
1033 /* XXX : not implemented */
1034 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
1035 SPR_NOACCESS, SPR_NOACCESS,
1036 &spr_read_generic, &spr_write_generic,
1037 0x00000000);
1038 /* XXX : not implemented */
1039 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
1040 SPR_NOACCESS, SPR_NOACCESS,
1041 &spr_read_generic, &spr_write_generic,
1042 0x00000000);
1043 /* XXX : not implemented */
1044 spr_register(env, SPR_7XX_PMC1, "PMC1",
1045 SPR_NOACCESS, SPR_NOACCESS,
1046 &spr_read_generic, &spr_write_generic,
1047 0x00000000);
1048 /* XXX : not implemented */
1049 spr_register(env, SPR_7XX_PMC2, "PMC2",
1050 SPR_NOACCESS, SPR_NOACCESS,
1051 &spr_read_generic, &spr_write_generic,
1052 0x00000000);
1053 /* XXX : not implemented */
1054 spr_register(env, SPR_7XX_PMC3, "PMC3",
1055 SPR_NOACCESS, SPR_NOACCESS,
1056 &spr_read_generic, &spr_write_generic,
1057 0x00000000);
1058 /* XXX : not implemented */
1059 spr_register(env, SPR_7XX_PMC4, "PMC4",
1060 SPR_NOACCESS, SPR_NOACCESS,
1061 &spr_read_generic, &spr_write_generic,
1062 0x00000000);
1063 /* XXX : not implemented */
1064 spr_register(env, SPR_7XX_SIAR, "SIAR",
1065 SPR_NOACCESS, SPR_NOACCESS,
1066 &spr_read_generic, SPR_NOACCESS,
1067 0x00000000);
1068 /* XXX : not implemented */
1069 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
1070 &spr_read_ureg, SPR_NOACCESS,
1071 &spr_read_ureg, SPR_NOACCESS,
1072 0x00000000);
1073 /* XXX : not implemented */
1074 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
1075 &spr_read_ureg, SPR_NOACCESS,
1076 &spr_read_ureg, SPR_NOACCESS,
1077 0x00000000);
1078 /* XXX : not implemented */
1079 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
1080 &spr_read_ureg, SPR_NOACCESS,
1081 &spr_read_ureg, SPR_NOACCESS,
1082 0x00000000);
1083 /* XXX : not implemented */
1084 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
1085 &spr_read_ureg, SPR_NOACCESS,
1086 &spr_read_ureg, SPR_NOACCESS,
1087 0x00000000);
1088 /* XXX : not implemented */
1089 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
1090 &spr_read_ureg, SPR_NOACCESS,
1091 &spr_read_ureg, SPR_NOACCESS,
1092 0x00000000);
1093 /* XXX : not implemented */
1094 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
1095 &spr_read_ureg, SPR_NOACCESS,
1096 &spr_read_ureg, SPR_NOACCESS,
1097 0x00000000);
1098 /* XXX : not implemented */
1099 spr_register(env, SPR_7XX_USIAR, "USIAR",
1100 &spr_read_ureg, SPR_NOACCESS,
1101 &spr_read_ureg, SPR_NOACCESS,
1102 0x00000000);
1103 /* External access control */
1104 /* XXX : not implemented */
1105 spr_register(env, SPR_EAR, "EAR",
1106 SPR_NOACCESS, SPR_NOACCESS,
1107 &spr_read_generic, &spr_write_generic,
1108 0x00000000);
1109 }
1110
1111 #ifdef TARGET_PPC64
1112 #ifndef CONFIG_USER_ONLY
1113 static void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
1114 {
1115 TCGv t0 = tcg_temp_new();
1116 TCGv t1 = tcg_temp_new();
1117 TCGv t2 = tcg_temp_new();
1118
1119 /* Note, the HV=1 PR=0 case is handled earlier by simply using
1120 * spr_write_generic for HV mode in the SPR table
1121 */
1122
1123 /* Build insertion mask into t1 based on context */
1124 if (ctx->pr) {
1125 gen_load_spr(t1, SPR_UAMOR);
1126 } else {
1127 gen_load_spr(t1, SPR_AMOR);
1128 }
1129
1130 /* Mask new bits into t2 */
1131 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1132
1133 /* Load AMR and clear new bits in t0 */
1134 gen_load_spr(t0, SPR_AMR);
1135 tcg_gen_andc_tl(t0, t0, t1);
1136
1137 /* Or'in new bits and write it out */
1138 tcg_gen_or_tl(t0, t0, t2);
1139 gen_store_spr(SPR_AMR, t0);
1140 spr_store_dump_spr(SPR_AMR);
1141
1142 tcg_temp_free(t0);
1143 tcg_temp_free(t1);
1144 tcg_temp_free(t2);
1145 }
1146
1147 static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
1148 {
1149 TCGv t0 = tcg_temp_new();
1150 TCGv t1 = tcg_temp_new();
1151 TCGv t2 = tcg_temp_new();
1152
1153 /* Note, the HV=1 case is handled earlier by simply using
1154 * spr_write_generic for HV mode in the SPR table
1155 */
1156
1157 /* Build insertion mask into t1 based on context */
1158 gen_load_spr(t1, SPR_AMOR);
1159
1160 /* Mask new bits into t2 */
1161 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1162
1163 /* Load AMR and clear new bits in t0 */
1164 gen_load_spr(t0, SPR_UAMOR);
1165 tcg_gen_andc_tl(t0, t0, t1);
1166
1167 /* Or'in new bits and write it out */
1168 tcg_gen_or_tl(t0, t0, t2);
1169 gen_store_spr(SPR_UAMOR, t0);
1170 spr_store_dump_spr(SPR_UAMOR);
1171
1172 tcg_temp_free(t0);
1173 tcg_temp_free(t1);
1174 tcg_temp_free(t2);
1175 }
1176
1177 static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
1178 {
1179 TCGv t0 = tcg_temp_new();
1180 TCGv t1 = tcg_temp_new();
1181 TCGv t2 = tcg_temp_new();
1182
1183 /* Note, the HV=1 case is handled earlier by simply using
1184 * spr_write_generic for HV mode in the SPR table
1185 */
1186
1187 /* Build insertion mask into t1 based on context */
1188 gen_load_spr(t1, SPR_AMOR);
1189
1190 /* Mask new bits into t2 */
1191 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1192
1193 /* Load AMR and clear new bits in t0 */
1194 gen_load_spr(t0, SPR_IAMR);
1195 tcg_gen_andc_tl(t0, t0, t1);
1196
1197 /* Or'in new bits and write it out */
1198 tcg_gen_or_tl(t0, t0, t2);
1199 gen_store_spr(SPR_IAMR, t0);
1200 spr_store_dump_spr(SPR_IAMR);
1201
1202 tcg_temp_free(t0);
1203 tcg_temp_free(t1);
1204 tcg_temp_free(t2);
1205 }
1206 #endif /* CONFIG_USER_ONLY */
1207
1208 static void gen_spr_amr(CPUPPCState *env)
1209 {
1210 #ifndef CONFIG_USER_ONLY
1211 /* Virtual Page Class Key protection */
1212 /* The AMR is accessible either via SPR 13 or SPR 29. 13 is
1213 * userspace accessible, 29 is privileged. So we only need to set
1214 * the kvm ONE_REG id on one of them, we use 29 */
1215 spr_register(env, SPR_UAMR, "UAMR",
1216 &spr_read_generic, &spr_write_amr,
1217 &spr_read_generic, &spr_write_amr,
1218 0);
1219 spr_register_kvm_hv(env, SPR_AMR, "AMR",
1220 SPR_NOACCESS, SPR_NOACCESS,
1221 &spr_read_generic, &spr_write_amr,
1222 &spr_read_generic, &spr_write_generic,
1223 KVM_REG_PPC_AMR, 0);
1224 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
1225 SPR_NOACCESS, SPR_NOACCESS,
1226 &spr_read_generic, &spr_write_uamor,
1227 &spr_read_generic, &spr_write_generic,
1228 KVM_REG_PPC_UAMOR, 0);
1229 spr_register_hv(env, SPR_AMOR, "AMOR",
1230 SPR_NOACCESS, SPR_NOACCESS,
1231 SPR_NOACCESS, SPR_NOACCESS,
1232 &spr_read_generic, &spr_write_generic,
1233 0);
1234 #endif /* !CONFIG_USER_ONLY */
1235 }
1236
1237 static void gen_spr_iamr(CPUPPCState *env)
1238 {
1239 #ifndef CONFIG_USER_ONLY
1240 spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
1241 SPR_NOACCESS, SPR_NOACCESS,
1242 &spr_read_generic, &spr_write_iamr,
1243 &spr_read_generic, &spr_write_generic,
1244 KVM_REG_PPC_IAMR, 0);
1245 #endif /* !CONFIG_USER_ONLY */
1246 }
1247 #endif /* TARGET_PPC64 */
1248
1249 #ifndef CONFIG_USER_ONLY
1250 static void spr_read_thrm(DisasContext *ctx, int gprn, int sprn)
1251 {
1252 gen_helper_fixup_thrm(cpu_env);
1253 gen_load_spr(cpu_gpr[gprn], sprn);
1254 spr_load_dump_spr(sprn);
1255 }
1256 #endif /* !CONFIG_USER_ONLY */
1257
1258 static void gen_spr_thrm(CPUPPCState *env)
1259 {
1260 /* Thermal management */
1261 /* XXX : not implemented */
1262 spr_register(env, SPR_THRM1, "THRM1",
1263 SPR_NOACCESS, SPR_NOACCESS,
1264 &spr_read_thrm, &spr_write_generic,
1265 0x00000000);
1266 /* XXX : not implemented */
1267 spr_register(env, SPR_THRM2, "THRM2",
1268 SPR_NOACCESS, SPR_NOACCESS,
1269 &spr_read_thrm, &spr_write_generic,
1270 0x00000000);
1271 /* XXX : not implemented */
1272 spr_register(env, SPR_THRM3, "THRM3",
1273 SPR_NOACCESS, SPR_NOACCESS,
1274 &spr_read_thrm, &spr_write_generic,
1275 0x00000000);
1276 }
1277
1278 /* SPR specific to PowerPC 604 implementation */
1279 static void gen_spr_604(CPUPPCState *env)
1280 {
1281 /* Processor identification */
1282 spr_register(env, SPR_PIR, "PIR",
1283 SPR_NOACCESS, SPR_NOACCESS,
1284 &spr_read_generic, &spr_write_pir,
1285 0x00000000);
1286 /* Breakpoints */
1287 /* XXX : not implemented */
1288 spr_register(env, SPR_IABR, "IABR",
1289 SPR_NOACCESS, SPR_NOACCESS,
1290 &spr_read_generic, &spr_write_generic,
1291 0x00000000);
1292 /* XXX : not implemented */
1293 spr_register_kvm(env, SPR_DABR, "DABR",
1294 SPR_NOACCESS, SPR_NOACCESS,
1295 &spr_read_generic, &spr_write_generic,
1296 KVM_REG_PPC_DABR, 0x00000000);
1297 /* Performance counters */
1298 /* XXX : not implemented */
1299 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
1300 SPR_NOACCESS, SPR_NOACCESS,
1301 &spr_read_generic, &spr_write_generic,
1302 0x00000000);
1303 /* XXX : not implemented */
1304 spr_register(env, SPR_7XX_PMC1, "PMC1",
1305 SPR_NOACCESS, SPR_NOACCESS,
1306 &spr_read_generic, &spr_write_generic,
1307 0x00000000);
1308 /* XXX : not implemented */
1309 spr_register(env, SPR_7XX_PMC2, "PMC2",
1310 SPR_NOACCESS, SPR_NOACCESS,
1311 &spr_read_generic, &spr_write_generic,
1312 0x00000000);
1313 /* XXX : not implemented */
1314 spr_register(env, SPR_7XX_SIAR, "SIAR",
1315 SPR_NOACCESS, SPR_NOACCESS,
1316 &spr_read_generic, SPR_NOACCESS,
1317 0x00000000);
1318 /* XXX : not implemented */
1319 spr_register(env, SPR_SDA, "SDA",
1320 SPR_NOACCESS, SPR_NOACCESS,
1321 &spr_read_generic, SPR_NOACCESS,
1322 0x00000000);
1323 /* External access control */
1324 /* XXX : not implemented */
1325 spr_register(env, SPR_EAR, "EAR",
1326 SPR_NOACCESS, SPR_NOACCESS,
1327 &spr_read_generic, &spr_write_generic,
1328 0x00000000);
1329 }
1330
1331 /* SPR specific to PowerPC 603 implementation */
1332 static void gen_spr_603(CPUPPCState *env)
1333 {
1334 /* External access control */
1335 /* XXX : not implemented */
1336 spr_register(env, SPR_EAR, "EAR",
1337 SPR_NOACCESS, SPR_NOACCESS,
1338 &spr_read_generic, &spr_write_generic,
1339 0x00000000);
1340 /* Breakpoints */
1341 /* XXX : not implemented */
1342 spr_register(env, SPR_IABR, "IABR",
1343 SPR_NOACCESS, SPR_NOACCESS,
1344 &spr_read_generic, &spr_write_generic,
1345 0x00000000);
1346
1347 }
1348
1349 /* SPR specific to PowerPC G2 implementation */
1350 static void gen_spr_G2(CPUPPCState *env)
1351 {
1352 /* Memory base address */
1353 /* MBAR */
1354 /* XXX : not implemented */
1355 spr_register(env, SPR_MBAR, "MBAR",
1356 SPR_NOACCESS, SPR_NOACCESS,
1357 &spr_read_generic, &spr_write_generic,
1358 0x00000000);
1359 /* Exception processing */
1360 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1361 SPR_NOACCESS, SPR_NOACCESS,
1362 &spr_read_generic, &spr_write_generic,
1363 0x00000000);
1364 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1365 SPR_NOACCESS, SPR_NOACCESS,
1366 &spr_read_generic, &spr_write_generic,
1367 0x00000000);
1368 /* Breakpoints */
1369 /* XXX : not implemented */
1370 spr_register(env, SPR_DABR, "DABR",
1371 SPR_NOACCESS, SPR_NOACCESS,
1372 &spr_read_generic, &spr_write_generic,
1373 0x00000000);
1374 /* XXX : not implemented */
1375 spr_register(env, SPR_DABR2, "DABR2",
1376 SPR_NOACCESS, SPR_NOACCESS,
1377 &spr_read_generic, &spr_write_generic,
1378 0x00000000);
1379 /* XXX : not implemented */
1380 spr_register(env, SPR_IABR, "IABR",
1381 SPR_NOACCESS, SPR_NOACCESS,
1382 &spr_read_generic, &spr_write_generic,
1383 0x00000000);
1384 /* XXX : not implemented */
1385 spr_register(env, SPR_IABR2, "IABR2",
1386 SPR_NOACCESS, SPR_NOACCESS,
1387 &spr_read_generic, &spr_write_generic,
1388 0x00000000);
1389 /* XXX : not implemented */
1390 spr_register(env, SPR_IBCR, "IBCR",
1391 SPR_NOACCESS, SPR_NOACCESS,
1392 &spr_read_generic, &spr_write_generic,
1393 0x00000000);
1394 /* XXX : not implemented */
1395 spr_register(env, SPR_DBCR, "DBCR",
1396 SPR_NOACCESS, SPR_NOACCESS,
1397 &spr_read_generic, &spr_write_generic,
1398 0x00000000);
1399 }
1400
1401 /* SPR specific to PowerPC 602 implementation */
1402 static void gen_spr_602(CPUPPCState *env)
1403 {
1404 /* ESA registers */
1405 /* XXX : not implemented */
1406 spr_register(env, SPR_SER, "SER",
1407 SPR_NOACCESS, SPR_NOACCESS,
1408 &spr_read_generic, &spr_write_generic,
1409 0x00000000);
1410 /* XXX : not implemented */
1411 spr_register(env, SPR_SEBR, "SEBR",
1412 SPR_NOACCESS, SPR_NOACCESS,
1413 &spr_read_generic, &spr_write_generic,
1414 0x00000000);
1415 /* XXX : not implemented */
1416 spr_register(env, SPR_ESASRR, "ESASRR",
1417 SPR_NOACCESS, SPR_NOACCESS,
1418 &spr_read_generic, &spr_write_generic,
1419 0x00000000);
1420 /* Floating point status */
1421 /* XXX : not implemented */
1422 spr_register(env, SPR_SP, "SP",
1423 SPR_NOACCESS, SPR_NOACCESS,
1424 &spr_read_generic, &spr_write_generic,
1425 0x00000000);
1426 /* XXX : not implemented */
1427 spr_register(env, SPR_LT, "LT",
1428 SPR_NOACCESS, SPR_NOACCESS,
1429 &spr_read_generic, &spr_write_generic,
1430 0x00000000);
1431 /* Watchdog timer */
1432 /* XXX : not implemented */
1433 spr_register(env, SPR_TCR, "TCR",
1434 SPR_NOACCESS, SPR_NOACCESS,
1435 &spr_read_generic, &spr_write_generic,
1436 0x00000000);
1437 /* Interrupt base */
1438 spr_register(env, SPR_IBR, "IBR",
1439 SPR_NOACCESS, SPR_NOACCESS,
1440 &spr_read_generic, &spr_write_generic,
1441 0x00000000);
1442 /* XXX : not implemented */
1443 spr_register(env, SPR_IABR, "IABR",
1444 SPR_NOACCESS, SPR_NOACCESS,
1445 &spr_read_generic, &spr_write_generic,
1446 0x00000000);
1447 }
1448
1449 /* SPR specific to PowerPC 601 implementation */
1450 static void gen_spr_601(CPUPPCState *env)
1451 {
1452 /* Multiplication/division register */
1453 /* MQ */
1454 spr_register(env, SPR_MQ, "MQ",
1455 &spr_read_generic, &spr_write_generic,
1456 &spr_read_generic, &spr_write_generic,
1457 0x00000000);
1458 /* RTC registers */
1459 spr_register(env, SPR_601_RTCU, "RTCU",
1460 SPR_NOACCESS, SPR_NOACCESS,
1461 SPR_NOACCESS, &spr_write_601_rtcu,
1462 0x00000000);
1463 spr_register(env, SPR_601_VRTCU, "RTCU",
1464 &spr_read_601_rtcu, SPR_NOACCESS,
1465 &spr_read_601_rtcu, SPR_NOACCESS,
1466 0x00000000);
1467 spr_register(env, SPR_601_RTCL, "RTCL",
1468 SPR_NOACCESS, SPR_NOACCESS,
1469 SPR_NOACCESS, &spr_write_601_rtcl,
1470 0x00000000);
1471 spr_register(env, SPR_601_VRTCL, "RTCL",
1472 &spr_read_601_rtcl, SPR_NOACCESS,
1473 &spr_read_601_rtcl, SPR_NOACCESS,
1474 0x00000000);
1475 /* Timer */
1476 #if 0 /* ? */
1477 spr_register(env, SPR_601_UDECR, "UDECR",
1478 &spr_read_decr, SPR_NOACCESS,
1479 &spr_read_decr, SPR_NOACCESS,
1480 0x00000000);
1481 #endif
1482 /* External access control */
1483 /* XXX : not implemented */
1484 spr_register(env, SPR_EAR, "EAR",
1485 SPR_NOACCESS, SPR_NOACCESS,
1486 &spr_read_generic, &spr_write_generic,
1487 0x00000000);
1488 /* Memory management */
1489 #if !defined(CONFIG_USER_ONLY)
1490 spr_register(env, SPR_IBAT0U, "IBAT0U",
1491 SPR_NOACCESS, SPR_NOACCESS,
1492 &spr_read_601_ubat, &spr_write_601_ubatu,
1493 0x00000000);
1494 spr_register(env, SPR_IBAT0L, "IBAT0L",
1495 SPR_NOACCESS, SPR_NOACCESS,
1496 &spr_read_601_ubat, &spr_write_601_ubatl,
1497 0x00000000);
1498 spr_register(env, SPR_IBAT1U, "IBAT1U",
1499 SPR_NOACCESS, SPR_NOACCESS,
1500 &spr_read_601_ubat, &spr_write_601_ubatu,
1501 0x00000000);
1502 spr_register(env, SPR_IBAT1L, "IBAT1L",
1503 SPR_NOACCESS, SPR_NOACCESS,
1504 &spr_read_601_ubat, &spr_write_601_ubatl,
1505 0x00000000);
1506 spr_register(env, SPR_IBAT2U, "IBAT2U",
1507 SPR_NOACCESS, SPR_NOACCESS,
1508 &spr_read_601_ubat, &spr_write_601_ubatu,
1509 0x00000000);
1510 spr_register(env, SPR_IBAT2L, "IBAT2L",
1511 SPR_NOACCESS, SPR_NOACCESS,
1512 &spr_read_601_ubat, &spr_write_601_ubatl,
1513 0x00000000);
1514 spr_register(env, SPR_IBAT3U, "IBAT3U",
1515 SPR_NOACCESS, SPR_NOACCESS,
1516 &spr_read_601_ubat, &spr_write_601_ubatu,
1517 0x00000000);
1518 spr_register(env, SPR_IBAT3L, "IBAT3L",
1519 SPR_NOACCESS, SPR_NOACCESS,
1520 &spr_read_601_ubat, &spr_write_601_ubatl,
1521 0x00000000);
1522 env->nb_BATs = 4;
1523 #endif
1524 }
1525
1526 static void gen_spr_74xx(CPUPPCState *env)
1527 {
1528 /* Processor identification */
1529 spr_register(env, SPR_PIR, "PIR",
1530 SPR_NOACCESS, SPR_NOACCESS,
1531 &spr_read_generic, &spr_write_pir,
1532 0x00000000);
1533 /* XXX : not implemented */
1534 spr_register(env, SPR_74XX_MMCR2, "MMCR2",
1535 SPR_NOACCESS, SPR_NOACCESS,
1536 &spr_read_generic, &spr_write_generic,
1537 0x00000000);
1538 /* XXX : not implemented */
1539 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
1540 &spr_read_ureg, SPR_NOACCESS,
1541 &spr_read_ureg, SPR_NOACCESS,
1542 0x00000000);
1543 /* XXX: not implemented */
1544 spr_register(env, SPR_BAMR, "BAMR",
1545 SPR_NOACCESS, SPR_NOACCESS,
1546 &spr_read_generic, &spr_write_generic,
1547 0x00000000);
1548 /* XXX : not implemented */
1549 spr_register(env, SPR_MSSCR0, "MSSCR0",
1550 SPR_NOACCESS, SPR_NOACCESS,
1551 &spr_read_generic, &spr_write_generic,
1552 0x00000000);
1553 /* Hardware implementation registers */
1554 /* XXX : not implemented */
1555 spr_register(env, SPR_HID0, "HID0",
1556 SPR_NOACCESS, SPR_NOACCESS,
1557 &spr_read_generic, &spr_write_generic,
1558 0x00000000);
1559 /* XXX : not implemented */
1560 spr_register(env, SPR_HID1, "HID1",
1561 SPR_NOACCESS, SPR_NOACCESS,
1562 &spr_read_generic, &spr_write_generic,
1563 0x00000000);
1564 /* Altivec */
1565 spr_register(env, SPR_VRSAVE, "VRSAVE",
1566 &spr_read_generic, &spr_write_generic,
1567 &spr_read_generic, &spr_write_generic,
1568 0x00000000);
1569 /* XXX : not implemented */
1570 spr_register(env, SPR_L2CR, "L2CR",
1571 SPR_NOACCESS, SPR_NOACCESS,
1572 &spr_read_generic, spr_access_nop,
1573 0x00000000);
1574 /* Not strictly an SPR */
1575 vscr_init(env, 0x00010000);
1576 }
1577
1578 static void gen_l3_ctrl(CPUPPCState *env)
1579 {
1580 /* L3CR */
1581 /* XXX : not implemented */
1582 spr_register(env, SPR_L3CR, "L3CR",
1583 SPR_NOACCESS, SPR_NOACCESS,
1584 &spr_read_generic, &spr_write_generic,
1585 0x00000000);
1586 /* L3ITCR0 */
1587 /* XXX : not implemented */
1588 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1589 SPR_NOACCESS, SPR_NOACCESS,
1590 &spr_read_generic, &spr_write_generic,
1591 0x00000000);
1592 /* L3PM */
1593 /* XXX : not implemented */
1594 spr_register(env, SPR_L3PM, "L3PM",
1595 SPR_NOACCESS, SPR_NOACCESS,
1596 &spr_read_generic, &spr_write_generic,
1597 0x00000000);
1598 }
1599
1600 static void gen_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
1601 {
1602 #if !defined(CONFIG_USER_ONLY)
1603 env->nb_tlb = nb_tlbs;
1604 env->nb_ways = nb_ways;
1605 env->id_tlbs = 1;
1606 env->tlb_type = TLB_6XX;
1607 /* XXX : not implemented */
1608 spr_register(env, SPR_PTEHI, "PTEHI",
1609 SPR_NOACCESS, SPR_NOACCESS,
1610 &spr_read_generic, &spr_write_generic,
1611 0x00000000);
1612 /* XXX : not implemented */
1613 spr_register(env, SPR_PTELO, "PTELO",
1614 SPR_NOACCESS, SPR_NOACCESS,
1615 &spr_read_generic, &spr_write_generic,
1616 0x00000000);
1617 /* XXX : not implemented */
1618 spr_register(env, SPR_TLBMISS, "TLBMISS",
1619 SPR_NOACCESS, SPR_NOACCESS,
1620 &spr_read_generic, &spr_write_generic,
1621 0x00000000);
1622 #endif
1623 }
1624
1625 #if !defined(CONFIG_USER_ONLY)
1626 static void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn)
1627 {
1628 TCGv t0 = tcg_temp_new();
1629
1630 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
1631 gen_store_spr(sprn, t0);
1632 tcg_temp_free(t0);
1633 }
1634
1635 static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
1636 {
1637 TCGv t0 = tcg_temp_new();
1638
1639 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
1640 gen_store_spr(sprn, t0);
1641 tcg_temp_free(t0);
1642 }
1643
1644 static void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn)
1645 {
1646 gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
1647 }
1648
1649 static void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn)
1650 {
1651 TCGv_i32 t0 = tcg_const_i32(sprn);
1652 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1653 tcg_temp_free_i32(t0);
1654 }
1655 #endif
1656
1657 static void gen_spr_usprg3(CPUPPCState *env)
1658 {
1659 spr_register(env, SPR_USPRG3, "USPRG3",
1660 &spr_read_ureg, SPR_NOACCESS,
1661 &spr_read_ureg, SPR_NOACCESS,
1662 0x00000000);
1663 }
1664
1665 static void gen_spr_usprgh(CPUPPCState *env)
1666 {
1667 spr_register(env, SPR_USPRG4, "USPRG4",
1668 &spr_read_ureg, SPR_NOACCESS,
1669 &spr_read_ureg, SPR_NOACCESS,
1670 0x00000000);
1671 spr_register(env, SPR_USPRG5, "USPRG5",
1672 &spr_read_ureg, SPR_NOACCESS,
1673 &spr_read_ureg, SPR_NOACCESS,
1674 0x00000000);
1675 spr_register(env, SPR_USPRG6, "USPRG6",
1676 &spr_read_ureg, SPR_NOACCESS,
1677 &spr_read_ureg, SPR_NOACCESS,
1678 0x00000000);
1679 spr_register(env, SPR_USPRG7, "USPRG7",
1680 &spr_read_ureg, SPR_NOACCESS,
1681 &spr_read_ureg, SPR_NOACCESS,
1682 0x00000000);
1683 }
1684
1685 /* PowerPC BookE SPR */
1686 static void gen_spr_BookE(CPUPPCState *env, uint64_t ivor_mask)
1687 {
1688 const char *ivor_names[64] = {
1689 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1690 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1691 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1692 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1693 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1694 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1695 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1696 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1697 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1698 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1699 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1700 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1701 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1702 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1703 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1704 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1705 };
1706 #define SPR_BOOKE_IVORxx (-1)
1707 int ivor_sprn[64] = {
1708 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1709 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1710 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1711 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1712 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1713 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1714 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1715 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1716 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1717 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1718 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1719 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1720 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1721 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1722 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1723 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1724 };
1725 int i;
1726
1727 /* Interrupt processing */
1728 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1729 SPR_NOACCESS, SPR_NOACCESS,
1730 &spr_read_generic, &spr_write_generic,
1731 0x00000000);
1732 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1733 SPR_NOACCESS, SPR_NOACCESS,
1734 &spr_read_generic, &spr_write_generic,
1735 0x00000000);
1736 /* Debug */
1737 /* XXX : not implemented */
1738 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1739 SPR_NOACCESS, SPR_NOACCESS,
1740 &spr_read_generic, &spr_write_generic,
1741 0x00000000);
1742 /* XXX : not implemented */
1743 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1744 SPR_NOACCESS, SPR_NOACCESS,
1745 &spr_read_generic, &spr_write_generic,
1746 0x00000000);
1747 /* XXX : not implemented */
1748 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1749 SPR_NOACCESS, SPR_NOACCESS,
1750 &spr_read_generic, &spr_write_generic,
1751 0x00000000);
1752 /* XXX : not implemented */
1753 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1754 SPR_NOACCESS, SPR_NOACCESS,
1755 &spr_read_generic, &spr_write_generic,
1756 0x00000000);
1757 /* XXX : not implemented */
1758 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1759 SPR_NOACCESS, SPR_NOACCESS,
1760 &spr_read_generic, &spr_write_40x_dbcr0,
1761 0x00000000);
1762 /* XXX : not implemented */
1763 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1764 SPR_NOACCESS, SPR_NOACCESS,
1765 &spr_read_generic, &spr_write_generic,
1766 0x00000000);
1767 /* XXX : not implemented */
1768 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1769 SPR_NOACCESS, SPR_NOACCESS,
1770 &spr_read_generic, &spr_write_generic,
1771 0x00000000);
1772 /* XXX : not implemented */
1773 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1774 SPR_NOACCESS, SPR_NOACCESS,
1775 &spr_read_generic, &spr_write_clear,
1776 0x00000000);
1777 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1778 SPR_NOACCESS, SPR_NOACCESS,
1779 &spr_read_generic, &spr_write_generic,
1780 0x00000000);
1781 spr_register(env, SPR_BOOKE_ESR, "ESR",
1782 SPR_NOACCESS, SPR_NOACCESS,
1783 &spr_read_generic, &spr_write_generic,
1784 0x00000000);
1785 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1786 SPR_NOACCESS, SPR_NOACCESS,
1787 &spr_read_generic, &spr_write_excp_prefix,
1788 0x00000000);
1789 /* Exception vectors */
1790 for (i = 0; i < 64; i++) {
1791 if (ivor_mask & (1ULL << i)) {
1792 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1793 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1794 exit(1);
1795 }
1796 spr_register(env, ivor_sprn[i], ivor_names[i],
1797 SPR_NOACCESS, SPR_NOACCESS,
1798 &spr_read_generic, &spr_write_excp_vector,
1799 0x00000000);
1800 }
1801 }
1802 spr_register(env, SPR_BOOKE_PID, "PID",
1803 SPR_NOACCESS, SPR_NOACCESS,
1804 &spr_read_generic, &spr_write_booke_pid,
1805 0x00000000);
1806 spr_register(env, SPR_BOOKE_TCR, "TCR",
1807 SPR_NOACCESS, SPR_NOACCESS,
1808 &spr_read_generic, &spr_write_booke_tcr,
1809 0x00000000);
1810 spr_register(env, SPR_BOOKE_TSR, "TSR",
1811 SPR_NOACCESS, SPR_NOACCESS,
1812 &spr_read_generic, &spr_write_booke_tsr,
1813 0x00000000);
1814 /* Timer */
1815 spr_register(env, SPR_DECR, "DECR",
1816 SPR_NOACCESS, SPR_NOACCESS,
1817 &spr_read_decr, &spr_write_decr,
1818 0x00000000);
1819 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1820 SPR_NOACCESS, SPR_NOACCESS,
1821 SPR_NOACCESS, &spr_write_generic,
1822 0x00000000);
1823 /* SPRGs */
1824 spr_register(env, SPR_USPRG0, "USPRG0",
1825 &spr_read_generic, &spr_write_generic,
1826 &spr_read_generic, &spr_write_generic,
1827 0x00000000);
1828 spr_register(env, SPR_SPRG4, "SPRG4",
1829 SPR_NOACCESS, SPR_NOACCESS,
1830 &spr_read_generic, &spr_write_generic,
1831 0x00000000);
1832 spr_register(env, SPR_SPRG5, "SPRG5",
1833 SPR_NOACCESS, SPR_NOACCESS,
1834 &spr_read_generic, &spr_write_generic,
1835 0x00000000);
1836 spr_register(env, SPR_SPRG6, "SPRG6",
1837 SPR_NOACCESS, SPR_NOACCESS,
1838 &spr_read_generic, &spr_write_generic,
1839 0x00000000);
1840 spr_register(env, SPR_SPRG7, "SPRG7",
1841 SPR_NOACCESS, SPR_NOACCESS,
1842 &spr_read_generic, &spr_write_generic,
1843 0x00000000);
1844 }
1845
1846 static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1847 uint32_t maxsize, uint32_t flags,
1848 uint32_t nentries)
1849 {
1850 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1851 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1852 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1853 flags | nentries;
1854 }
1855
1856 /* BookE 2.06 storage control registers */
1857 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1858 uint32_t *tlbncfg, uint32_t mmucfg)
1859 {
1860 #if !defined(CONFIG_USER_ONLY)
1861 const char *mas_names[8] = {
1862 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1863 };
1864 int mas_sprn[8] = {
1865 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1866 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1867 };
1868 int i;
1869
1870 /* TLB assist registers */
1871 /* XXX : not implemented */
1872 for (i = 0; i < 8; i++) {
1873 void (*uea_write)(DisasContext *ctx, int sprn, int gprn) = &spr_write_generic32;
1874 if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1875 uea_write = &spr_write_generic;
1876 }
1877 if (mas_mask & (1 << i)) {
1878 spr_register(env, mas_sprn[i], mas_names[i],
1879 SPR_NOACCESS, SPR_NOACCESS,
1880 &spr_read_generic, uea_write,
1881 0x00000000);
1882 }
1883 }
1884 if (env->nb_pids > 1) {
1885 /* XXX : not implemented */
1886 spr_register(env, SPR_BOOKE_PID1, "PID1",
1887 SPR_NOACCESS, SPR_NOACCESS,
1888 &spr_read_generic, &spr_write_booke_pid,
1889 0x00000000);
1890 }
1891 if (env->nb_pids > 2) {
1892 /* XXX : not implemented */
1893 spr_register(env, SPR_BOOKE_PID2, "PID2",
1894 SPR_NOACCESS, SPR_NOACCESS,
1895 &spr_read_generic, &spr_write_booke_pid,
1896 0x00000000);
1897 }
1898 /* XXX : not implemented */
1899 spr_register(env, SPR_MMUCFG, "MMUCFG",
1900 SPR_NOACCESS, SPR_NOACCESS,
1901 &spr_read_generic, SPR_NOACCESS,
1902 mmucfg);
1903 switch (env->nb_ways) {
1904 case 4:
1905 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1906 SPR_NOACCESS, SPR_NOACCESS,
1907 &spr_read_generic, SPR_NOACCESS,
1908 tlbncfg[3]);
1909 /* Fallthru */
1910 case 3:
1911 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1912 SPR_NOACCESS, SPR_NOACCESS,
1913 &spr_read_generic, SPR_NOACCESS,
1914 tlbncfg[2]);
1915 /* Fallthru */
1916 case 2:
1917 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1918 SPR_NOACCESS, SPR_NOACCESS,
1919 &spr_read_generic, SPR_NOACCESS,
1920 tlbncfg[1]);
1921 /* Fallthru */
1922 case 1:
1923 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1924 SPR_NOACCESS, SPR_NOACCESS,
1925 &spr_read_generic, SPR_NOACCESS,
1926 tlbncfg[0]);
1927 /* Fallthru */
1928 case 0:
1929 default:
1930 break;
1931 }
1932 #endif
1933
1934 gen_spr_usprgh(env);
1935 }
1936
1937 /* SPR specific to PowerPC 440 implementation */
1938 static void gen_spr_440(CPUPPCState *env)
1939 {
1940 /* Cache control */
1941 /* XXX : not implemented */
1942 spr_register(env, SPR_440_DNV0, "DNV0",
1943 SPR_NOACCESS, SPR_NOACCESS,
1944 &spr_read_generic, &spr_write_generic,
1945 0x00000000);
1946 /* XXX : not implemented */
1947 spr_register(env, SPR_440_DNV1, "DNV1",
1948 SPR_NOACCESS, SPR_NOACCESS,
1949 &spr_read_generic, &spr_write_generic,
1950 0x00000000);
1951 /* XXX : not implemented */
1952 spr_register(env, SPR_440_DNV2, "DNV2",
1953 SPR_NOACCESS, SPR_NOACCESS,
1954 &spr_read_generic, &spr_write_generic,
1955 0x00000000);
1956 /* XXX : not implemented */
1957 spr_register(env, SPR_440_DNV3, "DNV3",
1958 SPR_NOACCESS, SPR_NOACCESS,
1959 &spr_read_generic, &spr_write_generic,
1960 0x00000000);
1961 /* XXX : not implemented */
1962 spr_register(env, SPR_440_DTV0, "DTV0",
1963 SPR_NOACCESS, SPR_NOACCESS,
1964 &spr_read_generic, &spr_write_generic,
1965 0x00000000);
1966 /* XXX : not implemented */
1967 spr_register(env, SPR_440_DTV1, "DTV1",
1968 SPR_NOACCESS, SPR_NOACCESS,
1969 &spr_read_generic, &spr_write_generic,
1970 0x00000000);
1971 /* XXX : not implemented */
1972 spr_register(env, SPR_440_DTV2, "DTV2",
1973 SPR_NOACCESS, SPR_NOACCESS,
1974 &spr_read_generic, &spr_write_generic,
1975 0x00000000);
1976 /* XXX : not implemented */
1977 spr_register(env, SPR_440_DTV3, "DTV3",
1978 SPR_NOACCESS, SPR_NOACCESS,
1979 &spr_read_generic, &spr_write_generic,
1980 0x00000000);
1981 /* XXX : not implemented */
1982 spr_register(env, SPR_440_DVLIM, "DVLIM",
1983 SPR_NOACCESS, SPR_NOACCESS,
1984 &spr_read_generic, &spr_write_generic,
1985 0x00000000);
1986 /* XXX : not implemented */
1987 spr_register(env, SPR_440_INV0, "INV0",
1988 SPR_NOACCESS, SPR_NOACCESS,
1989 &spr_read_generic, &spr_write_generic,
1990 0x00000000);
1991 /* XXX : not implemented */
1992 spr_register(env, SPR_440_INV1, "INV1",
1993 SPR_NOACCESS, SPR_NOACCESS,
1994 &spr_read_generic, &spr_write_generic,
1995 0x00000000);
1996 /* XXX : not implemented */
1997 spr_register(env, SPR_440_INV2, "INV2",
1998 SPR_NOACCESS, SPR_NOACCESS,
1999 &spr_read_generic, &spr_write_generic,
2000 0x00000000);
2001 /* XXX : not implemented */
2002 spr_register(env, SPR_440_INV3, "INV3",
2003 SPR_NOACCESS, SPR_NOACCESS,
2004 &spr_read_generic, &spr_write_generic,
2005 0x00000000);
2006 /* XXX : not implemented */
2007 spr_register(env, SPR_440_ITV0, "ITV0",
2008 SPR_NOACCESS, SPR_NOACCESS,
2009 &spr_read_generic, &spr_write_generic,
2010 0x00000000);
2011 /* XXX : not implemented */
2012 spr_register(env, SPR_440_ITV1, "ITV1",
2013 SPR_NOACCESS, SPR_NOACCESS,
2014 &spr_read_generic, &spr_write_generic,
2015 0x00000000);
2016 /* XXX : not implemented */
2017 spr_register(env, SPR_440_ITV2, "ITV2",
2018 SPR_NOACCESS, SPR_NOACCESS,
2019 &spr_read_generic, &spr_write_generic,
2020 0x00000000);
2021 /* XXX : not implemented */
2022 spr_register(env, SPR_440_ITV3, "ITV3",
2023 SPR_NOACCESS, SPR_NOACCESS,
2024 &spr_read_generic, &spr_write_generic,
2025 0x00000000);
2026 /* XXX : not implemented */
2027 spr_register(env, SPR_440_IVLIM, "IVLIM",
2028 SPR_NOACCESS, SPR_NOACCESS,
2029 &spr_read_generic, &spr_write_generic,
2030 0x00000000);
2031 /* Cache debug */
2032 /* XXX : not implemented */
2033 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
2034 SPR_NOACCESS, SPR_NOACCESS,
2035 &spr_read_generic, SPR_NOACCESS,
2036 0x00000000);
2037 /* XXX : not implemented */
2038 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
2039 SPR_NOACCESS, SPR_NOACCESS,
2040 &spr_read_generic, SPR_NOACCESS,
2041 0x00000000);
2042 /* XXX : not implemented */
2043 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
2044 SPR_NOACCESS, SPR_NOACCESS,
2045 &spr_read_generic, SPR_NOACCESS,
2046 0x00000000);
2047 /* XXX : not implemented */
2048 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
2049 SPR_NOACCESS, SPR_NOACCESS,
2050 &spr_read_generic, SPR_NOACCESS,
2051 0x00000000);
2052 /* XXX : not implemented */
2053 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
2054 SPR_NOACCESS, SPR_NOACCESS,
2055 &spr_read_generic, SPR_NOACCESS,
2056 0x00000000);
2057 /* XXX : not implemented */
2058 spr_register(env, SPR_440_DBDR, "DBDR",
2059 SPR_NOACCESS, SPR_NOACCESS,
2060 &spr_read_generic, &spr_write_generic,
2061 0x00000000);
2062 /* Processor control */
2063 spr_register(env, SPR_4xx_CCR0, "CCR0",
2064 SPR_NOACCESS, SPR_NOACCESS,
2065 &spr_read_generic, &spr_write_generic,
2066 0x00000000);
2067 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
2068 SPR_NOACCESS, SPR_NOACCESS,
2069 &spr_read_generic, SPR_NOACCESS,
2070 0x00000000);
2071 /* Storage control */
2072 spr_register(env, SPR_440_MMUCR, "MMUCR",
2073 SPR_NOACCESS, SPR_NOACCESS,
2074 &spr_read_generic, &spr_write_generic,
2075 0x00000000);
2076 }
2077
2078 /* SPR shared between PowerPC 40x implementations */
2079 static void gen_spr_40x(CPUPPCState *env)
2080 {
2081 /* Cache */
2082 /* not emulated, as QEMU do not emulate caches */
2083 spr_register(env, SPR_40x_DCCR, "DCCR",
2084 SPR_NOACCESS, SPR_NOACCESS,
2085 &spr_read_generic, &spr_write_generic,
2086 0x00000000);
2087 /* not emulated, as QEMU do not emulate caches */
2088 spr_register(env, SPR_40x_ICCR, "ICCR",
2089 SPR_NOACCESS, SPR_NOACCESS,
2090 &spr_read_generic, &spr_write_generic,
2091 0x00000000);
2092 /* not emulated, as QEMU do not emulate caches */
2093 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
2094 SPR_NOACCESS, SPR_NOACCESS,
2095 &spr_read_generic, SPR_NOACCESS,
2096 0x00000000);
2097 /* Exception */
2098 spr_register(env, SPR_40x_DEAR, "DEAR",
2099 SPR_NOACCESS, SPR_NOACCESS,
2100 &spr_read_generic, &spr_write_generic,
2101 0x00000000);
2102 spr_register(env, SPR_40x_ESR, "ESR",
2103 SPR_NOACCESS, SPR_NOACCESS,
2104 &spr_read_generic, &spr_write_generic,
2105 0x00000000);
2106 spr_register(env, SPR_40x_EVPR, "EVPR",
2107 SPR_NOACCESS, SPR_NOACCESS,
2108 &spr_read_generic, &spr_write_excp_prefix,
2109 0x00000000);
2110 spr_register(env, SPR_40x_SRR2, "SRR2",
2111 &spr_read_generic, &spr_write_generic,
2112 &spr_read_generic, &spr_write_generic,
2113 0x00000000);
2114 spr_register(env, SPR_40x_SRR3, "SRR3",
2115 &spr_read_generic, &spr_write_generic,
2116 &spr_read_generic, &spr_write_generic,
2117 0x00000000);
2118 /* Timers */
2119 spr_register(env, SPR_40x_PIT, "PIT",
2120 SPR_NOACCESS, SPR_NOACCESS,
2121 &spr_read_40x_pit, &spr_write_40x_pit,
2122 0x00000000);
2123 spr_register(env, SPR_40x_TCR, "TCR",
2124 SPR_NOACCESS, SPR_NOACCESS,
2125 &spr_read_generic, &spr_write_booke_tcr,
2126 0x00000000);
2127 spr_register(env, SPR_40x_TSR, "TSR",
2128 SPR_NOACCESS, SPR_NOACCESS,
2129 &spr_read_generic, &spr_write_booke_tsr,
2130 0x00000000);
2131 }
2132
2133 /* SPR specific to PowerPC 405 implementation */
2134 static void gen_spr_405(CPUPPCState *env)
2135 {
2136 /* MMU */
2137 spr_register(env, SPR_40x_PID, "PID",
2138 SPR_NOACCESS, SPR_NOACCESS,
2139 &spr_read_generic, &spr_write_generic,
2140 0x00000000);
2141 spr_register(env, SPR_4xx_CCR0, "CCR0",
2142 SPR_NOACCESS, SPR_NOACCESS,
2143 &spr_read_generic, &spr_write_generic,
2144 0x00700000);
2145 /* Debug interface */
2146 /* XXX : not implemented */
2147 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2148 SPR_NOACCESS, SPR_NOACCESS,
2149 &spr_read_generic, &spr_write_40x_dbcr0,
2150 0x00000000);
2151 /* XXX : not implemented */
2152 spr_register(env, SPR_405_DBCR1, "DBCR1",
2153 SPR_NOACCESS, SPR_NOACCESS,
2154 &spr_read_generic, &spr_write_generic,
2155 0x00000000);
2156 /* XXX : not implemented */
2157 spr_register(env, SPR_40x_DBSR, "DBSR",
2158 SPR_NOACCESS, SPR_NOACCESS,
2159 &spr_read_generic, &spr_write_clear,
2160 /* Last reset was system reset */
2161 0x00000300);
2162 /* XXX : not implemented */
2163 spr_register(env, SPR_40x_DAC1, "DAC1",
2164 SPR_NOACCESS, SPR_NOACCESS,
2165 &spr_read_generic, &spr_write_generic,
2166 0x00000000);
2167 spr_register(env, SPR_40x_DAC2, "DAC2",
2168 SPR_NOACCESS, SPR_NOACCESS,
2169 &spr_read_generic, &spr_write_generic,
2170 0x00000000);
2171 /* XXX : not implemented */
2172 spr_register(env, SPR_405_DVC1, "DVC1",
2173 SPR_NOACCESS, SPR_NOACCESS,
2174 &spr_read_generic, &spr_write_generic,
2175 0x00000000);
2176 /* XXX : not implemented */
2177 spr_register(env, SPR_405_DVC2, "DVC2",
2178 SPR_NOACCESS, SPR_NOACCESS,
2179 &spr_read_generic, &spr_write_generic,
2180 0x00000000);
2181 /* XXX : not implemented */
2182 spr_register(env, SPR_40x_IAC1, "IAC1",
2183 SPR_NOACCESS, SPR_NOACCESS,
2184 &spr_read_generic, &spr_write_generic,
2185 0x00000000);
2186 spr_register(env, SPR_40x_IAC2, "IAC2",
2187 SPR_NOACCESS, SPR_NOACCESS,
2188 &spr_read_generic, &spr_write_generic,
2189 0x00000000);
2190 /* XXX : not implemented */
2191 spr_register(env, SPR_405_IAC3, "IAC3",
2192 SPR_NOACCESS, SPR_NOACCESS,
2193 &spr_read_generic, &spr_write_generic,
2194 0x00000000);
2195 /* XXX : not implemented */
2196 spr_register(env, SPR_405_IAC4, "IAC4",
2197 SPR_NOACCESS, SPR_NOACCESS,
2198 &spr_read_generic, &spr_write_generic,
2199 0x00000000);
2200 /* Storage control */
2201 /* XXX: TODO: not implemented */
2202 spr_register(env, SPR_405_SLER, "SLER",
2203 SPR_NOACCESS, SPR_NOACCESS,
2204 &spr_read_generic, &spr_write_40x_sler,
2205 0x00000000);
2206 spr_register(env, SPR_40x_ZPR, "ZPR",
2207 SPR_NOACCESS, SPR_NOACCESS,
2208 &spr_read_generic, &spr_write_generic,
2209 0x00000000);
2210 /* XXX : not implemented */
2211 spr_register(env, SPR_405_SU0R, "SU0R",
2212 SPR_NOACCESS, SPR_NOACCESS,
2213 &spr_read_generic, &spr_write_generic,
2214 0x00000000);
2215 /* SPRG */
2216 spr_register(env, SPR_USPRG0, "USPRG0",
2217 &spr_read_ureg, SPR_NOACCESS,
2218 &spr_read_ureg, SPR_NOACCESS,
2219 0x00000000);
2220 spr_register(env, SPR_SPRG4, "SPRG4",
2221 SPR_NOACCESS, SPR_NOACCESS,
2222 &spr_read_generic, &spr_write_generic,
2223 0x00000000);
2224 spr_register(env, SPR_SPRG5, "SPRG5",
2225 SPR_NOACCESS, SPR_NOACCESS,
2226 spr_read_generic, &spr_write_generic,
2227 0x00000000);
2228 spr_register(env, SPR_SPRG6, "SPRG6",
2229 SPR_NOACCESS, SPR_NOACCESS,
2230 spr_read_generic, &spr_write_generic,
2231 0x00000000);
2232 spr_register(env, SPR_SPRG7, "SPRG7",
2233 SPR_NOACCESS, SPR_NOACCESS,
2234 spr_read_generic, &spr_write_generic,
2235 0x00000000);
2236 gen_spr_usprgh(env);
2237 }
2238
2239 /* SPR shared between PowerPC 401 & 403 implementations */
2240 static void gen_spr_401_403(CPUPPCState *env)
2241 {
2242 /* Time base */
2243 spr_register(env, SPR_403_VTBL, "TBL",
2244 &spr_read_tbl, SPR_NOACCESS,
2245 &spr_read_tbl, SPR_NOACCESS,
2246 0x00000000);
2247 spr_register(env, SPR_403_TBL, "TBL",
2248 SPR_NOACCESS, SPR_NOACCESS,
2249 SPR_NOACCESS, &spr_write_tbl,
2250 0x00000000);
2251 spr_register(env, SPR_403_VTBU, "TBU",
2252 &spr_read_tbu, SPR_NOACCESS,
2253 &spr_read_tbu, SPR_NOACCESS,
2254 0x00000000);
2255 spr_register(env, SPR_403_TBU, "TBU",
2256 SPR_NOACCESS, SPR_NOACCESS,
2257 SPR_NOACCESS, &spr_write_tbu,
2258 0x00000000);
2259 /* Debug */
2260 /* not emulated, as QEMU do not emulate caches */
2261 spr_register(env, SPR_403_CDBCR, "CDBCR",
2262 SPR_NOACCESS, SPR_NOACCESS,
2263 &spr_read_generic, &spr_write_generic,
2264 0x00000000);
2265 }
2266
2267 /* SPR specific to PowerPC 401 implementation */
2268 static void gen_spr_401(CPUPPCState *env)
2269 {
2270 /* Debug interface */
2271 /* XXX : not implemented */
2272 spr_register(env, SPR_40x_DBCR0, "DBCR",
2273 SPR_NOACCESS, SPR_NOACCESS,
2274 &spr_read_generic, &spr_write_40x_dbcr0,
2275 0x00000000);
2276 /* XXX : not implemented */
2277 spr_register(env, SPR_40x_DBSR, "DBSR",
2278 SPR_NOACCESS, SPR_NOACCESS,
2279 &spr_read_generic, &spr_write_clear,
2280 /* Last reset was system reset */
2281 0x00000300);
2282 /* XXX : not implemented */
2283 spr_register(env, SPR_40x_DAC1, "DAC",
2284 SPR_NOACCESS, SPR_NOACCESS,
2285 &spr_read_generic, &spr_write_generic,
2286 0x00000000);
2287 /* XXX : not implemented */
2288 spr_register(env, SPR_40x_IAC1, "IAC",
2289 SPR_NOACCESS, SPR_NOACCESS,
2290 &spr_read_generic, &spr_write_generic,
2291 0x00000000);
2292 /* Storage control */
2293 /* XXX: TODO: not implemented */
2294 spr_register(env, SPR_405_SLER, "SLER",
2295 SPR_NOACCESS, SPR_NOACCESS,
2296 &spr_read_generic, &spr_write_40x_sler,
2297 0x00000000);
2298 /* not emulated, as QEMU never does speculative access */
2299 spr_register(env, SPR_40x_SGR, "SGR",
2300 SPR_NOACCESS, SPR_NOACCESS,
2301 &spr_read_generic, &spr_write_generic,
2302 0xFFFFFFFF);
2303 /* not emulated, as QEMU do not emulate caches */
2304 spr_register(env, SPR_40x_DCWR, "DCWR",
2305 SPR_NOACCESS, SPR_NOACCESS,
2306 &spr_read_generic, &spr_write_generic,
2307 0x00000000);
2308 }
2309
2310 static void gen_spr_401x2(CPUPPCState *env)
2311 {
2312 gen_spr_401(env);
2313 spr_register(env, SPR_40x_PID, "PID",
2314 SPR_NOACCESS, SPR_NOACCESS,
2315 &spr_read_generic, &spr_write_generic,
2316 0x00000000);
2317 spr_register(env, SPR_40x_ZPR, "ZPR",
2318 SPR_NOACCESS, SPR_NOACCESS,
2319 &spr_read_generic, &spr_write_generic,
2320 0x00000000);
2321 }
2322
2323 /* SPR specific to PowerPC 403 implementation */
2324 static void gen_spr_403(CPUPPCState *env)
2325 {
2326 /* Debug interface */
2327 /* XXX : not implemented */
2328 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2329 SPR_NOACCESS, SPR_NOACCESS,
2330 &spr_read_generic, &spr_write_40x_dbcr0,
2331 0x00000000);
2332 /* XXX : not implemented */
2333 spr_register(env, SPR_40x_DBSR, "DBSR",
2334 SPR_NOACCESS, SPR_NOACCESS,
2335 &spr_read_generic, &spr_write_clear,
2336 /* Last reset was system reset */
2337 0x00000300);
2338 /* XXX : not implemented */
2339 spr_register(env, SPR_40x_DAC1, "DAC1",
2340 SPR_NOACCESS, SPR_NOACCESS,
2341 &spr_read_generic, &spr_write_generic,
2342 0x00000000);
2343 /* XXX : not implemented */
2344 spr_register(env, SPR_40x_DAC2, "DAC2",
2345 SPR_NOACCESS, SPR_NOACCESS,
2346 &spr_read_generic, &spr_write_generic,
2347 0x00000000);
2348 /* XXX : not implemented */
2349 spr_register(env, SPR_40x_IAC1, "IAC1",
2350 SPR_NOACCESS, SPR_NOACCESS,
2351 &spr_read_generic, &spr_write_generic,
2352 0x00000000);
2353 /* XXX : not implemented */
2354 spr_register(env, SPR_40x_IAC2, "IAC2",
2355 SPR_NOACCESS, SPR_NOACCESS,
2356 &spr_read_generic, &spr_write_generic,
2357 0x00000000);
2358 }
2359
2360 static void gen_spr_403_real(CPUPPCState *env)
2361 {
2362 spr_register(env, SPR_403_PBL1, "PBL1",
2363 SPR_NOACCESS, SPR_NOACCESS,
2364 &spr_read_403_pbr, &spr_write_403_pbr,
2365 0x00000000);
2366 spr_register(env, SPR_403_PBU1, "PBU1",
2367 SPR_NOACCESS, SPR_NOACCESS,
2368 &spr_read_403_pbr, &spr_write_403_pbr,
2369 0x00000000);
2370 spr_register(env, SPR_403_PBL2, "PBL2",
2371 SPR_NOACCESS, SPR_NOACCESS,
2372 &spr_read_403_pbr, &spr_write_403_pbr,
2373 0x00000000);
2374 spr_register(env, SPR_403_PBU2, "PBU2",
2375 SPR_NOACCESS, SPR_NOACCESS,
2376 &spr_read_403_pbr, &spr_write_403_pbr,
2377 0x00000000);
2378 }
2379
2380 static void gen_spr_403_mmu(CPUPPCState *env)
2381 {
2382 /* MMU */
2383 spr_register(env, SPR_40x_PID, "PID",
2384 SPR_NOACCESS, SPR_NOACCESS,
2385 &spr_read_generic, &spr_write_generic,
2386 0x00000000);
2387 spr_register(env, SPR_40x_ZPR, "ZPR",
2388 SPR_NOACCESS, SPR_NOACCESS,
2389 &spr_read_generic, &spr_write_generic,
2390 0x00000000);
2391 }
2392
2393 /* SPR specific to PowerPC compression coprocessor extension */
2394 static void gen_spr_compress(CPUPPCState *env)
2395 {
2396 /* XXX : not implemented */
2397 spr_register(env, SPR_401_SKR, "SKR",
2398 SPR_NOACCESS, SPR_NOACCESS,
2399 &spr_read_generic, &spr_write_generic,
2400 0x00000000);
2401 }
2402
2403 static void gen_spr_5xx_8xx(CPUPPCState *env)
2404 {
2405 /* Exception processing */
2406 spr_register_kvm(env, SPR_DSISR, "DSISR",
2407 SPR_NOACCESS, SPR_NOACCESS,
2408 &spr_read_generic, &spr_write_generic,
2409 KVM_REG_PPC_DSISR, 0x00000000);
2410 spr_register_kvm(env, SPR_DAR, "DAR",
2411 SPR_NOACCESS, SPR_NOACCESS,
2412 &spr_read_generic, &spr_write_generic,
2413 KVM_REG_PPC_DAR, 0x00000000);
2414 /* Timer */
2415 spr_register(env, SPR_DECR, "DECR",
2416 SPR_NOACCESS, SPR_NOACCESS,
2417 &spr_read_decr, &spr_write_decr,
2418 0x00000000);
2419 /* XXX : not implemented */
2420 spr_register(env, SPR_MPC_EIE, "EIE",
2421 SPR_NOACCESS, SPR_NOACCESS,
2422 &spr_read_generic, &spr_write_generic,
2423 0x00000000);
2424 /* XXX : not implemented */
2425 spr_register(env, SPR_MPC_EID, "EID",
2426 SPR_NOACCESS, SPR_NOACCESS,
2427 &spr_read_generic, &spr_write_generic,
2428 0x00000000);
2429 /* XXX : not implemented */
2430 spr_register(env, SPR_MPC_NRI, "NRI",
2431 SPR_NOACCESS, SPR_NOACCESS,
2432 &spr_read_generic, &spr_write_generic,
2433 0x00000000);
2434 /* XXX : not implemented */
2435 spr_register(env, SPR_MPC_CMPA, "CMPA",
2436 SPR_NOACCESS, SPR_NOACCESS,
2437 &spr_read_generic, &spr_write_generic,
2438 0x00000000);
2439 /* XXX : not implemented */
2440 spr_register(env, SPR_MPC_CMPB, "CMPB",
2441 SPR_NOACCESS, SPR_NOACCESS,
2442 &spr_read_generic, &spr_write_generic,
2443 0x00000000);
2444 /* XXX : not implemented */
2445 spr_register(env, SPR_MPC_CMPC, "CMPC",
2446 SPR_NOACCESS, SPR_NOACCESS,
2447 &spr_read_generic, &spr_write_generic,
2448 0x00000000);
2449 /* XXX : not implemented */
2450 spr_register(env, SPR_MPC_CMPD, "CMPD",
2451 SPR_NOACCESS, SPR_NOACCESS,
2452 &spr_read_generic, &spr_write_generic,
2453 0x00000000);
2454 /* XXX : not implemented */
2455 spr_register(env, SPR_MPC_ECR, "ECR",
2456 SPR_NOACCESS, SPR_NOACCESS,
2457 &spr_read_generic, &spr_write_generic,
2458 0x00000000);
2459 /* XXX : not implemented */
2460 spr_register(env, SPR_MPC_DER, "DER",
2461 SPR_NOACCESS, SPR_NOACCESS,
2462 &spr_read_generic, &spr_write_generic,
2463 0x00000000);
2464 /* XXX : not implemented */
2465 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2466 SPR_NOACCESS, SPR_NOACCESS,
2467 &spr_read_generic, &spr_write_generic,
2468 0x00000000);
2469 /* XXX : not implemented */
2470 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2471 SPR_NOACCESS, SPR_NOACCESS,
2472 &spr_read_generic, &spr_write_generic,
2473 0x00000000);
2474 /* XXX : not implemented */
2475 spr_register(env, SPR_MPC_CMPE, "CMPE",
2476 SPR_NOACCESS, SPR_NOACCESS,
2477 &spr_read_generic, &spr_write_generic,
2478 0x00000000);
2479 /* XXX : not implemented */
2480 spr_register(env, SPR_MPC_CMPF, "CMPF",
2481 SPR_NOACCESS, SPR_NOACCESS,
2482 &spr_read_generic, &spr_write_generic,
2483 0x00000000);
2484 /* XXX : not implemented */
2485 spr_register(env, SPR_MPC_CMPG, "CMPG",
2486 SPR_NOACCESS, SPR_NOACCESS,
2487 &spr_read_generic, &spr_write_generic,
2488 0x00000000);
2489 /* XXX : not implemented */
2490 spr_register(env, SPR_MPC_CMPH, "CMPH",
2491 SPR_NOACCESS, SPR_NOACCESS,
2492 &spr_read_generic, &spr_write_generic,
2493 0x00000000);
2494 /* XXX : not implemented */
2495 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2496 SPR_NOACCESS, SPR_NOACCESS,
2497 &spr_read_generic, &spr_write_generic,
2498 0x00000000);
2499 /* XXX : not implemented */
2500 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2501 SPR_NOACCESS, SPR_NOACCESS,
2502 &spr_read_generic, &spr_write_generic,
2503 0x00000000);
2504 /* XXX : not implemented */
2505 spr_register(env, SPR_MPC_BAR, "BAR",
2506 SPR_NOACCESS, SPR_NOACCESS,
2507 &spr_read_generic, &spr_write_generic,
2508 0x00000000);
2509 /* XXX : not implemented */
2510 spr_register(env, SPR_MPC_DPDR, "DPDR",
2511 SPR_NOACCESS, SPR_NOACCESS,
2512 &spr_read_generic, &spr_write_generic,
2513 0x00000000);
2514 /* XXX : not implemented */
2515 spr_register(env, SPR_MPC_IMMR, "IMMR",
2516 SPR_NOACCESS, SPR_NOACCESS,
2517 &spr_read_generic, &spr_write_generic,
2518 0x00000000);
2519 }
2520
2521 static void gen_spr_5xx(CPUPPCState *env)
2522 {
2523 /* XXX : not implemented */
2524 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2525 SPR_NOACCESS, SPR_NOACCESS,
2526 &spr_read_generic, &spr_write_generic,
2527 0x00000000);
2528 /* XXX : not implemented */
2529 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2530 SPR_NOACCESS, SPR_NOACCESS,
2531 &spr_read_generic, &spr_write_generic,
2532 0x00000000);
2533 /* XXX : not implemented */
2534 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2535 SPR_NOACCESS, SPR_NOACCESS,
2536 &spr_read_generic, &spr_write_generic,
2537 0x00000000);
2538 /* XXX : not implemented */
2539 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2540 SPR_NOACCESS, SPR_NOACCESS,
2541 &spr_read_generic, &spr_write_generic,
2542 0x00000000);
2543 /* XXX : not implemented */
2544 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2545 SPR_NOACCESS, SPR_NOACCESS,
2546 &spr_read_generic, &spr_write_generic,
2547 0x00000000);
2548 /* XXX : not implemented */
2549 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2550 SPR_NOACCESS, SPR_NOACCESS,
2551 &spr_read_generic, &spr_write_generic,
2552 0x00000000);
2553 /* XXX : not implemented */
2554 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2555 SPR_NOACCESS, SPR_NOACCESS,
2556 &spr_read_generic, &spr_write_generic,
2557 0x00000000);
2558 /* XXX : not implemented */
2559 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2560 SPR_NOACCESS, SPR_NOACCESS,
2561 &spr_read_generic, &spr_write_generic,
2562 0x00000000);
2563 /* XXX : not implemented */
2564 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2565 SPR_NOACCESS, SPR_NOACCESS,
2566 &spr_read_generic, &spr_write_generic,
2567 0x00000000);
2568 /* XXX : not implemented */
2569 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2570 SPR_NOACCESS, SPR_NOACCESS,
2571 &spr_read_generic, &spr_write_generic,
2572 0x00000000);
2573 /* XXX : not implemented */
2574 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2575 SPR_NOACCESS, SPR_NOACCESS,
2576 &spr_read_generic, &spr_write_generic,
2577 0x00000000);
2578 /* XXX : not implemented */
2579 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2580 SPR_NOACCESS, SPR_NOACCESS,
2581 &spr_read_generic, &spr_write_generic,
2582 0x00000000);
2583 /* XXX : not implemented */
2584 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2585 SPR_NOACCESS, SPR_NOACCESS,
2586 &spr_read_generic, &spr_write_generic,
2587 0x00000000);
2588 /* XXX : not implemented */
2589 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2590 SPR_NOACCESS, SPR_NOACCESS,
2591 &spr_read_generic, &spr_write_generic,
2592 0x00000000);
2593 /* XXX : not implemented */
2594 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2595 SPR_NOACCESS, SPR_NOACCESS,
2596 &spr_read_generic, &spr_write_generic,
2597 0x00000000);
2598 /* XXX : not implemented */
2599 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2600 SPR_NOACCESS, SPR_NOACCESS,
2601 &spr_read_generic, &spr_write_generic,
2602 0x00000000);
2603 /* XXX : not implemented */
2604 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2605 SPR_NOACCESS, SPR_NOACCESS,
2606 &spr_read_generic, &spr_write_generic,
2607 0x00000000);
2608 /* XXX : not implemented */
2609 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2610 SPR_NOACCESS, SPR_NOACCESS,
2611 &spr_read_generic, &spr_write_generic,
2612 0x00000000);
2613 /* XXX : not implemented */
2614 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2615 SPR_NOACCESS, SPR_NOACCESS,
2616 &spr_read_generic, &spr_write_generic,
2617 0x00000000);
2618 /* XXX : not implemented */
2619 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2620 SPR_NOACCESS, SPR_NOACCESS,
2621 &spr_read_generic, &spr_write_generic,
2622 0x00000000);
2623 /* XXX : not implemented */
2624 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2625 SPR_NOACCESS, SPR_NOACCESS,
2626 &spr_read_generic, &spr_write_generic,
2627 0x00000000);
2628 }
2629
2630 static void gen_spr_8xx(CPUPPCState *env)
2631 {
2632 /* XXX : not implemented */
2633 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2634 SPR_NOACCESS, SPR_NOACCESS,
2635 &spr_read_generic, &spr_write_generic,
2636 0x00000000);
2637 /* XXX : not implemented */
2638 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2639 SPR_NOACCESS, SPR_NOACCESS,
2640 &spr_read_generic, &spr_write_generic,
2641 0x00000000);
2642 /* XXX : not implemented */
2643 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2644 SPR_NOACCESS, SPR_NOACCESS,
2645 &spr_read_generic, &spr_write_generic,
2646 0x00000000);
2647 /* XXX : not implemented */
2648 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2649 SPR_NOACCESS, SPR_NOACCESS,
2650 &spr_read_generic, &spr_write_generic,
2651 0x00000000);
2652 /* XXX : not implemented */
2653 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2654 SPR_NOACCESS, SPR_NOACCESS,
2655 &spr_read_generic, &spr_write_generic,
2656 0x00000000);
2657 /* XXX : not implemented */
2658 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2659 SPR_NOACCESS, SPR_NOACCESS,
2660 &spr_read_generic, &spr_write_generic,
2661 0x00000000);
2662 /* XXX : not implemented */
2663 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2664 SPR_NOACCESS, SPR_NOACCESS,
2665 &spr_read_generic, &spr_write_generic,
2666 0x00000000);
2667 /* XXX : not implemented */
2668 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2669 SPR_NOACCESS, SPR_NOACCESS,
2670 &spr_read_generic, &spr_write_generic,
2671 0x00000000);
2672 /* XXX : not implemented */
2673 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2674 SPR_NOACCESS, SPR_NOACCESS,
2675 &spr_read_generic, &spr_write_generic,
2676 0x00000000);
2677 /* XXX : not implemented */
2678 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2679 SPR_NOACCESS, SPR_NOACCESS,
2680 &spr_read_generic, &spr_write_generic,
2681 0x00000000);
2682 /* XXX : not implemented */
2683 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2684 SPR_NOACCESS, SPR_NOACCESS,
2685 &spr_read_generic, &spr_write_generic,
2686 0x00000000);
2687 /* XXX : not implemented */
2688 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2689 SPR_NOACCESS, SPR_NOACCESS,
2690 &spr_read_generic, &spr_write_generic,
2691 0x00000000);
2692 /* XXX : not implemented */
2693 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2694 SPR_NOACCESS, SPR_NOACCESS,
2695 &spr_read_generic, &spr_write_generic,
2696 0x00000000);
2697 /* XXX : not implemented */
2698 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2699 SPR_NOACCESS, SPR_NOACCESS,
2700 &spr_read_generic, &spr_write_generic,
2701 0x00000000);
2702 /* XXX : not implemented */
2703 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2704 SPR_NOACCESS, SPR_NOACCESS,
2705 &spr_read_generic, &spr_write_generic,
2706 0x00000000);
2707 /* XXX : not implemented */
2708 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2709 SPR_NOACCESS, SPR_NOACCESS,
2710 &spr_read_generic, &spr_write_generic,
2711 0x00000000);
2712 /* XXX : not implemented */
2713 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2714 SPR_NOACCESS, SPR_NOACCESS,
2715 &spr_read_generic, &spr_write_generic,
2716 0x00000000);
2717 /* XXX : not implemented */
2718 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2719 SPR_NOACCESS, SPR_NOACCESS,
2720 &spr_read_generic, &spr_write_generic,
2721 0x00000000);
2722 /* XXX : not implemented */
2723 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2724 SPR_NOACCESS, SPR_NOACCESS,
2725 &spr_read_generic, &spr_write_generic,
2726 0x00000000);
2727 /* XXX : not implemented */
2728 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2729 SPR_NOACCESS, SPR_NOACCESS,
2730 &spr_read_generic, &spr_write_generic,
2731 0x00000000);
2732 /* XXX : not implemented */
2733 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2734 SPR_NOACCESS, SPR_NOACCESS,
2735 &spr_read_generic, &spr_write_generic,
2736 0x00000000);
2737 /* XXX : not implemented */
2738 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2739 SPR_NOACCESS, SPR_NOACCESS,
2740 &spr_read_generic, &spr_write_generic,
2741 0x00000000);
2742 /* XXX : not implemented */
2743 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2744 SPR_NOACCESS, SPR_NOACCESS,
2745 &spr_read_generic, &spr_write_generic,
2746 0x00000000);
2747 /* XXX : not implemented */
2748 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2749 SPR_NOACCESS, SPR_NOACCESS,
2750 &spr_read_generic, &spr_write_generic,
2751 0x00000000);
2752 /* XXX : not implemented */
2753 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2754 SPR_NOACCESS, SPR_NOACCESS,
2755 &spr_read_generic, &spr_write_generic,
2756 0x00000000);
2757 }
2758
2759 // XXX: TODO
2760 /*
2761 * AMR => SPR 29 (Power 2.04)
2762 * CTRL => SPR 136 (Power 2.04)
2763 * CTRL => SPR 152 (Power 2.04)
2764 * SCOMC => SPR 276 (64 bits ?)
2765 * SCOMD => SPR 277 (64 bits ?)
2766 * TBU40 => SPR 286 (Power 2.04 hypv)
2767 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2768 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2769 * HDSISR => SPR 306 (Power 2.04 hypv)
2770 * HDAR => SPR 307 (Power 2.04 hypv)
2771 * PURR => SPR 309 (Power 2.04 hypv)
2772 * HDEC => SPR 310 (Power 2.04 hypv)
2773 * HIOR => SPR 311 (hypv)
2774 * RMOR => SPR 312 (970)
2775 * HRMOR => SPR 313 (Power 2.04 hypv)
2776 * HSRR0 => SPR 314 (Power 2.04 hypv)
2777 * HSRR1 => SPR 315 (Power 2.04 hypv)
2778 * LPIDR => SPR 317 (970)
2779 * EPR => SPR 702 (Power 2.04 emb)
2780 * perf => 768-783 (Power 2.04)
2781 * perf => 784-799 (Power 2.04)
2782 * PPR => SPR 896 (Power 2.04)
2783 * EPLC => SPR 947 (Power 2.04 emb)
2784 * EPSC => SPR 948 (Power 2.04 emb)
2785 * DABRX => 1015 (Power 2.04 hypv)
2786 * FPECR => SPR 1022 (?)
2787 * ... and more (thermal management, performance counters, ...)
2788 */
2789
2790 /*****************************************************************************/
2791 /* Exception vectors models */
2792 static void init_excp_4xx_real(CPUPPCState *env)
2793 {
2794 #if !defined(CONFIG_USER_ONLY)
2795 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2796 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2797 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2798 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2799 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2800 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2801 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2802 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2803 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2804 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2805 env->ivor_mask = 0x0000FFF0UL;
2806 env->ivpr_mask = 0xFFFF0000UL;
2807 /* Hardware reset vector */
2808 env->hreset_vector = 0xFFFFFFFCUL;
2809 #endif
2810 }
2811
2812 static void init_excp_4xx_softmmu(CPUPPCState *env)
2813 {
2814 #if !defined(CONFIG_USER_ONLY)
2815 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2816 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2817 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2818 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2819 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2820 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2821 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2822 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2823 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2824 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2825 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2826 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2827 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2828 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2829 env->ivor_mask = 0x0000FFF0UL;
2830 env->ivpr_mask = 0xFFFF0000UL;
2831 /* Hardware reset vector */
2832 env->hreset_vector = 0xFFFFFFFCUL;
2833 #endif
2834 }
2835
2836 static void init_excp_MPC5xx(CPUPPCState *env)
2837 {
2838 #if !defined(CONFIG_USER_ONLY)
2839 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2840 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2841 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2842 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2843 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2844 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2845 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2846 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2847 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2848 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2849 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2850 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2851 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2852 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2853 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2854 env->ivor_mask = 0x0000FFF0UL;
2855 env->ivpr_mask = 0xFFFF0000UL;
2856 /* Hardware reset vector */
2857 env->hreset_vector = 0x00000100UL;
2858 #endif
2859 }
2860
2861 static void init_excp_MPC8xx(CPUPPCState *env)
2862 {
2863 #if !defined(CONFIG_USER_ONLY)
2864 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2865 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2866 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2867 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2868 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2869 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2870 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2871 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2872 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2873 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2874 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2875 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2876 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2877 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2878 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2879 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2880 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2881 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2882 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2883 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2884 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2885 env->ivor_mask = 0x0000FFF0UL;
2886 env->ivpr_mask = 0xFFFF0000UL;
2887 /* Hardware reset vector */
2888 env->hreset_vector = 0x00000100UL;
2889 #endif
2890 }
2891
2892 static void init_excp_G2(CPUPPCState *env)
2893 {
2894 #if !defined(CONFIG_USER_ONLY)
2895 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2896 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2897 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2898 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2899 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2900 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2901 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2902 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2903 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2904 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2905 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2906 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2907 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2908 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2909 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2910 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2911 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2912 /* Hardware reset vector */
2913 env->hreset_vector = 0x00000100UL;
2914 #endif
2915 }
2916
2917 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2918 {
2919 #if !defined(CONFIG_USER_ONLY)
2920 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2921 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2922 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2923 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2924 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2925 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2926 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2927 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2928 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2929 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2930 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2931 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2932 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2933 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2934 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2935 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2936 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2937 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2938 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2939 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2940 env->ivor_mask = 0x0000FFF7UL;
2941 env->ivpr_mask = ivpr_mask;
2942 /* Hardware reset vector */
2943 env->hreset_vector = 0xFFFFFFFCUL;
2944 #endif
2945 }
2946
2947 static void init_excp_BookE(CPUPPCState *env)
2948 {
2949 #if !defined(CONFIG_USER_ONLY)
2950 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2951 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2952 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2953 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2954 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2955 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2956 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2957 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2958 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2959 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2960 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2961 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2962 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2963 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2964 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2965 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2966 env->ivor_mask = 0x0000FFF0UL;
2967 env->ivpr_mask = 0xFFFF0000UL;
2968 /* Hardware reset vector */
2969 env->hreset_vector = 0xFFFFFFFCUL;
2970 #endif
2971 }
2972
2973 static void init_excp_601(CPUPPCState *env)
2974 {
2975 #if !defined(CONFIG_USER_ONLY)
2976 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2977 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2978 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2979 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2980 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2981 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2982 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2983 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2984 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2985 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2986 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2987 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2988 /* Hardware reset vector */
2989 env->hreset_vector = 0x00000100UL;
2990 #endif
2991 }
2992
2993 static void init_excp_602(CPUPPCState *env)
2994 {
2995 #if !defined(CONFIG_USER_ONLY)
2996 /* XXX: exception prefix has a special behavior on 602 */
2997 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2998 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2999 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3000 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3001 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3002 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3003 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3004 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3005 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3006 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3007 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3008 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3009 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3010 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3011 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3012 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3013 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
3014 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
3015 /* Hardware reset vector */
3016 env->hreset_vector = 0x00000100UL;
3017 #endif
3018 }
3019
3020 static void init_excp_603(CPUPPCState *env)
3021 {
3022 #if !defined(CONFIG_USER_ONLY)
3023 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3024 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3025 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3026 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3027 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3028 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3029 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3030 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3031 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3032 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3033 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3034 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3035 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3036 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3037 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3038 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3039 /* Hardware reset vector */
3040 env->hreset_vector = 0x00000100UL;
3041 #endif
3042 }
3043
3044 static void init_excp_604(CPUPPCState *env)
3045 {
3046 #if !defined(CONFIG_USER_ONLY)
3047 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3048 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3049 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3050 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3051 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3052 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3053 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3054 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3055 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3056 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3057 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3058 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3059 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3060 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3061 /* Hardware reset vector */
3062 env->hreset_vector = 0x00000100UL;
3063 #endif
3064 }
3065
3066 static void init_excp_7x0(CPUPPCState *env)
3067 {
3068 #if !defined(CONFIG_USER_ONLY)
3069 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3070 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3071 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3072 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3073 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3074 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3075 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3076 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3077 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3078 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3079 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3080 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3081 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3082 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3083 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
3084 /* Hardware reset vector */
3085 env->hreset_vector = 0x00000100UL;
3086 #endif
3087 }
3088
3089 static void init_excp_750cl(CPUPPCState *env)
3090 {
3091 #if !defined(CONFIG_USER_ONLY)
3092 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3093 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3094 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3095 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3096 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3097 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3098 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;