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[qemu.git] / target / ppc / translate_init.inc.c
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "disas/dis-asm.h"
22 #include "exec/gdbstub.h"
23 #include "kvm_ppc.h"
24 #include "sysemu/arch_init.h"
25 #include "sysemu/cpus.h"
26 #include "sysemu/hw_accel.h"
27 #include "sysemu/tcg.h"
28 #include "cpu-models.h"
29 #include "mmu-hash32.h"
30 #include "mmu-hash64.h"
31 #include "qemu/error-report.h"
32 #include "qemu/module.h"
33 #include "qemu/qemu-print.h"
34 #include "qapi/error.h"
35 #include "qapi/qmp/qnull.h"
36 #include "qapi/visitor.h"
37 #include "hw/qdev-properties.h"
38 #include "hw/ppc/ppc.h"
39 #include "mmu-book3s-v3.h"
40 #include "sysemu/qtest.h"
41 #include "qemu/cutils.h"
42 #include "disas/capstone.h"
43 #include "fpu/softfloat.h"
44 #include "qapi/qapi-commands-machine-target.h"
45
46 /* #define PPC_DUMP_CPU */
47 /* #define PPC_DEBUG_SPR */
48 /* #define PPC_DUMP_SPR_ACCESSES */
49 /* #define USE_APPLE_GDB */
50
51 /*
52 * Generic callbacks:
53 * do nothing but store/retrieve spr value
54 */
55 static void spr_load_dump_spr(int sprn)
56 {
57 #ifdef PPC_DUMP_SPR_ACCESSES
58 TCGv_i32 t0 = tcg_const_i32(sprn);
59 gen_helper_load_dump_spr(cpu_env, t0);
60 tcg_temp_free_i32(t0);
61 #endif
62 }
63
64 static void spr_read_generic(DisasContext *ctx, int gprn, int sprn)
65 {
66 gen_load_spr(cpu_gpr[gprn], sprn);
67 spr_load_dump_spr(sprn);
68 }
69
70 static void spr_store_dump_spr(int sprn)
71 {
72 #ifdef PPC_DUMP_SPR_ACCESSES
73 TCGv_i32 t0 = tcg_const_i32(sprn);
74 gen_helper_store_dump_spr(cpu_env, t0);
75 tcg_temp_free_i32(t0);
76 #endif
77 }
78
79 static void spr_write_generic(DisasContext *ctx, int sprn, int gprn)
80 {
81 gen_store_spr(sprn, cpu_gpr[gprn]);
82 spr_store_dump_spr(sprn);
83 }
84
85 #if !defined(CONFIG_USER_ONLY)
86 static void spr_write_generic32(DisasContext *ctx, int sprn, int gprn)
87 {
88 #ifdef TARGET_PPC64
89 TCGv t0 = tcg_temp_new();
90 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
91 gen_store_spr(sprn, t0);
92 tcg_temp_free(t0);
93 spr_store_dump_spr(sprn);
94 #else
95 spr_write_generic(ctx, sprn, gprn);
96 #endif
97 }
98
99 static void spr_write_clear(DisasContext *ctx, int sprn, int gprn)
100 {
101 TCGv t0 = tcg_temp_new();
102 TCGv t1 = tcg_temp_new();
103 gen_load_spr(t0, sprn);
104 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
105 tcg_gen_and_tl(t0, t0, t1);
106 gen_store_spr(sprn, t0);
107 tcg_temp_free(t0);
108 tcg_temp_free(t1);
109 }
110
111 static void spr_access_nop(DisasContext *ctx, int sprn, int gprn)
112 {
113 }
114
115 #endif
116
117 /* SPR common to all PowerPC */
118 /* XER */
119 static void spr_read_xer(DisasContext *ctx, int gprn, int sprn)
120 {
121 gen_read_xer(ctx, cpu_gpr[gprn]);
122 }
123
124 static void spr_write_xer(DisasContext *ctx, int sprn, int gprn)
125 {
126 gen_write_xer(cpu_gpr[gprn]);
127 }
128
129 /* LR */
130 static void spr_read_lr(DisasContext *ctx, int gprn, int sprn)
131 {
132 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
133 }
134
135 static void spr_write_lr(DisasContext *ctx, int sprn, int gprn)
136 {
137 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
138 }
139
140 /* CFAR */
141 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
142 static void spr_read_cfar(DisasContext *ctx, int gprn, int sprn)
143 {
144 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
145 }
146
147 static void spr_write_cfar(DisasContext *ctx, int sprn, int gprn)
148 {
149 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
150 }
151 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
152
153 /* CTR */
154 static void spr_read_ctr(DisasContext *ctx, int gprn, int sprn)
155 {
156 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
157 }
158
159 static void spr_write_ctr(DisasContext *ctx, int sprn, int gprn)
160 {
161 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
162 }
163
164 /* User read access to SPR */
165 /* USPRx */
166 /* UMMCRx */
167 /* UPMCx */
168 /* USIA */
169 /* UDECR */
170 static void spr_read_ureg(DisasContext *ctx, int gprn, int sprn)
171 {
172 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
173 }
174
175 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
176 static void spr_write_ureg(DisasContext *ctx, int sprn, int gprn)
177 {
178 gen_store_spr(sprn + 0x10, cpu_gpr[gprn]);
179 }
180 #endif
181
182 /* SPR common to all non-embedded PowerPC */
183 /* DECR */
184 #if !defined(CONFIG_USER_ONLY)
185 static void spr_read_decr(DisasContext *ctx, int gprn, int sprn)
186 {
187 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
188 gen_io_start();
189 }
190 gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
191 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
192 gen_stop_exception(ctx);
193 }
194 }
195
196 static void spr_write_decr(DisasContext *ctx, int sprn, int gprn)
197 {
198 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
199 gen_io_start();
200 }
201 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
202 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
203 gen_stop_exception(ctx);
204 }
205 }
206 #endif
207
208 /* SPR common to all non-embedded PowerPC, except 601 */
209 /* Time base */
210 static void spr_read_tbl(DisasContext *ctx, int gprn, int sprn)
211 {
212 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
213 gen_io_start();
214 }
215 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
216 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
217 gen_io_end();
218 gen_stop_exception(ctx);
219 }
220 }
221
222 static void spr_read_tbu(DisasContext *ctx, int gprn, int sprn)
223 {
224 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
225 gen_io_start();
226 }
227 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
228 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
229 gen_io_end();
230 gen_stop_exception(ctx);
231 }
232 }
233
234 ATTRIBUTE_UNUSED
235 static void spr_read_atbl(DisasContext *ctx, int gprn, int sprn)
236 {
237 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
238 }
239
240 ATTRIBUTE_UNUSED
241 static void spr_read_atbu(DisasContext *ctx, int gprn, int sprn)
242 {
243 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
244 }
245
246 #if !defined(CONFIG_USER_ONLY)
247 static void spr_write_tbl(DisasContext *ctx, int sprn, int gprn)
248 {
249 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
250 gen_io_start();
251 }
252 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
253 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
254 gen_io_end();
255 gen_stop_exception(ctx);
256 }
257 }
258
259 static void spr_write_tbu(DisasContext *ctx, int sprn, int gprn)
260 {
261 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
262 gen_io_start();
263 }
264 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
265 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
266 gen_io_end();
267 gen_stop_exception(ctx);
268 }
269 }
270
271 ATTRIBUTE_UNUSED
272 static void spr_write_atbl(DisasContext *ctx, int sprn, int gprn)
273 {
274 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
275 }
276
277 ATTRIBUTE_UNUSED
278 static void spr_write_atbu(DisasContext *ctx, int sprn, int gprn)
279 {
280 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
281 }
282
283 #if defined(TARGET_PPC64)
284 ATTRIBUTE_UNUSED
285 static void spr_read_purr(DisasContext *ctx, int gprn, int sprn)
286 {
287 gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
288 }
289
290 static void spr_write_purr(DisasContext *ctx, int sprn, int gprn)
291 {
292 gen_helper_store_purr(cpu_env, cpu_gpr[gprn]);
293 }
294
295 /* HDECR */
296 static void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn)
297 {
298 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
299 gen_io_start();
300 }
301 gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env);
302 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
303 gen_io_end();
304 gen_stop_exception(ctx);
305 }
306 }
307
308 static void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn)
309 {
310 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
311 gen_io_start();
312 }
313 gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]);
314 if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
315 gen_io_end();
316 gen_stop_exception(ctx);
317 }
318 }
319
320 static void spr_read_vtb(DisasContext *ctx, int gprn, int sprn)
321 {
322 gen_helper_load_vtb(cpu_gpr[gprn], cpu_env);
323 }
324
325 static void spr_write_vtb(DisasContext *ctx, int sprn, int gprn)
326 {
327 gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]);
328 }
329
330 static void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn)
331 {
332 gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]);
333 }
334
335 #endif
336 #endif
337
338 #if !defined(CONFIG_USER_ONLY)
339 /* IBAT0U...IBAT0U */
340 /* IBAT0L...IBAT7L */
341 static void spr_read_ibat(DisasContext *ctx, int gprn, int sprn)
342 {
343 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
344 offsetof(CPUPPCState,
345 IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
346 }
347
348 static void spr_read_ibat_h(DisasContext *ctx, int gprn, int sprn)
349 {
350 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
351 offsetof(CPUPPCState,
352 IBAT[sprn & 1][((sprn - SPR_IBAT4U) / 2) + 4]));
353 }
354
355 static void spr_write_ibatu(DisasContext *ctx, int sprn, int gprn)
356 {
357 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
358 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
359 tcg_temp_free_i32(t0);
360 }
361
362 static void spr_write_ibatu_h(DisasContext *ctx, int sprn, int gprn)
363 {
364 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
365 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
366 tcg_temp_free_i32(t0);
367 }
368
369 static void spr_write_ibatl(DisasContext *ctx, int sprn, int gprn)
370 {
371 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
372 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
373 tcg_temp_free_i32(t0);
374 }
375
376 static void spr_write_ibatl_h(DisasContext *ctx, int sprn, int gprn)
377 {
378 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
379 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
380 tcg_temp_free_i32(t0);
381 }
382
383 /* DBAT0U...DBAT7U */
384 /* DBAT0L...DBAT7L */
385 static void spr_read_dbat(DisasContext *ctx, int gprn, int sprn)
386 {
387 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
388 offsetof(CPUPPCState,
389 DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
390 }
391
392 static void spr_read_dbat_h(DisasContext *ctx, int gprn, int sprn)
393 {
394 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
395 offsetof(CPUPPCState,
396 DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
397 }
398
399 static void spr_write_dbatu(DisasContext *ctx, int sprn, int gprn)
400 {
401 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
402 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
403 tcg_temp_free_i32(t0);
404 }
405
406 static void spr_write_dbatu_h(DisasContext *ctx, int sprn, int gprn)
407 {
408 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
409 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
410 tcg_temp_free_i32(t0);
411 }
412
413 static void spr_write_dbatl(DisasContext *ctx, int sprn, int gprn)
414 {
415 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
416 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
417 tcg_temp_free_i32(t0);
418 }
419
420 static void spr_write_dbatl_h(DisasContext *ctx, int sprn, int gprn)
421 {
422 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
423 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
424 tcg_temp_free_i32(t0);
425 }
426
427 /* SDR1 */
428 static void spr_write_sdr1(DisasContext *ctx, int sprn, int gprn)
429 {
430 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
431 }
432
433 #if defined(TARGET_PPC64)
434 /* 64 bits PowerPC specific SPRs */
435 /* PIDR */
436 static void spr_write_pidr(DisasContext *ctx, int sprn, int gprn)
437 {
438 gen_helper_store_pidr(cpu_env, cpu_gpr[gprn]);
439 }
440
441 static void spr_write_lpidr(DisasContext *ctx, int sprn, int gprn)
442 {
443 gen_helper_store_lpidr(cpu_env, cpu_gpr[gprn]);
444 }
445
446 static void spr_read_hior(DisasContext *ctx, int gprn, int sprn)
447 {
448 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
449 }
450
451 static void spr_write_hior(DisasContext *ctx, int sprn, int gprn)
452 {
453 TCGv t0 = tcg_temp_new();
454 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
455 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
456 tcg_temp_free(t0);
457 }
458 static void spr_write_ptcr(DisasContext *ctx, int sprn, int gprn)
459 {
460 gen_helper_store_ptcr(cpu_env, cpu_gpr[gprn]);
461 }
462
463 static void spr_write_pcr(DisasContext *ctx, int sprn, int gprn)
464 {
465 gen_helper_store_pcr(cpu_env, cpu_gpr[gprn]);
466 }
467
468 /* DPDES */
469 static void spr_read_dpdes(DisasContext *ctx, int gprn, int sprn)
470 {
471 gen_helper_load_dpdes(cpu_gpr[gprn], cpu_env);
472 }
473
474 static void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn)
475 {
476 gen_helper_store_dpdes(cpu_env, cpu_gpr[gprn]);
477 }
478 #endif
479 #endif
480
481 /* PowerPC 601 specific registers */
482 /* RTC */
483 static void spr_read_601_rtcl(DisasContext *ctx, int gprn, int sprn)
484 {
485 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
486 }
487
488 static void spr_read_601_rtcu(DisasContext *ctx, int gprn, int sprn)
489 {
490 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
491 }
492
493 #if !defined(CONFIG_USER_ONLY)
494 static void spr_write_601_rtcu(DisasContext *ctx, int sprn, int gprn)
495 {
496 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
497 }
498
499 static void spr_write_601_rtcl(DisasContext *ctx, int sprn, int gprn)
500 {
501 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
502 }
503
504 static void spr_write_hid0_601(DisasContext *ctx, int sprn, int gprn)
505 {
506 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
507 /* Must stop the translation as endianness may have changed */
508 gen_stop_exception(ctx);
509 }
510 #endif
511
512 /* Unified bats */
513 #if !defined(CONFIG_USER_ONLY)
514 static void spr_read_601_ubat(DisasContext *ctx, int gprn, int sprn)
515 {
516 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
517 offsetof(CPUPPCState,
518 IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
519 }
520
521 static void spr_write_601_ubatu(DisasContext *ctx, int sprn, int gprn)
522 {
523 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
524 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
525 tcg_temp_free_i32(t0);
526 }
527
528 static void spr_write_601_ubatl(DisasContext *ctx, int sprn, int gprn)
529 {
530 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
531 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
532 tcg_temp_free_i32(t0);
533 }
534 #endif
535
536 /* PowerPC 40x specific registers */
537 #if !defined(CONFIG_USER_ONLY)
538 static void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn)
539 {
540 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
541 }
542
543 static void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn)
544 {
545 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
546 }
547
548 static void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn)
549 {
550 gen_store_spr(sprn, cpu_gpr[gprn]);
551 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
552 /* We must stop translation as we may have rebooted */
553 gen_stop_exception(ctx);
554 }
555
556 static void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn)
557 {
558 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
559 }
560
561 static void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn)
562 {
563 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
564 }
565
566 static void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn)
567 {
568 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
569 }
570 #endif
571
572 /* PowerPC 403 specific registers */
573 /* PBL1 / PBU1 / PBL2 / PBU2 */
574 #if !defined(CONFIG_USER_ONLY)
575 static void spr_read_403_pbr(DisasContext *ctx, int gprn, int sprn)
576 {
577 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env,
578 offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
579 }
580
581 static void spr_write_403_pbr(DisasContext *ctx, int sprn, int gprn)
582 {
583 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
584 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
585 tcg_temp_free_i32(t0);
586 }
587
588 static void spr_write_pir(DisasContext *ctx, int sprn, int gprn)
589 {
590 TCGv t0 = tcg_temp_new();
591 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
592 gen_store_spr(SPR_PIR, t0);
593 tcg_temp_free(t0);
594 }
595 #endif
596
597 /* SPE specific registers */
598 static void spr_read_spefscr(DisasContext *ctx, int gprn, int sprn)
599 {
600 TCGv_i32 t0 = tcg_temp_new_i32();
601 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
602 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
603 tcg_temp_free_i32(t0);
604 }
605
606 static void spr_write_spefscr(DisasContext *ctx, int sprn, int gprn)
607 {
608 TCGv_i32 t0 = tcg_temp_new_i32();
609 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
610 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
611 tcg_temp_free_i32(t0);
612 }
613
614 #if !defined(CONFIG_USER_ONLY)
615 /* Callback used to write the exception vector base */
616 static void spr_write_excp_prefix(DisasContext *ctx, int sprn, int gprn)
617 {
618 TCGv t0 = tcg_temp_new();
619 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
620 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
621 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
622 gen_store_spr(sprn, t0);
623 tcg_temp_free(t0);
624 }
625
626 static void spr_write_excp_vector(DisasContext *ctx, int sprn, int gprn)
627 {
628 int sprn_offs;
629
630 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
631 sprn_offs = sprn - SPR_BOOKE_IVOR0;
632 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
633 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
634 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
635 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
636 } else {
637 printf("Trying to write an unknown exception vector %d %03x\n",
638 sprn, sprn);
639 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
640 return;
641 }
642
643 TCGv t0 = tcg_temp_new();
644 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
645 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
646 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
647 gen_store_spr(sprn, t0);
648 tcg_temp_free(t0);
649 }
650 #endif
651
652 static inline void vscr_init(CPUPPCState *env, uint32_t val)
653 {
654 /* Altivec always uses round-to-nearest */
655 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
656 helper_mtvscr(env, val);
657 }
658
659 #ifdef CONFIG_USER_ONLY
660 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
661 oea_read, oea_write, one_reg_id, initial_value) \
662 _spr_register(env, num, name, uea_read, uea_write, initial_value)
663 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
664 oea_read, oea_write, hea_read, hea_write, \
665 one_reg_id, initial_value) \
666 _spr_register(env, num, name, uea_read, uea_write, initial_value)
667 #else
668 #if !defined(CONFIG_KVM)
669 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
670 oea_read, oea_write, one_reg_id, initial_value) \
671 _spr_register(env, num, name, uea_read, uea_write, \
672 oea_read, oea_write, oea_read, oea_write, initial_value)
673 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
674 oea_read, oea_write, hea_read, hea_write, \
675 one_reg_id, initial_value) \
676 _spr_register(env, num, name, uea_read, uea_write, \
677 oea_read, oea_write, hea_read, hea_write, initial_value)
678 #else
679 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
680 oea_read, oea_write, one_reg_id, initial_value) \
681 _spr_register(env, num, name, uea_read, uea_write, \
682 oea_read, oea_write, oea_read, oea_write, \
683 one_reg_id, initial_value)
684 #define spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
685 oea_read, oea_write, hea_read, hea_write, \
686 one_reg_id, initial_value) \
687 _spr_register(env, num, name, uea_read, uea_write, \
688 oea_read, oea_write, hea_read, hea_write, \
689 one_reg_id, initial_value)
690 #endif
691 #endif
692
693 #define spr_register(env, num, name, uea_read, uea_write, \
694 oea_read, oea_write, initial_value) \
695 spr_register_kvm(env, num, name, uea_read, uea_write, \
696 oea_read, oea_write, 0, initial_value)
697
698 #define spr_register_hv(env, num, name, uea_read, uea_write, \
699 oea_read, oea_write, hea_read, hea_write, \
700 initial_value) \
701 spr_register_kvm_hv(env, num, name, uea_read, uea_write, \
702 oea_read, oea_write, hea_read, hea_write, \
703 0, initial_value)
704
705 static inline void _spr_register(CPUPPCState *env, int num,
706 const char *name,
707 void (*uea_read)(DisasContext *ctx,
708 int gprn, int sprn),
709 void (*uea_write)(DisasContext *ctx,
710 int sprn, int gprn),
711 #if !defined(CONFIG_USER_ONLY)
712
713 void (*oea_read)(DisasContext *ctx,
714 int gprn, int sprn),
715 void (*oea_write)(DisasContext *ctx,
716 int sprn, int gprn),
717 void (*hea_read)(DisasContext *opaque,
718 int gprn, int sprn),
719 void (*hea_write)(DisasContext *opaque,
720 int sprn, int gprn),
721 #endif
722 #if defined(CONFIG_KVM)
723 uint64_t one_reg_id,
724 #endif
725 target_ulong initial_value)
726 {
727 ppc_spr_t *spr;
728
729 spr = &env->spr_cb[num];
730 if (spr->name != NULL || env->spr[num] != 0x00000000 ||
731 #if !defined(CONFIG_USER_ONLY)
732 spr->oea_read != NULL || spr->oea_write != NULL ||
733 #endif
734 spr->uea_read != NULL || spr->uea_write != NULL) {
735 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
736 exit(1);
737 }
738 #if defined(PPC_DEBUG_SPR)
739 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
740 name, initial_value);
741 #endif
742 spr->name = name;
743 spr->uea_read = uea_read;
744 spr->uea_write = uea_write;
745 #if !defined(CONFIG_USER_ONLY)
746 spr->oea_read = oea_read;
747 spr->oea_write = oea_write;
748 spr->hea_read = hea_read;
749 spr->hea_write = hea_write;
750 #endif
751 #if defined(CONFIG_KVM)
752 spr->one_reg_id = one_reg_id,
753 #endif
754 env->spr[num] = spr->default_value = initial_value;
755 }
756
757 /* Generic PowerPC SPRs */
758 static void gen_spr_generic(CPUPPCState *env)
759 {
760 /* Integer processing */
761 spr_register(env, SPR_XER, "XER",
762 &spr_read_xer, &spr_write_xer,
763 &spr_read_xer, &spr_write_xer,
764 0x00000000);
765 /* Branch contol */
766 spr_register(env, SPR_LR, "LR",
767 &spr_read_lr, &spr_write_lr,
768 &spr_read_lr, &spr_write_lr,
769 0x00000000);
770 spr_register(env, SPR_CTR, "CTR",
771 &spr_read_ctr, &spr_write_ctr,
772 &spr_read_ctr, &spr_write_ctr,
773 0x00000000);
774 /* Interrupt processing */
775 spr_register(env, SPR_SRR0, "SRR0",
776 SPR_NOACCESS, SPR_NOACCESS,
777 &spr_read_generic, &spr_write_generic,
778 0x00000000);
779 spr_register(env, SPR_SRR1, "SRR1",
780 SPR_NOACCESS, SPR_NOACCESS,
781 &spr_read_generic, &spr_write_generic,
782 0x00000000);
783 /* Processor control */
784 spr_register(env, SPR_SPRG0, "SPRG0",
785 SPR_NOACCESS, SPR_NOACCESS,
786 &spr_read_generic, &spr_write_generic,
787 0x00000000);
788 spr_register(env, SPR_SPRG1, "SPRG1",
789 SPR_NOACCESS, SPR_NOACCESS,
790 &spr_read_generic, &spr_write_generic,
791 0x00000000);
792 spr_register(env, SPR_SPRG2, "SPRG2",
793 SPR_NOACCESS, SPR_NOACCESS,
794 &spr_read_generic, &spr_write_generic,
795 0x00000000);
796 spr_register(env, SPR_SPRG3, "SPRG3",
797 SPR_NOACCESS, SPR_NOACCESS,
798 &spr_read_generic, &spr_write_generic,
799 0x00000000);
800 }
801
802 /* SPR common to all non-embedded PowerPC, including 601 */
803 static void gen_spr_ne_601(CPUPPCState *env)
804 {
805 /* Exception processing */
806 spr_register_kvm(env, SPR_DSISR, "DSISR",
807 SPR_NOACCESS, SPR_NOACCESS,
808 &spr_read_generic, &spr_write_generic,
809 KVM_REG_PPC_DSISR, 0x00000000);
810 spr_register_kvm(env, SPR_DAR, "DAR",
811 SPR_NOACCESS, SPR_NOACCESS,
812 &spr_read_generic, &spr_write_generic,
813 KVM_REG_PPC_DAR, 0x00000000);
814 /* Timer */
815 spr_register(env, SPR_DECR, "DECR",
816 SPR_NOACCESS, SPR_NOACCESS,
817 &spr_read_decr, &spr_write_decr,
818 0x00000000);
819 }
820
821 /* Storage Description Register 1 */
822 static void gen_spr_sdr1(CPUPPCState *env)
823 {
824 #ifndef CONFIG_USER_ONLY
825 if (env->has_hv_mode) {
826 /*
827 * SDR1 is a hypervisor resource on CPUs which have a
828 * hypervisor mode
829 */
830 spr_register_hv(env, SPR_SDR1, "SDR1",
831 SPR_NOACCESS, SPR_NOACCESS,
832 SPR_NOACCESS, SPR_NOACCESS,
833 &spr_read_generic, &spr_write_sdr1,
834 0x00000000);
835 } else {
836 spr_register(env, SPR_SDR1, "SDR1",
837 SPR_NOACCESS, SPR_NOACCESS,
838 &spr_read_generic, &spr_write_sdr1,
839 0x00000000);
840 }
841 #endif
842 }
843
844 /* BATs 0-3 */
845 static void gen_low_BATs(CPUPPCState *env)
846 {
847 #if !defined(CONFIG_USER_ONLY)
848 spr_register(env, SPR_IBAT0U, "IBAT0U",
849 SPR_NOACCESS, SPR_NOACCESS,
850 &spr_read_ibat, &spr_write_ibatu,
851 0x00000000);
852 spr_register(env, SPR_IBAT0L, "IBAT0L",
853 SPR_NOACCESS, SPR_NOACCESS,
854 &spr_read_ibat, &spr_write_ibatl,
855 0x00000000);
856 spr_register(env, SPR_IBAT1U, "IBAT1U",
857 SPR_NOACCESS, SPR_NOACCESS,
858 &spr_read_ibat, &spr_write_ibatu,
859 0x00000000);
860 spr_register(env, SPR_IBAT1L, "IBAT1L",
861 SPR_NOACCESS, SPR_NOACCESS,
862 &spr_read_ibat, &spr_write_ibatl,
863 0x00000000);
864 spr_register(env, SPR_IBAT2U, "IBAT2U",
865 SPR_NOACCESS, SPR_NOACCESS,
866 &spr_read_ibat, &spr_write_ibatu,
867 0x00000000);
868 spr_register(env, SPR_IBAT2L, "IBAT2L",
869 SPR_NOACCESS, SPR_NOACCESS,
870 &spr_read_ibat, &spr_write_ibatl,
871 0x00000000);
872 spr_register(env, SPR_IBAT3U, "IBAT3U",
873 SPR_NOACCESS, SPR_NOACCESS,
874 &spr_read_ibat, &spr_write_ibatu,
875 0x00000000);
876 spr_register(env, SPR_IBAT3L, "IBAT3L",
877 SPR_NOACCESS, SPR_NOACCESS,
878 &spr_read_ibat, &spr_write_ibatl,
879 0x00000000);
880 spr_register(env, SPR_DBAT0U, "DBAT0U",
881 SPR_NOACCESS, SPR_NOACCESS,
882 &spr_read_dbat, &spr_write_dbatu,
883 0x00000000);
884 spr_register(env, SPR_DBAT0L, "DBAT0L",
885 SPR_NOACCESS, SPR_NOACCESS,
886 &spr_read_dbat, &spr_write_dbatl,
887 0x00000000);
888 spr_register(env, SPR_DBAT1U, "DBAT1U",
889 SPR_NOACCESS, SPR_NOACCESS,
890 &spr_read_dbat, &spr_write_dbatu,
891 0x00000000);
892 spr_register(env, SPR_DBAT1L, "DBAT1L",
893 SPR_NOACCESS, SPR_NOACCESS,
894 &spr_read_dbat, &spr_write_dbatl,
895 0x00000000);
896 spr_register(env, SPR_DBAT2U, "DBAT2U",
897 SPR_NOACCESS, SPR_NOACCESS,
898 &spr_read_dbat, &spr_write_dbatu,
899 0x00000000);
900 spr_register(env, SPR_DBAT2L, "DBAT2L",
901 SPR_NOACCESS, SPR_NOACCESS,
902 &spr_read_dbat, &spr_write_dbatl,
903 0x00000000);
904 spr_register(env, SPR_DBAT3U, "DBAT3U",
905 SPR_NOACCESS, SPR_NOACCESS,
906 &spr_read_dbat, &spr_write_dbatu,
907 0x00000000);
908 spr_register(env, SPR_DBAT3L, "DBAT3L",
909 SPR_NOACCESS, SPR_NOACCESS,
910 &spr_read_dbat, &spr_write_dbatl,
911 0x00000000);
912 env->nb_BATs += 4;
913 #endif
914 }
915
916 /* BATs 4-7 */
917 static void gen_high_BATs(CPUPPCState *env)
918 {
919 #if !defined(CONFIG_USER_ONLY)
920 spr_register(env, SPR_IBAT4U, "IBAT4U",
921 SPR_NOACCESS, SPR_NOACCESS,
922 &spr_read_ibat_h, &spr_write_ibatu_h,
923 0x00000000);
924 spr_register(env, SPR_IBAT4L, "IBAT4L",
925 SPR_NOACCESS, SPR_NOACCESS,
926 &spr_read_ibat_h, &spr_write_ibatl_h,
927 0x00000000);
928 spr_register(env, SPR_IBAT5U, "IBAT5U",
929 SPR_NOACCESS, SPR_NOACCESS,
930 &spr_read_ibat_h, &spr_write_ibatu_h,
931 0x00000000);
932 spr_register(env, SPR_IBAT5L, "IBAT5L",
933 SPR_NOACCESS, SPR_NOACCESS,
934 &spr_read_ibat_h, &spr_write_ibatl_h,
935 0x00000000);
936 spr_register(env, SPR_IBAT6U, "IBAT6U",
937 SPR_NOACCESS, SPR_NOACCESS,
938 &spr_read_ibat_h, &spr_write_ibatu_h,
939 0x00000000);
940 spr_register(env, SPR_IBAT6L, "IBAT6L",
941 SPR_NOACCESS, SPR_NOACCESS,
942 &spr_read_ibat_h, &spr_write_ibatl_h,
943 0x00000000);
944 spr_register(env, SPR_IBAT7U, "IBAT7U",
945 SPR_NOACCESS, SPR_NOACCESS,
946 &spr_read_ibat_h, &spr_write_ibatu_h,
947 0x00000000);
948 spr_register(env, SPR_IBAT7L, "IBAT7L",
949 SPR_NOACCESS, SPR_NOACCESS,
950 &spr_read_ibat_h, &spr_write_ibatl_h,
951 0x00000000);
952 spr_register(env, SPR_DBAT4U, "DBAT4U",
953 SPR_NOACCESS, SPR_NOACCESS,
954 &spr_read_dbat_h, &spr_write_dbatu_h,
955 0x00000000);
956 spr_register(env, SPR_DBAT4L, "DBAT4L",
957 SPR_NOACCESS, SPR_NOACCESS,
958 &spr_read_dbat_h, &spr_write_dbatl_h,
959 0x00000000);
960 spr_register(env, SPR_DBAT5U, "DBAT5U",
961 SPR_NOACCESS, SPR_NOACCESS,
962 &spr_read_dbat_h, &spr_write_dbatu_h,
963 0x00000000);
964 spr_register(env, SPR_DBAT5L, "DBAT5L",
965 SPR_NOACCESS, SPR_NOACCESS,
966 &spr_read_dbat_h, &spr_write_dbatl_h,
967 0x00000000);
968 spr_register(env, SPR_DBAT6U, "DBAT6U",
969 SPR_NOACCESS, SPR_NOACCESS,
970 &spr_read_dbat_h, &spr_write_dbatu_h,
971 0x00000000);
972 spr_register(env, SPR_DBAT6L, "DBAT6L",
973 SPR_NOACCESS, SPR_NOACCESS,
974 &spr_read_dbat_h, &spr_write_dbatl_h,
975 0x00000000);
976 spr_register(env, SPR_DBAT7U, "DBAT7U",
977 SPR_NOACCESS, SPR_NOACCESS,
978 &spr_read_dbat_h, &spr_write_dbatu_h,
979 0x00000000);
980 spr_register(env, SPR_DBAT7L, "DBAT7L",
981 SPR_NOACCESS, SPR_NOACCESS,
982 &spr_read_dbat_h, &spr_write_dbatl_h,
983 0x00000000);
984 env->nb_BATs += 4;
985 #endif
986 }
987
988 /* Generic PowerPC time base */
989 static void gen_tbl(CPUPPCState *env)
990 {
991 spr_register(env, SPR_VTBL, "TBL",
992 &spr_read_tbl, SPR_NOACCESS,
993 &spr_read_tbl, SPR_NOACCESS,
994 0x00000000);
995 spr_register(env, SPR_TBL, "TBL",
996 &spr_read_tbl, SPR_NOACCESS,
997 &spr_read_tbl, &spr_write_tbl,
998 0x00000000);
999 spr_register(env, SPR_VTBU, "TBU",
1000 &spr_read_tbu, SPR_NOACCESS,
1001 &spr_read_tbu, SPR_NOACCESS,
1002 0x00000000);
1003 spr_register(env, SPR_TBU, "TBU",
1004 &spr_read_tbu, SPR_NOACCESS,
1005 &spr_read_tbu, &spr_write_tbu,
1006 0x00000000);
1007 }
1008
1009 /* Softare table search registers */
1010 static void gen_6xx_7xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
1011 {
1012 #if !defined(CONFIG_USER_ONLY)
1013 env->nb_tlb = nb_tlbs;
1014 env->nb_ways = nb_ways;
1015 env->id_tlbs = 1;
1016 env->tlb_type = TLB_6XX;
1017 spr_register(env, SPR_DMISS, "DMISS",
1018 SPR_NOACCESS, SPR_NOACCESS,
1019 &spr_read_generic, SPR_NOACCESS,
1020 0x00000000);
1021 spr_register(env, SPR_DCMP, "DCMP",
1022 SPR_NOACCESS, SPR_NOACCESS,
1023 &spr_read_generic, SPR_NOACCESS,
1024 0x00000000);
1025 spr_register(env, SPR_HASH1, "HASH1",
1026 SPR_NOACCESS, SPR_NOACCESS,
1027 &spr_read_generic, SPR_NOACCESS,
1028 0x00000000);
1029 spr_register(env, SPR_HASH2, "HASH2",
1030 SPR_NOACCESS, SPR_NOACCESS,
1031 &spr_read_generic, SPR_NOACCESS,
1032 0x00000000);
1033 spr_register(env, SPR_IMISS, "IMISS",
1034 SPR_NOACCESS, SPR_NOACCESS,
1035 &spr_read_generic, SPR_NOACCESS,
1036 0x00000000);
1037 spr_register(env, SPR_ICMP, "ICMP",
1038 SPR_NOACCESS, SPR_NOACCESS,
1039 &spr_read_generic, SPR_NOACCESS,
1040 0x00000000);
1041 spr_register(env, SPR_RPA, "RPA",
1042 SPR_NOACCESS, SPR_NOACCESS,
1043 &spr_read_generic, &spr_write_generic,
1044 0x00000000);
1045 #endif
1046 }
1047
1048 /* SPR common to MPC755 and G2 */
1049 static void gen_spr_G2_755(CPUPPCState *env)
1050 {
1051 /* SGPRs */
1052 spr_register(env, SPR_SPRG4, "SPRG4",
1053 SPR_NOACCESS, SPR_NOACCESS,
1054 &spr_read_generic, &spr_write_generic,
1055 0x00000000);
1056 spr_register(env, SPR_SPRG5, "SPRG5",
1057 SPR_NOACCESS, SPR_NOACCESS,
1058 &spr_read_generic, &spr_write_generic,
1059 0x00000000);
1060 spr_register(env, SPR_SPRG6, "SPRG6",
1061 SPR_NOACCESS, SPR_NOACCESS,
1062 &spr_read_generic, &spr_write_generic,
1063 0x00000000);
1064 spr_register(env, SPR_SPRG7, "SPRG7",
1065 SPR_NOACCESS, SPR_NOACCESS,
1066 &spr_read_generic, &spr_write_generic,
1067 0x00000000);
1068 }
1069
1070 /* SPR common to all 7xx PowerPC implementations */
1071 static void gen_spr_7xx(CPUPPCState *env)
1072 {
1073 /* Breakpoints */
1074 /* XXX : not implemented */
1075 spr_register_kvm(env, SPR_DABR, "DABR",
1076 SPR_NOACCESS, SPR_NOACCESS,
1077 &spr_read_generic, &spr_write_generic,
1078 KVM_REG_PPC_DABR, 0x00000000);
1079 /* XXX : not implemented */
1080 spr_register(env, SPR_IABR, "IABR",
1081 SPR_NOACCESS, SPR_NOACCESS,
1082 &spr_read_generic, &spr_write_generic,
1083 0x00000000);
1084 /* Cache management */
1085 /* XXX : not implemented */
1086 spr_register(env, SPR_ICTC, "ICTC",
1087 SPR_NOACCESS, SPR_NOACCESS,
1088 &spr_read_generic, &spr_write_generic,
1089 0x00000000);
1090 /* Performance monitors */
1091 /* XXX : not implemented */
1092 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
1093 SPR_NOACCESS, SPR_NOACCESS,
1094 &spr_read_generic, &spr_write_generic,
1095 0x00000000);
1096 /* XXX : not implemented */
1097 spr_register(env, SPR_7XX_MMCR1, "MMCR1",
1098 SPR_NOACCESS, SPR_NOACCESS,
1099 &spr_read_generic, &spr_write_generic,
1100 0x00000000);
1101 /* XXX : not implemented */
1102 spr_register(env, SPR_7XX_PMC1, "PMC1",
1103 SPR_NOACCESS, SPR_NOACCESS,
1104 &spr_read_generic, &spr_write_generic,
1105 0x00000000);
1106 /* XXX : not implemented */
1107 spr_register(env, SPR_7XX_PMC2, "PMC2",
1108 SPR_NOACCESS, SPR_NOACCESS,
1109 &spr_read_generic, &spr_write_generic,
1110 0x00000000);
1111 /* XXX : not implemented */
1112 spr_register(env, SPR_7XX_PMC3, "PMC3",
1113 SPR_NOACCESS, SPR_NOACCESS,
1114 &spr_read_generic, &spr_write_generic,
1115 0x00000000);
1116 /* XXX : not implemented */
1117 spr_register(env, SPR_7XX_PMC4, "PMC4",
1118 SPR_NOACCESS, SPR_NOACCESS,
1119 &spr_read_generic, &spr_write_generic,
1120 0x00000000);
1121 /* XXX : not implemented */
1122 spr_register(env, SPR_7XX_SIAR, "SIAR",
1123 SPR_NOACCESS, SPR_NOACCESS,
1124 &spr_read_generic, SPR_NOACCESS,
1125 0x00000000);
1126 /* XXX : not implemented */
1127 spr_register(env, SPR_7XX_UMMCR0, "UMMCR0",
1128 &spr_read_ureg, SPR_NOACCESS,
1129 &spr_read_ureg, SPR_NOACCESS,
1130 0x00000000);
1131 /* XXX : not implemented */
1132 spr_register(env, SPR_7XX_UMMCR1, "UMMCR1",
1133 &spr_read_ureg, SPR_NOACCESS,
1134 &spr_read_ureg, SPR_NOACCESS,
1135 0x00000000);
1136 /* XXX : not implemented */
1137 spr_register(env, SPR_7XX_UPMC1, "UPMC1",
1138 &spr_read_ureg, SPR_NOACCESS,
1139 &spr_read_ureg, SPR_NOACCESS,
1140 0x00000000);
1141 /* XXX : not implemented */
1142 spr_register(env, SPR_7XX_UPMC2, "UPMC2",
1143 &spr_read_ureg, SPR_NOACCESS,
1144 &spr_read_ureg, SPR_NOACCESS,
1145 0x00000000);
1146 /* XXX : not implemented */
1147 spr_register(env, SPR_7XX_UPMC3, "UPMC3",
1148 &spr_read_ureg, SPR_NOACCESS,
1149 &spr_read_ureg, SPR_NOACCESS,
1150 0x00000000);
1151 /* XXX : not implemented */
1152 spr_register(env, SPR_7XX_UPMC4, "UPMC4",
1153 &spr_read_ureg, SPR_NOACCESS,
1154 &spr_read_ureg, SPR_NOACCESS,
1155 0x00000000);
1156 /* XXX : not implemented */
1157 spr_register(env, SPR_7XX_USIAR, "USIAR",
1158 &spr_read_ureg, SPR_NOACCESS,
1159 &spr_read_ureg, SPR_NOACCESS,
1160 0x00000000);
1161 /* External access control */
1162 /* XXX : not implemented */
1163 spr_register(env, SPR_EAR, "EAR",
1164 SPR_NOACCESS, SPR_NOACCESS,
1165 &spr_read_generic, &spr_write_generic,
1166 0x00000000);
1167 }
1168
1169 #ifdef TARGET_PPC64
1170 #ifndef CONFIG_USER_ONLY
1171 static void spr_write_amr(DisasContext *ctx, int sprn, int gprn)
1172 {
1173 TCGv t0 = tcg_temp_new();
1174 TCGv t1 = tcg_temp_new();
1175 TCGv t2 = tcg_temp_new();
1176
1177 /*
1178 * Note, the HV=1 PR=0 case is handled earlier by simply using
1179 * spr_write_generic for HV mode in the SPR table
1180 */
1181
1182 /* Build insertion mask into t1 based on context */
1183 if (ctx->pr) {
1184 gen_load_spr(t1, SPR_UAMOR);
1185 } else {
1186 gen_load_spr(t1, SPR_AMOR);
1187 }
1188
1189 /* Mask new bits into t2 */
1190 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1191
1192 /* Load AMR and clear new bits in t0 */
1193 gen_load_spr(t0, SPR_AMR);
1194 tcg_gen_andc_tl(t0, t0, t1);
1195
1196 /* Or'in new bits and write it out */
1197 tcg_gen_or_tl(t0, t0, t2);
1198 gen_store_spr(SPR_AMR, t0);
1199 spr_store_dump_spr(SPR_AMR);
1200
1201 tcg_temp_free(t0);
1202 tcg_temp_free(t1);
1203 tcg_temp_free(t2);
1204 }
1205
1206 static void spr_write_uamor(DisasContext *ctx, int sprn, int gprn)
1207 {
1208 TCGv t0 = tcg_temp_new();
1209 TCGv t1 = tcg_temp_new();
1210 TCGv t2 = tcg_temp_new();
1211
1212 /*
1213 * Note, the HV=1 case is handled earlier by simply using
1214 * spr_write_generic for HV mode in the SPR table
1215 */
1216
1217 /* Build insertion mask into t1 based on context */
1218 gen_load_spr(t1, SPR_AMOR);
1219
1220 /* Mask new bits into t2 */
1221 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1222
1223 /* Load AMR and clear new bits in t0 */
1224 gen_load_spr(t0, SPR_UAMOR);
1225 tcg_gen_andc_tl(t0, t0, t1);
1226
1227 /* Or'in new bits and write it out */
1228 tcg_gen_or_tl(t0, t0, t2);
1229 gen_store_spr(SPR_UAMOR, t0);
1230 spr_store_dump_spr(SPR_UAMOR);
1231
1232 tcg_temp_free(t0);
1233 tcg_temp_free(t1);
1234 tcg_temp_free(t2);
1235 }
1236
1237 static void spr_write_iamr(DisasContext *ctx, int sprn, int gprn)
1238 {
1239 TCGv t0 = tcg_temp_new();
1240 TCGv t1 = tcg_temp_new();
1241 TCGv t2 = tcg_temp_new();
1242
1243 /*
1244 * Note, the HV=1 case is handled earlier by simply using
1245 * spr_write_generic for HV mode in the SPR table
1246 */
1247
1248 /* Build insertion mask into t1 based on context */
1249 gen_load_spr(t1, SPR_AMOR);
1250
1251 /* Mask new bits into t2 */
1252 tcg_gen_and_tl(t2, t1, cpu_gpr[gprn]);
1253
1254 /* Load AMR and clear new bits in t0 */
1255 gen_load_spr(t0, SPR_IAMR);
1256 tcg_gen_andc_tl(t0, t0, t1);
1257
1258 /* Or'in new bits and write it out */
1259 tcg_gen_or_tl(t0, t0, t2);
1260 gen_store_spr(SPR_IAMR, t0);
1261 spr_store_dump_spr(SPR_IAMR);
1262
1263 tcg_temp_free(t0);
1264 tcg_temp_free(t1);
1265 tcg_temp_free(t2);
1266 }
1267 #endif /* CONFIG_USER_ONLY */
1268
1269 static void gen_spr_amr(CPUPPCState *env)
1270 {
1271 #ifndef CONFIG_USER_ONLY
1272 /*
1273 * Virtual Page Class Key protection
1274 *
1275 * The AMR is accessible either via SPR 13 or SPR 29. 13 is
1276 * userspace accessible, 29 is privileged. So we only need to set
1277 * the kvm ONE_REG id on one of them, we use 29
1278 */
1279 spr_register(env, SPR_UAMR, "UAMR",
1280 &spr_read_generic, &spr_write_amr,
1281 &spr_read_generic, &spr_write_amr,
1282 0);
1283 spr_register_kvm_hv(env, SPR_AMR, "AMR",
1284 SPR_NOACCESS, SPR_NOACCESS,
1285 &spr_read_generic, &spr_write_amr,
1286 &spr_read_generic, &spr_write_generic,
1287 KVM_REG_PPC_AMR, 0);
1288 spr_register_kvm_hv(env, SPR_UAMOR, "UAMOR",
1289 SPR_NOACCESS, SPR_NOACCESS,
1290 &spr_read_generic, &spr_write_uamor,
1291 &spr_read_generic, &spr_write_generic,
1292 KVM_REG_PPC_UAMOR, 0);
1293 spr_register_hv(env, SPR_AMOR, "AMOR",
1294 SPR_NOACCESS, SPR_NOACCESS,
1295 SPR_NOACCESS, SPR_NOACCESS,
1296 &spr_read_generic, &spr_write_generic,
1297 0);
1298 #endif /* !CONFIG_USER_ONLY */
1299 }
1300
1301 static void gen_spr_iamr(CPUPPCState *env)
1302 {
1303 #ifndef CONFIG_USER_ONLY
1304 spr_register_kvm_hv(env, SPR_IAMR, "IAMR",
1305 SPR_NOACCESS, SPR_NOACCESS,
1306 &spr_read_generic, &spr_write_iamr,
1307 &spr_read_generic, &spr_write_generic,
1308 KVM_REG_PPC_IAMR, 0);
1309 #endif /* !CONFIG_USER_ONLY */
1310 }
1311 #endif /* TARGET_PPC64 */
1312
1313 #ifndef CONFIG_USER_ONLY
1314 static void spr_read_thrm(DisasContext *ctx, int gprn, int sprn)
1315 {
1316 gen_helper_fixup_thrm(cpu_env);
1317 gen_load_spr(cpu_gpr[gprn], sprn);
1318 spr_load_dump_spr(sprn);
1319 }
1320 #endif /* !CONFIG_USER_ONLY */
1321
1322 static void gen_spr_thrm(CPUPPCState *env)
1323 {
1324 /* Thermal management */
1325 /* XXX : not implemented */
1326 spr_register(env, SPR_THRM1, "THRM1",
1327 SPR_NOACCESS, SPR_NOACCESS,
1328 &spr_read_thrm, &spr_write_generic,
1329 0x00000000);
1330 /* XXX : not implemented */
1331 spr_register(env, SPR_THRM2, "THRM2",
1332 SPR_NOACCESS, SPR_NOACCESS,
1333 &spr_read_thrm, &spr_write_generic,
1334 0x00000000);
1335 /* XXX : not implemented */
1336 spr_register(env, SPR_THRM3, "THRM3",
1337 SPR_NOACCESS, SPR_NOACCESS,
1338 &spr_read_thrm, &spr_write_generic,
1339 0x00000000);
1340 }
1341
1342 /* SPR specific to PowerPC 604 implementation */
1343 static void gen_spr_604(CPUPPCState *env)
1344 {
1345 /* Processor identification */
1346 spr_register(env, SPR_PIR, "PIR",
1347 SPR_NOACCESS, SPR_NOACCESS,
1348 &spr_read_generic, &spr_write_pir,
1349 0x00000000);
1350 /* Breakpoints */
1351 /* XXX : not implemented */
1352 spr_register(env, SPR_IABR, "IABR",
1353 SPR_NOACCESS, SPR_NOACCESS,
1354 &spr_read_generic, &spr_write_generic,
1355 0x00000000);
1356 /* XXX : not implemented */
1357 spr_register_kvm(env, SPR_DABR, "DABR",
1358 SPR_NOACCESS, SPR_NOACCESS,
1359 &spr_read_generic, &spr_write_generic,
1360 KVM_REG_PPC_DABR, 0x00000000);
1361 /* Performance counters */
1362 /* XXX : not implemented */
1363 spr_register(env, SPR_7XX_MMCR0, "MMCR0",
1364 SPR_NOACCESS, SPR_NOACCESS,
1365 &spr_read_generic, &spr_write_generic,
1366 0x00000000);
1367 /* XXX : not implemented */
1368 spr_register(env, SPR_7XX_PMC1, "PMC1",
1369 SPR_NOACCESS, SPR_NOACCESS,
1370 &spr_read_generic, &spr_write_generic,
1371 0x00000000);
1372 /* XXX : not implemented */
1373 spr_register(env, SPR_7XX_PMC2, "PMC2",
1374 SPR_NOACCESS, SPR_NOACCESS,
1375 &spr_read_generic, &spr_write_generic,
1376 0x00000000);
1377 /* XXX : not implemented */
1378 spr_register(env, SPR_7XX_SIAR, "SIAR",
1379 SPR_NOACCESS, SPR_NOACCESS,
1380 &spr_read_generic, SPR_NOACCESS,
1381 0x00000000);
1382 /* XXX : not implemented */
1383 spr_register(env, SPR_SDA, "SDA",
1384 SPR_NOACCESS, SPR_NOACCESS,
1385 &spr_read_generic, SPR_NOACCESS,
1386 0x00000000);
1387 /* External access control */
1388 /* XXX : not implemented */
1389 spr_register(env, SPR_EAR, "EAR",
1390 SPR_NOACCESS, SPR_NOACCESS,
1391 &spr_read_generic, &spr_write_generic,
1392 0x00000000);
1393 }
1394
1395 /* SPR specific to PowerPC 603 implementation */
1396 static void gen_spr_603(CPUPPCState *env)
1397 {
1398 /* External access control */
1399 /* XXX : not implemented */
1400 spr_register(env, SPR_EAR, "EAR",
1401 SPR_NOACCESS, SPR_NOACCESS,
1402 &spr_read_generic, &spr_write_generic,
1403 0x00000000);
1404 /* Breakpoints */
1405 /* XXX : not implemented */
1406 spr_register(env, SPR_IABR, "IABR",
1407 SPR_NOACCESS, SPR_NOACCESS,
1408 &spr_read_generic, &spr_write_generic,
1409 0x00000000);
1410
1411 }
1412
1413 /* SPR specific to PowerPC G2 implementation */
1414 static void gen_spr_G2(CPUPPCState *env)
1415 {
1416 /* Memory base address */
1417 /* MBAR */
1418 /* XXX : not implemented */
1419 spr_register(env, SPR_MBAR, "MBAR",
1420 SPR_NOACCESS, SPR_NOACCESS,
1421 &spr_read_generic, &spr_write_generic,
1422 0x00000000);
1423 /* Exception processing */
1424 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1425 SPR_NOACCESS, SPR_NOACCESS,
1426 &spr_read_generic, &spr_write_generic,
1427 0x00000000);
1428 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1429 SPR_NOACCESS, SPR_NOACCESS,
1430 &spr_read_generic, &spr_write_generic,
1431 0x00000000);
1432 /* Breakpoints */
1433 /* XXX : not implemented */
1434 spr_register(env, SPR_DABR, "DABR",
1435 SPR_NOACCESS, SPR_NOACCESS,
1436 &spr_read_generic, &spr_write_generic,
1437 0x00000000);
1438 /* XXX : not implemented */
1439 spr_register(env, SPR_DABR2, "DABR2",
1440 SPR_NOACCESS, SPR_NOACCESS,
1441 &spr_read_generic, &spr_write_generic,
1442 0x00000000);
1443 /* XXX : not implemented */
1444 spr_register(env, SPR_IABR, "IABR",
1445 SPR_NOACCESS, SPR_NOACCESS,
1446 &spr_read_generic, &spr_write_generic,
1447 0x00000000);
1448 /* XXX : not implemented */
1449 spr_register(env, SPR_IABR2, "IABR2",
1450 SPR_NOACCESS, SPR_NOACCESS,
1451 &spr_read_generic, &spr_write_generic,
1452 0x00000000);
1453 /* XXX : not implemented */
1454 spr_register(env, SPR_IBCR, "IBCR",
1455 SPR_NOACCESS, SPR_NOACCESS,
1456 &spr_read_generic, &spr_write_generic,
1457 0x00000000);
1458 /* XXX : not implemented */
1459 spr_register(env, SPR_DBCR, "DBCR",
1460 SPR_NOACCESS, SPR_NOACCESS,
1461 &spr_read_generic, &spr_write_generic,
1462 0x00000000);
1463 }
1464
1465 /* SPR specific to PowerPC 602 implementation */
1466 static void gen_spr_602(CPUPPCState *env)
1467 {
1468 /* ESA registers */
1469 /* XXX : not implemented */
1470 spr_register(env, SPR_SER, "SER",
1471 SPR_NOACCESS, SPR_NOACCESS,
1472 &spr_read_generic, &spr_write_generic,
1473 0x00000000);
1474 /* XXX : not implemented */
1475 spr_register(env, SPR_SEBR, "SEBR",
1476 SPR_NOACCESS, SPR_NOACCESS,
1477 &spr_read_generic, &spr_write_generic,
1478 0x00000000);
1479 /* XXX : not implemented */
1480 spr_register(env, SPR_ESASRR, "ESASRR",
1481 SPR_NOACCESS, SPR_NOACCESS,
1482 &spr_read_generic, &spr_write_generic,
1483 0x00000000);
1484 /* Floating point status */
1485 /* XXX : not implemented */
1486 spr_register(env, SPR_SP, "SP",
1487 SPR_NOACCESS, SPR_NOACCESS,
1488 &spr_read_generic, &spr_write_generic,
1489 0x00000000);
1490 /* XXX : not implemented */
1491 spr_register(env, SPR_LT, "LT",
1492 SPR_NOACCESS, SPR_NOACCESS,
1493 &spr_read_generic, &spr_write_generic,
1494 0x00000000);
1495 /* Watchdog timer */
1496 /* XXX : not implemented */
1497 spr_register(env, SPR_TCR, "TCR",
1498 SPR_NOACCESS, SPR_NOACCESS,
1499 &spr_read_generic, &spr_write_generic,
1500 0x00000000);
1501 /* Interrupt base */
1502 spr_register(env, SPR_IBR, "IBR",
1503 SPR_NOACCESS, SPR_NOACCESS,
1504 &spr_read_generic, &spr_write_generic,
1505 0x00000000);
1506 /* XXX : not implemented */
1507 spr_register(env, SPR_IABR, "IABR",
1508 SPR_NOACCESS, SPR_NOACCESS,
1509 &spr_read_generic, &spr_write_generic,
1510 0x00000000);
1511 }
1512
1513 /* SPR specific to PowerPC 601 implementation */
1514 static void gen_spr_601(CPUPPCState *env)
1515 {
1516 /* Multiplication/division register */
1517 /* MQ */
1518 spr_register(env, SPR_MQ, "MQ",
1519 &spr_read_generic, &spr_write_generic,
1520 &spr_read_generic, &spr_write_generic,
1521 0x00000000);
1522 /* RTC registers */
1523 spr_register(env, SPR_601_RTCU, "RTCU",
1524 SPR_NOACCESS, SPR_NOACCESS,
1525 SPR_NOACCESS, &spr_write_601_rtcu,
1526 0x00000000);
1527 spr_register(env, SPR_601_VRTCU, "RTCU",
1528 &spr_read_601_rtcu, SPR_NOACCESS,
1529 &spr_read_601_rtcu, SPR_NOACCESS,
1530 0x00000000);
1531 spr_register(env, SPR_601_RTCL, "RTCL",
1532 SPR_NOACCESS, SPR_NOACCESS,
1533 SPR_NOACCESS, &spr_write_601_rtcl,
1534 0x00000000);
1535 spr_register(env, SPR_601_VRTCL, "RTCL",
1536 &spr_read_601_rtcl, SPR_NOACCESS,
1537 &spr_read_601_rtcl, SPR_NOACCESS,
1538 0x00000000);
1539 /* Timer */
1540 #if 0 /* ? */
1541 spr_register(env, SPR_601_UDECR, "UDECR",
1542 &spr_read_decr, SPR_NOACCESS,
1543 &spr_read_decr, SPR_NOACCESS,
1544 0x00000000);
1545 #endif
1546 /* External access control */
1547 /* XXX : not implemented */
1548 spr_register(env, SPR_EAR, "EAR",
1549 SPR_NOACCESS, SPR_NOACCESS,
1550 &spr_read_generic, &spr_write_generic,
1551 0x00000000);
1552 /* Memory management */
1553 #if !defined(CONFIG_USER_ONLY)
1554 spr_register(env, SPR_IBAT0U, "IBAT0U",
1555 SPR_NOACCESS, SPR_NOACCESS,
1556 &spr_read_601_ubat, &spr_write_601_ubatu,
1557 0x00000000);
1558 spr_register(env, SPR_IBAT0L, "IBAT0L",
1559 SPR_NOACCESS, SPR_NOACCESS,
1560 &spr_read_601_ubat, &spr_write_601_ubatl,
1561 0x00000000);
1562 spr_register(env, SPR_IBAT1U, "IBAT1U",
1563 SPR_NOACCESS, SPR_NOACCESS,
1564 &spr_read_601_ubat, &spr_write_601_ubatu,
1565 0x00000000);
1566 spr_register(env, SPR_IBAT1L, "IBAT1L",
1567 SPR_NOACCESS, SPR_NOACCESS,
1568 &spr_read_601_ubat, &spr_write_601_ubatl,
1569 0x00000000);
1570 spr_register(env, SPR_IBAT2U, "IBAT2U",
1571 SPR_NOACCESS, SPR_NOACCESS,
1572 &spr_read_601_ubat, &spr_write_601_ubatu,
1573 0x00000000);
1574 spr_register(env, SPR_IBAT2L, "IBAT2L",
1575 SPR_NOACCESS, SPR_NOACCESS,
1576 &spr_read_601_ubat, &spr_write_601_ubatl,
1577 0x00000000);
1578 spr_register(env, SPR_IBAT3U, "IBAT3U",
1579 SPR_NOACCESS, SPR_NOACCESS,
1580 &spr_read_601_ubat, &spr_write_601_ubatu,
1581 0x00000000);
1582 spr_register(env, SPR_IBAT3L, "IBAT3L",
1583 SPR_NOACCESS, SPR_NOACCESS,
1584 &spr_read_601_ubat, &spr_write_601_ubatl,
1585 0x00000000);
1586 env->nb_BATs = 4;
1587 #endif
1588 }
1589
1590 static void gen_spr_74xx(CPUPPCState *env)
1591 {
1592 /* Processor identification */
1593 spr_register(env, SPR_PIR, "PIR",
1594 SPR_NOACCESS, SPR_NOACCESS,
1595 &spr_read_generic, &spr_write_pir,
1596 0x00000000);
1597 /* XXX : not implemented */
1598 spr_register(env, SPR_74XX_MMCR2, "MMCR2",
1599 SPR_NOACCESS, SPR_NOACCESS,
1600 &spr_read_generic, &spr_write_generic,
1601 0x00000000);
1602 /* XXX : not implemented */
1603 spr_register(env, SPR_74XX_UMMCR2, "UMMCR2",
1604 &spr_read_ureg, SPR_NOACCESS,
1605 &spr_read_ureg, SPR_NOACCESS,
1606 0x00000000);
1607 /* XXX: not implemented */
1608 spr_register(env, SPR_BAMR, "BAMR",
1609 SPR_NOACCESS, SPR_NOACCESS,
1610 &spr_read_generic, &spr_write_generic,
1611 0x00000000);
1612 /* XXX : not implemented */
1613 spr_register(env, SPR_MSSCR0, "MSSCR0",
1614 SPR_NOACCESS, SPR_NOACCESS,
1615 &spr_read_generic, &spr_write_generic,
1616 0x00000000);
1617 /* Hardware implementation registers */
1618 /* XXX : not implemented */
1619 spr_register(env, SPR_HID0, "HID0",
1620 SPR_NOACCESS, SPR_NOACCESS,
1621 &spr_read_generic, &spr_write_generic,
1622 0x00000000);
1623 /* XXX : not implemented */
1624 spr_register(env, SPR_HID1, "HID1",
1625 SPR_NOACCESS, SPR_NOACCESS,
1626 &spr_read_generic, &spr_write_generic,
1627 0x00000000);
1628 /* Altivec */
1629 spr_register(env, SPR_VRSAVE, "VRSAVE",
1630 &spr_read_generic, &spr_write_generic,
1631 &spr_read_generic, &spr_write_generic,
1632 0x00000000);
1633 /* XXX : not implemented */
1634 spr_register(env, SPR_L2CR, "L2CR",
1635 SPR_NOACCESS, SPR_NOACCESS,
1636 &spr_read_generic, spr_access_nop,
1637 0x00000000);
1638 /* Not strictly an SPR */
1639 vscr_init(env, 0x00010000);
1640 }
1641
1642 static void gen_l3_ctrl(CPUPPCState *env)
1643 {
1644 /* L3CR */
1645 /* XXX : not implemented */
1646 spr_register(env, SPR_L3CR, "L3CR",
1647 SPR_NOACCESS, SPR_NOACCESS,
1648 &spr_read_generic, &spr_write_generic,
1649 0x00000000);
1650 /* L3ITCR0 */
1651 /* XXX : not implemented */
1652 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1653 SPR_NOACCESS, SPR_NOACCESS,
1654 &spr_read_generic, &spr_write_generic,
1655 0x00000000);
1656 /* L3PM */
1657 /* XXX : not implemented */
1658 spr_register(env, SPR_L3PM, "L3PM",
1659 SPR_NOACCESS, SPR_NOACCESS,
1660 &spr_read_generic, &spr_write_generic,
1661 0x00000000);
1662 }
1663
1664 static void gen_74xx_soft_tlb(CPUPPCState *env, int nb_tlbs, int nb_ways)
1665 {
1666 #if !defined(CONFIG_USER_ONLY)
1667 env->nb_tlb = nb_tlbs;
1668 env->nb_ways = nb_ways;
1669 env->id_tlbs = 1;
1670 env->tlb_type = TLB_6XX;
1671 /* XXX : not implemented */
1672 spr_register(env, SPR_PTEHI, "PTEHI",
1673 SPR_NOACCESS, SPR_NOACCESS,
1674 &spr_read_generic, &spr_write_generic,
1675 0x00000000);
1676 /* XXX : not implemented */
1677 spr_register(env, SPR_PTELO, "PTELO",
1678 SPR_NOACCESS, SPR_NOACCESS,
1679 &spr_read_generic, &spr_write_generic,
1680 0x00000000);
1681 /* XXX : not implemented */
1682 spr_register(env, SPR_TLBMISS, "TLBMISS",
1683 SPR_NOACCESS, SPR_NOACCESS,
1684 &spr_read_generic, &spr_write_generic,
1685 0x00000000);
1686 #endif
1687 }
1688
1689 #if !defined(CONFIG_USER_ONLY)
1690 static void spr_write_e500_l1csr0(DisasContext *ctx, int sprn, int gprn)
1691 {
1692 TCGv t0 = tcg_temp_new();
1693
1694 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
1695 gen_store_spr(sprn, t0);
1696 tcg_temp_free(t0);
1697 }
1698
1699 static void spr_write_e500_l1csr1(DisasContext *ctx, int sprn, int gprn)
1700 {
1701 TCGv t0 = tcg_temp_new();
1702
1703 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
1704 gen_store_spr(sprn, t0);
1705 tcg_temp_free(t0);
1706 }
1707
1708 static void spr_write_booke206_mmucsr0(DisasContext *ctx, int sprn, int gprn)
1709 {
1710 gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
1711 }
1712
1713 static void spr_write_booke_pid(DisasContext *ctx, int sprn, int gprn)
1714 {
1715 TCGv_i32 t0 = tcg_const_i32(sprn);
1716 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1717 tcg_temp_free_i32(t0);
1718 }
1719 static void spr_write_eplc(DisasContext *ctx, int sprn, int gprn)
1720 {
1721 gen_helper_booke_set_eplc(cpu_env, cpu_gpr[gprn]);
1722 }
1723 static void spr_write_epsc(DisasContext *ctx, int sprn, int gprn)
1724 {
1725 gen_helper_booke_set_epsc(cpu_env, cpu_gpr[gprn]);
1726 }
1727
1728 #endif
1729
1730 static void gen_spr_usprg3(CPUPPCState *env)
1731 {
1732 spr_register(env, SPR_USPRG3, "USPRG3",
1733 &spr_read_ureg, SPR_NOACCESS,
1734 &spr_read_ureg, SPR_NOACCESS,
1735 0x00000000);
1736 }
1737
1738 static void gen_spr_usprgh(CPUPPCState *env)
1739 {
1740 spr_register(env, SPR_USPRG4, "USPRG4",
1741 &spr_read_ureg, SPR_NOACCESS,
1742 &spr_read_ureg, SPR_NOACCESS,
1743 0x00000000);
1744 spr_register(env, SPR_USPRG5, "USPRG5",
1745 &spr_read_ureg, SPR_NOACCESS,
1746 &spr_read_ureg, SPR_NOACCESS,
1747 0x00000000);
1748 spr_register(env, SPR_USPRG6, "USPRG6",
1749 &spr_read_ureg, SPR_NOACCESS,
1750 &spr_read_ureg, SPR_NOACCESS,
1751 0x00000000);
1752 spr_register(env, SPR_USPRG7, "USPRG7",
1753 &spr_read_ureg, SPR_NOACCESS,
1754 &spr_read_ureg, SPR_NOACCESS,
1755 0x00000000);
1756 }
1757
1758 /* PowerPC BookE SPR */
1759 static void gen_spr_BookE(CPUPPCState *env, uint64_t ivor_mask)
1760 {
1761 const char *ivor_names[64] = {
1762 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1763 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1764 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1765 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1766 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1767 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1768 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1769 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1770 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1771 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1772 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1773 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1774 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1775 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1776 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1777 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1778 };
1779 #define SPR_BOOKE_IVORxx (-1)
1780 int ivor_sprn[64] = {
1781 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1782 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1783 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1784 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1785 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1786 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1787 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1788 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1789 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1790 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1791 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1792 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1793 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1794 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1795 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1796 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1797 };
1798 int i;
1799
1800 /* Interrupt processing */
1801 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1802 SPR_NOACCESS, SPR_NOACCESS,
1803 &spr_read_generic, &spr_write_generic,
1804 0x00000000);
1805 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1806 SPR_NOACCESS, SPR_NOACCESS,
1807 &spr_read_generic, &spr_write_generic,
1808 0x00000000);
1809 /* Debug */
1810 /* XXX : not implemented */
1811 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1812 SPR_NOACCESS, SPR_NOACCESS,
1813 &spr_read_generic, &spr_write_generic,
1814 0x00000000);
1815 /* XXX : not implemented */
1816 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1817 SPR_NOACCESS, SPR_NOACCESS,
1818 &spr_read_generic, &spr_write_generic,
1819 0x00000000);
1820 /* XXX : not implemented */
1821 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1822 SPR_NOACCESS, SPR_NOACCESS,
1823 &spr_read_generic, &spr_write_generic,
1824 0x00000000);
1825 /* XXX : not implemented */
1826 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1827 SPR_NOACCESS, SPR_NOACCESS,
1828 &spr_read_generic, &spr_write_generic,
1829 0x00000000);
1830 /* XXX : not implemented */
1831 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1832 SPR_NOACCESS, SPR_NOACCESS,
1833 &spr_read_generic, &spr_write_40x_dbcr0,
1834 0x00000000);
1835 /* XXX : not implemented */
1836 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1837 SPR_NOACCESS, SPR_NOACCESS,
1838 &spr_read_generic, &spr_write_generic,
1839 0x00000000);
1840 /* XXX : not implemented */
1841 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1842 SPR_NOACCESS, SPR_NOACCESS,
1843 &spr_read_generic, &spr_write_generic,
1844 0x00000000);
1845 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
1846 SPR_NOACCESS, SPR_NOACCESS,
1847 &spr_read_generic, &spr_write_generic,
1848 0x00000000);
1849 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
1850 SPR_NOACCESS, SPR_NOACCESS,
1851 &spr_read_generic, &spr_write_generic,
1852 0x00000000);
1853 /* XXX : not implemented */
1854 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1855 SPR_NOACCESS, SPR_NOACCESS,
1856 &spr_read_generic, &spr_write_clear,
1857 0x00000000);
1858 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1859 SPR_NOACCESS, SPR_NOACCESS,
1860 &spr_read_generic, &spr_write_generic,
1861 0x00000000);
1862 spr_register(env, SPR_BOOKE_ESR, "ESR",
1863 SPR_NOACCESS, SPR_NOACCESS,
1864 &spr_read_generic, &spr_write_generic,
1865 0x00000000);
1866 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1867 SPR_NOACCESS, SPR_NOACCESS,
1868 &spr_read_generic, &spr_write_excp_prefix,
1869 0x00000000);
1870 /* Exception vectors */
1871 for (i = 0; i < 64; i++) {
1872 if (ivor_mask & (1ULL << i)) {
1873 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1874 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1875 exit(1);
1876 }
1877 spr_register(env, ivor_sprn[i], ivor_names[i],
1878 SPR_NOACCESS, SPR_NOACCESS,
1879 &spr_read_generic, &spr_write_excp_vector,
1880 0x00000000);
1881 }
1882 }
1883 spr_register(env, SPR_BOOKE_PID, "PID",
1884 SPR_NOACCESS, SPR_NOACCESS,
1885 &spr_read_generic, &spr_write_booke_pid,
1886 0x00000000);
1887 spr_register(env, SPR_BOOKE_TCR, "TCR",
1888 SPR_NOACCESS, SPR_NOACCESS,
1889 &spr_read_generic, &spr_write_booke_tcr,
1890 0x00000000);
1891 spr_register(env, SPR_BOOKE_TSR, "TSR",
1892 SPR_NOACCESS, SPR_NOACCESS,
1893 &spr_read_generic, &spr_write_booke_tsr,
1894 0x00000000);
1895 /* Timer */
1896 spr_register(env, SPR_DECR, "DECR",
1897 SPR_NOACCESS, SPR_NOACCESS,
1898 &spr_read_decr, &spr_write_decr,
1899 0x00000000);
1900 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1901 SPR_NOACCESS, SPR_NOACCESS,
1902 SPR_NOACCESS, &spr_write_generic,
1903 0x00000000);
1904 /* SPRGs */
1905 spr_register(env, SPR_USPRG0, "USPRG0",
1906 &spr_read_generic, &spr_write_generic,
1907 &spr_read_generic, &spr_write_generic,
1908 0x00000000);
1909 spr_register(env, SPR_SPRG4, "SPRG4",
1910 SPR_NOACCESS, SPR_NOACCESS,
1911 &spr_read_generic, &spr_write_generic,
1912 0x00000000);
1913 spr_register(env, SPR_SPRG5, "SPRG5",
1914 SPR_NOACCESS, SPR_NOACCESS,
1915 &spr_read_generic, &spr_write_generic,
1916 0x00000000);
1917 spr_register(env, SPR_SPRG6, "SPRG6",
1918 SPR_NOACCESS, SPR_NOACCESS,
1919 &spr_read_generic, &spr_write_generic,
1920 0x00000000);
1921 spr_register(env, SPR_SPRG7, "SPRG7",
1922 SPR_NOACCESS, SPR_NOACCESS,
1923 &spr_read_generic, &spr_write_generic,
1924 0x00000000);
1925 spr_register(env, SPR_BOOKE_SPRG8, "SPRG8",
1926 SPR_NOACCESS, SPR_NOACCESS,
1927 &spr_read_generic, &spr_write_generic,
1928 0x00000000);
1929 spr_register(env, SPR_BOOKE_SPRG9, "SPRG9",
1930 SPR_NOACCESS, SPR_NOACCESS,
1931 &spr_read_generic, &spr_write_generic,
1932 0x00000000);
1933 }
1934
1935 static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1936 uint32_t maxsize, uint32_t flags,
1937 uint32_t nentries)
1938 {
1939 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1940 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1941 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1942 flags | nentries;
1943 }
1944
1945 /* BookE 2.06 storage control registers */
1946 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1947 uint32_t *tlbncfg, uint32_t mmucfg)
1948 {
1949 #if !defined(CONFIG_USER_ONLY)
1950 const char *mas_names[8] = {
1951 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1952 };
1953 int mas_sprn[8] = {
1954 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1955 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1956 };
1957 int i;
1958
1959 /* TLB assist registers */
1960 /* XXX : not implemented */
1961 for (i = 0; i < 8; i++) {
1962 void (*uea_write)(DisasContext *ctx, int sprn, int gprn) =
1963 &spr_write_generic32;
1964 if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1965 uea_write = &spr_write_generic;
1966 }
1967 if (mas_mask & (1 << i)) {
1968 spr_register(env, mas_sprn[i], mas_names[i],
1969 SPR_NOACCESS, SPR_NOACCESS,
1970 &spr_read_generic, uea_write,
1971 0x00000000);
1972 }
1973 }
1974 if (env->nb_pids > 1) {
1975 /* XXX : not implemented */
1976 spr_register(env, SPR_BOOKE_PID1, "PID1",
1977 SPR_NOACCESS, SPR_NOACCESS,
1978 &spr_read_generic, &spr_write_booke_pid,
1979 0x00000000);
1980 }
1981 if (env->nb_pids > 2) {
1982 /* XXX : not implemented */
1983 spr_register(env, SPR_BOOKE_PID2, "PID2",
1984 SPR_NOACCESS, SPR_NOACCESS,
1985 &spr_read_generic, &spr_write_booke_pid,
1986 0x00000000);
1987 }
1988
1989 spr_register(env, SPR_BOOKE_EPLC, "EPLC",
1990 SPR_NOACCESS, SPR_NOACCESS,
1991 &spr_read_generic, &spr_write_eplc,
1992 0x00000000);
1993 spr_register(env, SPR_BOOKE_EPSC, "EPSC",
1994 SPR_NOACCESS, SPR_NOACCESS,
1995 &spr_read_generic, &spr_write_epsc,
1996 0x00000000);
1997
1998 /* XXX : not implemented */
1999 spr_register(env, SPR_MMUCFG, "MMUCFG",
2000 SPR_NOACCESS, SPR_NOACCESS,
2001 &spr_read_generic, SPR_NOACCESS,
2002 mmucfg);
2003 switch (env->nb_ways) {
2004 case 4:
2005 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
2006 SPR_NOACCESS, SPR_NOACCESS,
2007 &spr_read_generic, SPR_NOACCESS,
2008 tlbncfg[3]);
2009 /* Fallthru */
2010 case 3:
2011 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
2012 SPR_NOACCESS, SPR_NOACCESS,
2013 &spr_read_generic, SPR_NOACCESS,
2014 tlbncfg[2]);
2015 /* Fallthru */
2016 case 2:
2017 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
2018 SPR_NOACCESS, SPR_NOACCESS,
2019 &spr_read_generic, SPR_NOACCESS,
2020 tlbncfg[1]);
2021 /* Fallthru */
2022 case 1:
2023 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
2024 SPR_NOACCESS, SPR_NOACCESS,
2025 &spr_read_generic, SPR_NOACCESS,
2026 tlbncfg[0]);
2027 /* Fallthru */
2028 case 0:
2029 default:
2030 break;
2031 }
2032 #endif
2033
2034 gen_spr_usprgh(env);
2035 }
2036
2037 /* SPR specific to PowerPC 440 implementation */
2038 static void gen_spr_440(CPUPPCState *env)
2039 {
2040 /* Cache control */
2041 /* XXX : not implemented */
2042 spr_register(env, SPR_440_DNV0, "DNV0",
2043 SPR_NOACCESS, SPR_NOACCESS,
2044 &spr_read_generic, &spr_write_generic,
2045 0x00000000);
2046 /* XXX : not implemented */
2047 spr_register(env, SPR_440_DNV1, "DNV1",
2048 SPR_NOACCESS, SPR_NOACCESS,
2049 &spr_read_generic, &spr_write_generic,
2050 0x00000000);
2051 /* XXX : not implemented */
2052 spr_register(env, SPR_440_DNV2, "DNV2",
2053 SPR_NOACCESS, SPR_NOACCESS,
2054 &spr_read_generic, &spr_write_generic,
2055 0x00000000);
2056 /* XXX : not implemented */
2057 spr_register(env, SPR_440_DNV3, "DNV3",
2058 SPR_NOACCESS, SPR_NOACCESS,
2059 &spr_read_generic, &spr_write_generic,
2060 0x00000000);
2061 /* XXX : not implemented */
2062 spr_register(env, SPR_440_DTV0, "DTV0",
2063 SPR_NOACCESS, SPR_NOACCESS,
2064 &spr_read_generic, &spr_write_generic,
2065 0x00000000);
2066 /* XXX : not implemented */
2067 spr_register(env, SPR_440_DTV1, "DTV1",
2068 SPR_NOACCESS, SPR_NOACCESS,
2069 &spr_read_generic, &spr_write_generic,
2070 0x00000000);
2071 /* XXX : not implemented */
2072 spr_register(env, SPR_440_DTV2, "DTV2",
2073 SPR_NOACCESS, SPR_NOACCESS,
2074 &spr_read_generic, &spr_write_generic,
2075 0x00000000);
2076 /* XXX : not implemented */
2077 spr_register(env, SPR_440_DTV3, "DTV3",
2078 SPR_NOACCESS, SPR_NOACCESS,
2079 &spr_read_generic, &spr_write_generic,
2080 0x00000000);
2081 /* XXX : not implemented */
2082 spr_register(env, SPR_440_DVLIM, "DVLIM",
2083 SPR_NOACCESS, SPR_NOACCESS,
2084 &spr_read_generic, &spr_write_generic,
2085 0x00000000);
2086 /* XXX : not implemented */
2087 spr_register(env, SPR_440_INV0, "INV0",
2088 SPR_NOACCESS, SPR_NOACCESS,
2089 &spr_read_generic, &spr_write_generic,
2090 0x00000000);
2091 /* XXX : not implemented */
2092 spr_register(env, SPR_440_INV1, "INV1",
2093 SPR_NOACCESS, SPR_NOACCESS,
2094 &spr_read_generic, &spr_write_generic,
2095 0x00000000);
2096 /* XXX : not implemented */
2097 spr_register(env, SPR_440_INV2, "INV2",
2098 SPR_NOACCESS, SPR_NOACCESS,
2099 &spr_read_generic, &spr_write_generic,
2100 0x00000000);
2101 /* XXX : not implemented */
2102 spr_register(env, SPR_440_INV3, "INV3",
2103 SPR_NOACCESS, SPR_NOACCESS,
2104 &spr_read_generic, &spr_write_generic,
2105 0x00000000);
2106 /* XXX : not implemented */
2107 spr_register(env, SPR_440_ITV0, "ITV0",
2108 SPR_NOACCESS, SPR_NOACCESS,
2109 &spr_read_generic, &spr_write_generic,
2110 0x00000000);
2111 /* XXX : not implemented */
2112 spr_register(env, SPR_440_ITV1, "ITV1",
2113 SPR_NOACCESS, SPR_NOACCESS,
2114 &spr_read_generic, &spr_write_generic,
2115 0x00000000);
2116 /* XXX : not implemented */
2117 spr_register(env, SPR_440_ITV2, "ITV2",
2118 SPR_NOACCESS, SPR_NOACCESS,
2119 &spr_read_generic, &spr_write_generic,
2120 0x00000000);
2121 /* XXX : not implemented */
2122 spr_register(env, SPR_440_ITV3, "ITV3",
2123 SPR_NOACCESS, SPR_NOACCESS,
2124 &spr_read_generic, &spr_write_generic,
2125 0x00000000);
2126 /* XXX : not implemented */
2127 spr_register(env, SPR_440_IVLIM, "IVLIM",
2128 SPR_NOACCESS, SPR_NOACCESS,
2129 &spr_read_generic, &spr_write_generic,
2130 0x00000000);
2131 /* Cache debug */
2132 /* XXX : not implemented */
2133 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
2134 SPR_NOACCESS, SPR_NOACCESS,
2135 &spr_read_generic, SPR_NOACCESS,
2136 0x00000000);
2137 /* XXX : not implemented */
2138 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
2139 SPR_NOACCESS, SPR_NOACCESS,
2140 &spr_read_generic, SPR_NOACCESS,
2141 0x00000000);
2142 /* XXX : not implemented */
2143 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
2144 SPR_NOACCESS, SPR_NOACCESS,
2145 &spr_read_generic, SPR_NOACCESS,
2146 0x00000000);
2147 /* XXX : not implemented */
2148 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
2149 SPR_NOACCESS, SPR_NOACCESS,
2150 &spr_read_generic, SPR_NOACCESS,
2151 0x00000000);
2152 /* XXX : not implemented */
2153 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
2154 SPR_NOACCESS, SPR_NOACCESS,
2155 &spr_read_generic, SPR_NOACCESS,
2156 0x00000000);
2157 /* XXX : not implemented */
2158 spr_register(env, SPR_440_DBDR, "DBDR",
2159 SPR_NOACCESS, SPR_NOACCESS,
2160 &spr_read_generic, &spr_write_generic,
2161 0x00000000);
2162 /* Processor control */
2163 spr_register(env, SPR_4xx_CCR0, "CCR0",
2164 SPR_NOACCESS, SPR_NOACCESS,
2165 &spr_read_generic, &spr_write_generic,
2166 0x00000000);
2167 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
2168 SPR_NOACCESS, SPR_NOACCESS,
2169 &spr_read_generic, SPR_NOACCESS,
2170 0x00000000);
2171 /* Storage control */
2172 spr_register(env, SPR_440_MMUCR, "MMUCR",
2173 SPR_NOACCESS, SPR_NOACCESS,
2174 &spr_read_generic, &spr_write_generic,
2175 0x00000000);
2176 }
2177
2178 /* SPR shared between PowerPC 40x implementations */
2179 static void gen_spr_40x(CPUPPCState *env)
2180 {
2181 /* Cache */
2182 /* not emulated, as QEMU do not emulate caches */
2183 spr_register(env, SPR_40x_DCCR, "DCCR",
2184 SPR_NOACCESS, SPR_NOACCESS,
2185 &spr_read_generic, &spr_write_generic,
2186 0x00000000);
2187 /* not emulated, as QEMU do not emulate caches */
2188 spr_register(env, SPR_40x_ICCR, "ICCR",
2189 SPR_NOACCESS, SPR_NOACCESS,
2190 &spr_read_generic, &spr_write_generic,
2191 0x00000000);
2192 /* not emulated, as QEMU do not emulate caches */
2193 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
2194 SPR_NOACCESS, SPR_NOACCESS,
2195 &spr_read_generic, SPR_NOACCESS,
2196 0x00000000);
2197 /* Exception */
2198 spr_register(env, SPR_40x_DEAR, "DEAR",
2199 SPR_NOACCESS, SPR_NOACCESS,
2200 &spr_read_generic, &spr_write_generic,
2201 0x00000000);
2202 spr_register(env, SPR_40x_ESR, "ESR",
2203 SPR_NOACCESS, SPR_NOACCESS,
2204 &spr_read_generic, &spr_write_generic,
2205 0x00000000);
2206 spr_register(env, SPR_40x_EVPR, "EVPR",
2207 SPR_NOACCESS, SPR_NOACCESS,
2208 &spr_read_generic, &spr_write_excp_prefix,
2209 0x00000000);
2210 spr_register(env, SPR_40x_SRR2, "SRR2",
2211 &spr_read_generic, &spr_write_generic,
2212 &spr_read_generic, &spr_write_generic,
2213 0x00000000);
2214 spr_register(env, SPR_40x_SRR3, "SRR3",
2215 &spr_read_generic, &spr_write_generic,
2216 &spr_read_generic, &spr_write_generic,
2217 0x00000000);
2218 /* Timers */
2219 spr_register(env, SPR_40x_PIT, "PIT",
2220 SPR_NOACCESS, SPR_NOACCESS,
2221 &spr_read_40x_pit, &spr_write_40x_pit,
2222 0x00000000);
2223 spr_register(env, SPR_40x_TCR, "TCR",
2224 SPR_NOACCESS, SPR_NOACCESS,
2225 &spr_read_generic, &spr_write_booke_tcr,
2226 0x00000000);
2227 spr_register(env, SPR_40x_TSR, "TSR",
2228 SPR_NOACCESS, SPR_NOACCESS,
2229 &spr_read_generic, &spr_write_booke_tsr,
2230 0x00000000);
2231 }
2232
2233 /* SPR specific to PowerPC 405 implementation */
2234 static void gen_spr_405(CPUPPCState *env)
2235 {
2236 /* MMU */
2237 spr_register(env, SPR_40x_PID, "PID",
2238 SPR_NOACCESS, SPR_NOACCESS,
2239 &spr_read_generic, &spr_write_generic,
2240 0x00000000);
2241 spr_register(env, SPR_4xx_CCR0, "CCR0",
2242 SPR_NOACCESS, SPR_NOACCESS,
2243 &spr_read_generic, &spr_write_generic,
2244 0x00700000);
2245 /* Debug interface */
2246 /* XXX : not implemented */
2247 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2248 SPR_NOACCESS, SPR_NOACCESS,
2249 &spr_read_generic, &spr_write_40x_dbcr0,
2250 0x00000000);
2251 /* XXX : not implemented */
2252 spr_register(env, SPR_405_DBCR1, "DBCR1",
2253 SPR_NOACCESS, SPR_NOACCESS,
2254 &spr_read_generic, &spr_write_generic,
2255 0x00000000);
2256 /* XXX : not implemented */
2257 spr_register(env, SPR_40x_DBSR, "DBSR",
2258 SPR_NOACCESS, SPR_NOACCESS,
2259 &spr_read_generic, &spr_write_clear,
2260 /* Last reset was system reset */
2261 0x00000300);
2262 /* XXX : not implemented */
2263 spr_register(env, SPR_40x_DAC1, "DAC1",
2264 SPR_NOACCESS, SPR_NOACCESS,
2265 &spr_read_generic, &spr_write_generic,
2266 0x00000000);
2267 spr_register(env, SPR_40x_DAC2, "DAC2",
2268 SPR_NOACCESS, SPR_NOACCESS,
2269 &spr_read_generic, &spr_write_generic,
2270 0x00000000);
2271 /* XXX : not implemented */
2272 spr_register(env, SPR_405_DVC1, "DVC1",
2273 SPR_NOACCESS, SPR_NOACCESS,
2274 &spr_read_generic, &spr_write_generic,
2275 0x00000000);
2276 /* XXX : not implemented */
2277 spr_register(env, SPR_405_DVC2, "DVC2",
2278 SPR_NOACCESS, SPR_NOACCESS,
2279 &spr_read_generic, &spr_write_generic,
2280 0x00000000);
2281 /* XXX : not implemented */
2282 spr_register(env, SPR_40x_IAC1, "IAC1",
2283 SPR_NOACCESS, SPR_NOACCESS,
2284 &spr_read_generic, &spr_write_generic,
2285 0x00000000);
2286 spr_register(env, SPR_40x_IAC2, "IAC2",
2287 SPR_NOACCESS, SPR_NOACCESS,
2288 &spr_read_generic, &spr_write_generic,
2289 0x00000000);
2290 /* XXX : not implemented */
2291 spr_register(env, SPR_405_IAC3, "IAC3",
2292 SPR_NOACCESS, SPR_NOACCESS,
2293 &spr_read_generic, &spr_write_generic,
2294 0x00000000);
2295 /* XXX : not implemented */
2296 spr_register(env, SPR_405_IAC4, "IAC4",
2297 SPR_NOACCESS, SPR_NOACCESS,
2298 &spr_read_generic, &spr_write_generic,
2299 0x00000000);
2300 /* Storage control */
2301 /* XXX: TODO: not implemented */
2302 spr_register(env, SPR_405_SLER, "SLER",
2303 SPR_NOACCESS, SPR_NOACCESS,
2304 &spr_read_generic, &spr_write_40x_sler,
2305 0x00000000);
2306 spr_register(env, SPR_40x_ZPR, "ZPR",
2307 SPR_NOACCESS, SPR_NOACCESS,
2308 &spr_read_generic, &spr_write_generic,
2309 0x00000000);
2310 /* XXX : not implemented */
2311 spr_register(env, SPR_405_SU0R, "SU0R",
2312 SPR_NOACCESS, SPR_NOACCESS,
2313 &spr_read_generic, &spr_write_generic,
2314 0x00000000);
2315 /* SPRG */
2316 spr_register(env, SPR_USPRG0, "USPRG0",
2317 &spr_read_ureg, SPR_NOACCESS,
2318 &spr_read_ureg, SPR_NOACCESS,
2319 0x00000000);
2320 spr_register(env, SPR_SPRG4, "SPRG4",
2321 SPR_NOACCESS, SPR_NOACCESS,
2322 &spr_read_generic, &spr_write_generic,
2323 0x00000000);
2324 spr_register(env, SPR_SPRG5, "SPRG5",
2325 SPR_NOACCESS, SPR_NOACCESS,
2326 spr_read_generic, &spr_write_generic,
2327 0x00000000);
2328 spr_register(env, SPR_SPRG6, "SPRG6",
2329 SPR_NOACCESS, SPR_NOACCESS,
2330 spr_read_generic, &spr_write_generic,
2331 0x00000000);
2332 spr_register(env, SPR_SPRG7, "SPRG7",
2333 SPR_NOACCESS, SPR_NOACCESS,
2334 spr_read_generic, &spr_write_generic,
2335 0x00000000);
2336 gen_spr_usprgh(env);
2337 }
2338
2339 /* SPR shared between PowerPC 401 & 403 implementations */
2340 static void gen_spr_401_403(CPUPPCState *env)
2341 {
2342 /* Time base */
2343 spr_register(env, SPR_403_VTBL, "TBL",
2344 &spr_read_tbl, SPR_NOACCESS,
2345 &spr_read_tbl, SPR_NOACCESS,
2346 0x00000000);
2347 spr_register(env, SPR_403_TBL, "TBL",
2348 SPR_NOACCESS, SPR_NOACCESS,
2349 SPR_NOACCESS, &spr_write_tbl,
2350 0x00000000);
2351 spr_register(env, SPR_403_VTBU, "TBU",
2352 &spr_read_tbu, SPR_NOACCESS,
2353 &spr_read_tbu, SPR_NOACCESS,
2354 0x00000000);
2355 spr_register(env, SPR_403_TBU, "TBU",
2356 SPR_NOACCESS, SPR_NOACCESS,
2357 SPR_NOACCESS, &spr_write_tbu,
2358 0x00000000);
2359 /* Debug */
2360 /* not emulated, as QEMU do not emulate caches */
2361 spr_register(env, SPR_403_CDBCR, "CDBCR",
2362 SPR_NOACCESS, SPR_NOACCESS,
2363 &spr_read_generic, &spr_write_generic,
2364 0x00000000);
2365 }
2366
2367 /* SPR specific to PowerPC 401 implementation */
2368 static void gen_spr_401(CPUPPCState *env)
2369 {
2370 /* Debug interface */
2371 /* XXX : not implemented */
2372 spr_register(env, SPR_40x_DBCR0, "DBCR",
2373 SPR_NOACCESS, SPR_NOACCESS,
2374 &spr_read_generic, &spr_write_40x_dbcr0,
2375 0x00000000);
2376 /* XXX : not implemented */
2377 spr_register(env, SPR_40x_DBSR, "DBSR",
2378 SPR_NOACCESS, SPR_NOACCESS,
2379 &spr_read_generic, &spr_write_clear,
2380 /* Last reset was system reset */
2381 0x00000300);
2382 /* XXX : not implemented */
2383 spr_register(env, SPR_40x_DAC1, "DAC",
2384 SPR_NOACCESS, SPR_NOACCESS,
2385 &spr_read_generic, &spr_write_generic,
2386 0x00000000);
2387 /* XXX : not implemented */
2388 spr_register(env, SPR_40x_IAC1, "IAC",
2389 SPR_NOACCESS, SPR_NOACCESS,
2390 &spr_read_generic, &spr_write_generic,
2391 0x00000000);
2392 /* Storage control */
2393 /* XXX: TODO: not implemented */
2394 spr_register(env, SPR_405_SLER, "SLER",
2395 SPR_NOACCESS, SPR_NOACCESS,
2396 &spr_read_generic, &spr_write_40x_sler,
2397 0x00000000);
2398 /* not emulated, as QEMU never does speculative access */
2399 spr_register(env, SPR_40x_SGR, "SGR",
2400 SPR_NOACCESS, SPR_NOACCESS,
2401 &spr_read_generic, &spr_write_generic,
2402 0xFFFFFFFF);
2403 /* not emulated, as QEMU do not emulate caches */
2404 spr_register(env, SPR_40x_DCWR, "DCWR",
2405 SPR_NOACCESS, SPR_NOACCESS,
2406 &spr_read_generic, &spr_write_generic,
2407 0x00000000);
2408 }
2409
2410 static void gen_spr_401x2(CPUPPCState *env)
2411 {
2412 gen_spr_401(env);
2413 spr_register(env, SPR_40x_PID, "PID",
2414 SPR_NOACCESS, SPR_NOACCESS,
2415 &spr_read_generic, &spr_write_generic,
2416 0x00000000);
2417 spr_register(env, SPR_40x_ZPR, "ZPR",
2418 SPR_NOACCESS, SPR_NOACCESS,
2419 &spr_read_generic, &spr_write_generic,
2420 0x00000000);
2421 }
2422
2423 /* SPR specific to PowerPC 403 implementation */
2424 static void gen_spr_403(CPUPPCState *env)
2425 {
2426 /* Debug interface */
2427 /* XXX : not implemented */
2428 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2429 SPR_NOACCESS, SPR_NOACCESS,
2430 &spr_read_generic, &spr_write_40x_dbcr0,
2431 0x00000000);
2432 /* XXX : not implemented */
2433 spr_register(env, SPR_40x_DBSR, "DBSR",
2434 SPR_NOACCESS, SPR_NOACCESS,
2435 &spr_read_generic, &spr_write_clear,
2436 /* Last reset was system reset */
2437 0x00000300);
2438 /* XXX : not implemented */
2439 spr_register(env, SPR_40x_DAC1, "DAC1",
2440 SPR_NOACCESS, SPR_NOACCESS,
2441 &spr_read_generic, &spr_write_generic,
2442 0x00000000);
2443 /* XXX : not implemented */
2444 spr_register(env, SPR_40x_DAC2, "DAC2",
2445 SPR_NOACCESS, SPR_NOACCESS,
2446 &spr_read_generic, &spr_write_generic,
2447 0x00000000);
2448 /* XXX : not implemented */
2449 spr_register(env, SPR_40x_IAC1, "IAC1",
2450 SPR_NOACCESS, SPR_NOACCESS,
2451 &spr_read_generic, &spr_write_generic,
2452 0x00000000);
2453 /* XXX : not implemented */
2454 spr_register(env, SPR_40x_IAC2, "IAC2",
2455 SPR_NOACCESS, SPR_NOACCESS,
2456 &spr_read_generic, &spr_write_generic,
2457 0x00000000);
2458 }
2459
2460 static void gen_spr_403_real(CPUPPCState *env)
2461 {
2462 spr_register(env, SPR_403_PBL1, "PBL1",
2463 SPR_NOACCESS, SPR_NOACCESS,
2464 &spr_read_403_pbr, &spr_write_403_pbr,
2465 0x00000000);
2466 spr_register(env, SPR_403_PBU1, "PBU1",
2467 SPR_NOACCESS, SPR_NOACCESS,
2468 &spr_read_403_pbr, &spr_write_403_pbr,
2469 0x00000000);
2470 spr_register(env, SPR_403_PBL2, "PBL2",
2471 SPR_NOACCESS, SPR_NOACCESS,
2472 &spr_read_403_pbr, &spr_write_403_pbr,
2473 0x00000000);
2474 spr_register(env, SPR_403_PBU2, "PBU2",
2475 SPR_NOACCESS, SPR_NOACCESS,
2476 &spr_read_403_pbr, &spr_write_403_pbr,
2477 0x00000000);
2478 }
2479
2480 static void gen_spr_403_mmu(CPUPPCState *env)
2481 {
2482 /* MMU */
2483 spr_register(env, SPR_40x_PID, "PID",
2484 SPR_NOACCESS, SPR_NOACCESS,
2485 &spr_read_generic, &spr_write_generic,
2486 0x00000000);
2487 spr_register(env, SPR_40x_ZPR, "ZPR",
2488 SPR_NOACCESS, SPR_NOACCESS,
2489 &spr_read_generic, &spr_write_generic,
2490 0x00000000);
2491 }
2492
2493 /* SPR specific to PowerPC compression coprocessor extension */
2494 static void gen_spr_compress(CPUPPCState *env)
2495 {
2496 /* XXX : not implemented */
2497 spr_register(env, SPR_401_SKR, "SKR",
2498 SPR_NOACCESS, SPR_NOACCESS,
2499 &spr_read_generic, &spr_write_generic,
2500 0x00000000);
2501 }
2502
2503 static void gen_spr_5xx_8xx(CPUPPCState *env)
2504 {
2505 /* Exception processing */
2506 spr_register_kvm(env, SPR_DSISR, "DSISR",
2507 SPR_NOACCESS, SPR_NOACCESS,
2508 &spr_read_generic, &spr_write_generic,
2509 KVM_REG_PPC_DSISR, 0x00000000);
2510 spr_register_kvm(env, SPR_DAR, "DAR",
2511 SPR_NOACCESS, SPR_NOACCESS,
2512 &spr_read_generic, &spr_write_generic,
2513 KVM_REG_PPC_DAR, 0x00000000);
2514 /* Timer */
2515 spr_register(env, SPR_DECR, "DECR",
2516 SPR_NOACCESS, SPR_NOACCESS,
2517 &spr_read_decr, &spr_write_decr,
2518 0x00000000);
2519 /* XXX : not implemented */
2520 spr_register(env, SPR_MPC_EIE, "EIE",
2521 SPR_NOACCESS, SPR_NOACCESS,
2522 &spr_read_generic, &spr_write_generic,
2523 0x00000000);
2524 /* XXX : not implemented */
2525 spr_register(env, SPR_MPC_EID, "EID",
2526 SPR_NOACCESS, SPR_NOACCESS,
2527 &spr_read_generic, &spr_write_generic,
2528 0x00000000);
2529 /* XXX : not implemented */
2530 spr_register(env, SPR_MPC_NRI, "NRI",
2531 SPR_NOACCESS, SPR_NOACCESS,
2532 &spr_read_generic, &spr_write_generic,
2533 0x00000000);
2534 /* XXX : not implemented */
2535 spr_register(env, SPR_MPC_CMPA, "CMPA",
2536 SPR_NOACCESS, SPR_NOACCESS,
2537 &spr_read_generic, &spr_write_generic,
2538 0x00000000);
2539 /* XXX : not implemented */
2540 spr_register(env, SPR_MPC_CMPB, "CMPB",
2541 SPR_NOACCESS, SPR_NOACCESS,
2542 &spr_read_generic, &spr_write_generic,
2543 0x00000000);
2544 /* XXX : not implemented */
2545 spr_register(env, SPR_MPC_CMPC, "CMPC",
2546 SPR_NOACCESS, SPR_NOACCESS,
2547 &spr_read_generic, &spr_write_generic,
2548 0x00000000);
2549 /* XXX : not implemented */
2550 spr_register(env, SPR_MPC_CMPD, "CMPD",
2551 SPR_NOACCESS, SPR_NOACCESS,
2552 &spr_read_generic, &spr_write_generic,
2553 0x00000000);
2554 /* XXX : not implemented */
2555 spr_register(env, SPR_MPC_ECR, "ECR",
2556 SPR_NOACCESS, SPR_NOACCESS,
2557 &spr_read_generic, &spr_write_generic,
2558 0x00000000);
2559 /* XXX : not implemented */
2560 spr_register(env, SPR_MPC_DER, "DER",
2561 SPR_NOACCESS, SPR_NOACCESS,
2562 &spr_read_generic, &spr_write_generic,
2563 0x00000000);
2564 /* XXX : not implemented */
2565 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2566 SPR_NOACCESS, SPR_NOACCESS,
2567 &spr_read_generic, &spr_write_generic,
2568 0x00000000);
2569 /* XXX : not implemented */
2570 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2571 SPR_NOACCESS, SPR_NOACCESS,
2572 &spr_read_generic, &spr_write_generic,
2573 0x00000000);
2574 /* XXX : not implemented */
2575 spr_register(env, SPR_MPC_CMPE, "CMPE",
2576 SPR_NOACCESS, SPR_NOACCESS,
2577 &spr_read_generic, &spr_write_generic,
2578 0x00000000);
2579 /* XXX : not implemented */
2580 spr_register(env, SPR_MPC_CMPF, "CMPF",
2581 SPR_NOACCESS, SPR_NOACCESS,
2582 &spr_read_generic, &spr_write_generic,
2583 0x00000000);
2584 /* XXX : not implemented */
2585 spr_register(env, SPR_MPC_CMPG, "CMPG",
2586 SPR_NOACCESS, SPR_NOACCESS,
2587 &spr_read_generic, &spr_write_generic,
2588 0x00000000);
2589 /* XXX : not implemented */
2590 spr_register(env, SPR_MPC_CMPH, "CMPH",
2591 SPR_NOACCESS, SPR_NOACCESS,
2592 &spr_read_generic, &spr_write_generic,
2593 0x00000000);
2594 /* XXX : not implemented */
2595 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2596 SPR_NOACCESS, SPR_NOACCESS,
2597 &spr_read_generic, &spr_write_generic,
2598 0x00000000);
2599 /* XXX : not implemented */
2600 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2601 SPR_NOACCESS, SPR_NOACCESS,
2602 &spr_read_generic, &spr_write_generic,
2603 0x00000000);
2604 /* XXX : not implemented */
2605 spr_register(env, SPR_MPC_BAR, "BAR",
2606 SPR_NOACCESS, SPR_NOACCESS,
2607 &spr_read_generic, &spr_write_generic,
2608 0x00000000);
2609 /* XXX : not implemented */
2610 spr_register(env, SPR_MPC_DPDR, "DPDR",
2611 SPR_NOACCESS, SPR_NOACCESS,
2612 &spr_read_generic, &spr_write_generic,
2613 0x00000000);
2614 /* XXX : not implemented */
2615 spr_register(env, SPR_MPC_IMMR, "IMMR",
2616 SPR_NOACCESS, SPR_NOACCESS,
2617 &spr_read_generic, &spr_write_generic,
2618 0x00000000);
2619 }
2620
2621 static void gen_spr_5xx(CPUPPCState *env)
2622 {
2623 /* XXX : not implemented */
2624 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2625 SPR_NOACCESS, SPR_NOACCESS,
2626 &spr_read_generic, &spr_write_generic,
2627 0x00000000);
2628 /* XXX : not implemented */
2629 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2630 SPR_NOACCESS, SPR_NOACCESS,
2631 &spr_read_generic, &spr_write_generic,
2632 0x00000000);
2633 /* XXX : not implemented */
2634 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2635 SPR_NOACCESS, SPR_NOACCESS,
2636 &spr_read_generic, &spr_write_generic,
2637 0x00000000);
2638 /* XXX : not implemented */
2639 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2640 SPR_NOACCESS, SPR_NOACCESS,
2641 &spr_read_generic, &spr_write_generic,
2642 0x00000000);
2643 /* XXX : not implemented */
2644 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2645 SPR_NOACCESS, SPR_NOACCESS,
2646 &spr_read_generic, &spr_write_generic,
2647 0x00000000);
2648 /* XXX : not implemented */
2649 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2650 SPR_NOACCESS, SPR_NOACCESS,
2651 &spr_read_generic, &spr_write_generic,
2652 0x00000000);
2653 /* XXX : not implemented */
2654 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2655 SPR_NOACCESS, SPR_NOACCESS,
2656 &spr_read_generic, &spr_write_generic,
2657 0x00000000);
2658 /* XXX : not implemented */
2659 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2660 SPR_NOACCESS, SPR_NOACCESS,
2661 &spr_read_generic, &spr_write_generic,
2662 0x00000000);
2663 /* XXX : not implemented */
2664 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2665 SPR_NOACCESS, SPR_NOACCESS,
2666 &spr_read_generic, &spr_write_generic,
2667 0x00000000);
2668 /* XXX : not implemented */
2669 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2670 SPR_NOACCESS, SPR_NOACCESS,
2671 &spr_read_generic, &spr_write_generic,
2672 0x00000000);
2673 /* XXX : not implemented */
2674 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2675 SPR_NOACCESS, SPR_NOACCESS,
2676 &spr_read_generic, &spr_write_generic,
2677 0x00000000);
2678 /* XXX : not implemented */
2679 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2680 SPR_NOACCESS, SPR_NOACCESS,
2681 &spr_read_generic, &spr_write_generic,
2682 0x00000000);
2683 /* XXX : not implemented */
2684 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2685 SPR_NOACCESS, SPR_NOACCESS,
2686 &spr_read_generic, &spr_write_generic,
2687 0x00000000);
2688 /* XXX : not implemented */
2689 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2690 SPR_NOACCESS, SPR_NOACCESS,
2691 &spr_read_generic, &spr_write_generic,
2692 0x00000000);
2693 /* XXX : not implemented */
2694 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2695 SPR_NOACCESS, SPR_NOACCESS,
2696 &spr_read_generic, &spr_write_generic,
2697 0x00000000);
2698 /* XXX : not implemented */
2699 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2700 SPR_NOACCESS, SPR_NOACCESS,
2701 &spr_read_generic, &spr_write_generic,
2702 0x00000000);
2703 /* XXX : not implemented */
2704 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2705 SPR_NOACCESS, SPR_NOACCESS,
2706 &spr_read_generic, &spr_write_generic,
2707 0x00000000);
2708 /* XXX : not implemented */
2709 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2710 SPR_NOACCESS, SPR_NOACCESS,
2711 &spr_read_generic, &spr_write_generic,
2712 0x00000000);
2713 /* XXX : not implemented */
2714 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2715 SPR_NOACCESS, SPR_NOACCESS,
2716 &spr_read_generic, &spr_write_generic,
2717 0x00000000);
2718 /* XXX : not implemented */
2719 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2720 SPR_NOACCESS, SPR_NOACCESS,
2721 &spr_read_generic, &spr_write_generic,
2722 0x00000000);
2723 /* XXX : not implemented */
2724 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2725 SPR_NOACCESS, SPR_NOACCESS,
2726 &spr_read_generic, &spr_write_generic,
2727 0x00000000);
2728 }
2729
2730 static void gen_spr_8xx(CPUPPCState *env)
2731 {
2732 /* XXX : not implemented */
2733 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2734 SPR_NOACCESS, SPR_NOACCESS,
2735 &spr_read_generic, &spr_write_generic,
2736 0x00000000);
2737 /* XXX : not implemented */
2738 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2739 SPR_NOACCESS, SPR_NOACCESS,
2740 &spr_read_generic, &spr_write_generic,
2741 0x00000000);
2742 /* XXX : not implemented */
2743 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2744 SPR_NOACCESS, SPR_NOACCESS,
2745 &spr_read_generic, &spr_write_generic,
2746 0x00000000);
2747 /* XXX : not implemented */
2748 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2749 SPR_NOACCESS, SPR_NOACCESS,
2750 &spr_read_generic, &spr_write_generic,
2751 0x00000000);
2752 /* XXX : not implemented */
2753 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2754 SPR_NOACCESS, SPR_NOACCESS,
2755 &spr_read_generic, &spr_write_generic,
2756 0x00000000);
2757 /* XXX : not implemented */
2758 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2759 SPR_NOACCESS, SPR_NOACCESS,
2760 &spr_read_generic, &spr_write_generic,
2761 0x00000000);
2762 /* XXX : not implemented */
2763 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2764 SPR_NOACCESS, SPR_NOACCESS,
2765 &spr_read_generic, &spr_write_generic,
2766 0x00000000);
2767 /* XXX : not implemented */
2768 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2769 SPR_NOACCESS, SPR_NOACCESS,
2770 &spr_read_generic, &spr_write_generic,
2771 0x00000000);
2772 /* XXX : not implemented */
2773 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2774 SPR_NOACCESS, SPR_NOACCESS,
2775 &spr_read_generic, &spr_write_generic,
2776 0x00000000);
2777 /* XXX : not implemented */
2778 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2779 SPR_NOACCESS, SPR_NOACCESS,
2780 &spr_read_generic, &spr_write_generic,
2781 0x00000000);
2782 /* XXX : not implemented */
2783 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2784 SPR_NOACCESS, SPR_NOACCESS,
2785 &spr_read_generic, &spr_write_generic,
2786 0x00000000);
2787 /* XXX : not implemented */
2788 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2789 SPR_NOACCESS, SPR_NOACCESS,
2790 &spr_read_generic, &spr_write_generic,
2791 0x00000000);
2792 /* XXX : not implemented */
2793 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2794 SPR_NOACCESS, SPR_NOACCESS,
2795 &spr_read_generic, &spr_write_generic,
2796 0x00000000);
2797 /* XXX : not implemented */
2798 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2799 SPR_NOACCESS, SPR_NOACCESS,
2800 &spr_read_generic, &spr_write_generic,
2801 0x00000000);
2802 /* XXX : not implemented */
2803 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2804 SPR_NOACCESS, SPR_NOACCESS,
2805 &spr_read_generic, &spr_write_generic,
2806 0x00000000);
2807 /* XXX : not implemented */
2808 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2809 SPR_NOACCESS, SPR_NOACCESS,
2810 &spr_read_generic, &spr_write_generic,
2811 0x00000000);
2812 /* XXX : not implemented */
2813 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2814 SPR_NOACCESS, SPR_NOACCESS,
2815 &spr_read_generic, &spr_write_generic,
2816 0x00000000);
2817 /* XXX : not implemented */
2818 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2819 SPR_NOACCESS, SPR_NOACCESS,
2820 &spr_read_generic, &spr_write_generic,
2821 0x00000000);
2822 /* XXX : not implemented */
2823 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2824 SPR_NOACCESS, SPR_NOACCESS,
2825 &spr_read_generic, &spr_write_generic,
2826 0x00000000);
2827 /* XXX : not implemented */
2828 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2829 SPR_NOACCESS, SPR_NOACCESS,
2830 &spr_read_generic, &spr_write_generic,
2831 0x00000000);
2832 /* XXX : not implemented */
2833 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2834 SPR_NOACCESS, SPR_NOACCESS,
2835 &spr_read_generic, &spr_write_generic,
2836 0x00000000);
2837 /* XXX : not implemented */
2838 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2839 SPR_NOACCESS, SPR_NOACCESS,
2840 &spr_read_generic, &spr_write_generic,
2841 0x00000000);
2842 /* XXX : not implemented */
2843 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2844 SPR_NOACCESS, SPR_NOACCESS,
2845 &spr_read_generic, &spr_write_generic,
2846 0x00000000);
2847 /* XXX : not implemented */
2848 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2849 SPR_NOACCESS, SPR_NOACCESS,
2850 &spr_read_generic, &spr_write_generic,
2851 0x00000000);
2852 /* XXX : not implemented */
2853 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2854 SPR_NOACCESS, SPR_NOACCESS,
2855 &spr_read_generic, &spr_write_generic,
2856 0x00000000);
2857 }
2858
2859 /*
2860 * AMR => SPR 29 (Power 2.04)
2861 * CTRL => SPR 136 (Power 2.04)
2862 * CTRL => SPR 152 (Power 2.04)
2863 * SCOMC => SPR 276 (64 bits ?)
2864 * SCOMD => SPR 277 (64 bits ?)
2865 * TBU40 => SPR 286 (Power 2.04 hypv)
2866 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2867 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2868 * HDSISR => SPR 306 (Power 2.04 hypv)
2869 * HDAR => SPR 307 (Power 2.04 hypv)
2870 * PURR => SPR 309 (Power 2.04 hypv)
2871 * HDEC => SPR 310 (Power 2.04 hypv)
2872 * HIOR => SPR 311 (hypv)
2873 * RMOR => SPR 312 (970)
2874 * HRMOR => SPR 313 (Power 2.04 hypv)
2875 * HSRR0 => SPR 314 (Power 2.04 hypv)
2876 * HSRR1 => SPR 315 (Power 2.04 hypv)
2877 * LPIDR => SPR 317 (970)
2878 * EPR => SPR 702 (Power 2.04 emb)
2879 * perf => 768-783 (Power 2.04)
2880 * perf => 784-799 (Power 2.04)
2881 * PPR => SPR 896 (Power 2.04)
2882 * DABRX => 1015 (Power 2.04 hypv)
2883 * FPECR => SPR 1022 (?)
2884 * ... and more (thermal management, performance counters, ...)
2885 */
2886
2887 /*****************************************************************************/
2888 /* Exception vectors models */
2889 static void init_excp_4xx_real(CPUPPCState *env)
2890 {
2891 #if !defined(CONFIG_USER_ONLY)
2892 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2893 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2894 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2895 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2896 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2897 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2898 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2899 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2900 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2901 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2902 env->ivor_mask = 0x0000FFF0UL;
2903 env->ivpr_mask = 0xFFFF0000UL;
2904 /* Hardware reset vector */
2905 env->hreset_vector = 0xFFFFFFFCUL;
2906 #endif
2907 }
2908
2909 static void init_excp_4xx_softmmu(CPUPPCState *env)
2910 {
2911 #if !defined(CONFIG_USER_ONLY)
2912 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2913 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2914 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2915 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2916 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2917 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2918 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2919 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2920 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2921 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2922 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2923 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2924 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2925 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2926 env->ivor_mask = 0x0000FFF0UL;
2927 env->ivpr_mask = 0xFFFF0000UL;
2928 /* Hardware reset vector */
2929 env->hreset_vector = 0xFFFFFFFCUL;
2930 #endif
2931 }
2932
2933 static void init_excp_MPC5xx(CPUPPCState *env)
2934 {
2935 #if !defined(CONFIG_USER_ONLY)
2936 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2937 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2938 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2939 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2940 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2941 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2942 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2943 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2944 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2945 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2946 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2947 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2948 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2949 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2950 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2951 env->ivor_mask = 0x0000FFF0UL;
2952 env->ivpr_mask = 0xFFFF0000UL;
2953 /* Hardware reset vector */
2954 env->hreset_vector = 0x00000100UL;
2955 #endif
2956 }
2957
2958 static void init_excp_MPC8xx(CPUPPCState *env)
2959 {
2960 #if !defined(CONFIG_USER_ONLY)
2961 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2962 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2963 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2964 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2965 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2966 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2967 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2968 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2969 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2970 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2971 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2972 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2973 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2974 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2975 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2976 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2977 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2978 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2979 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2980 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2981 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2982 env->ivor_mask = 0x0000FFF0UL;
2983 env->ivpr_mask = 0xFFFF0000UL;
2984 /* Hardware reset vector */
2985 env->hreset_vector = 0x00000100UL;
2986 #endif
2987 }
2988
2989 static void init_excp_G2(CPUPPCState *env)
2990 {
2991 #if !defined(CONFIG_USER_ONLY)
2992 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2993 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2994 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2995 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2996 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2997 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2998 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2999 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3000 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3001 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
3002 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3003 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3004 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3005 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3006 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3007 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3008 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3009 /* Hardware reset vector */
3010 env->hreset_vector = 0x00000100UL;
3011 #endif
3012 }
3013
3014 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
3015 {
3016 #if !defined(CONFIG_USER_ONLY)
3017 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
3018 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
3019 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
3020 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
3021 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
3022 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
3023 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
3024 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
3025 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
3026 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
3027 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
3028 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
3029 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
3030 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
3031 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
3032 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
3033 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
3034 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
3035 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
3036 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
3037 env->ivor_mask = 0x0000FFF7UL;
3038 env->ivpr_mask = ivpr_mask;
3039 /* Hardware reset vector */
3040 env->hreset_vector = 0xFFFFFFFCUL;
3041 #endif
3042 }
3043
3044 static void init_excp_BookE(CPUPPCState *env)
3045 {
3046 #if !defined(CONFIG_USER_ONLY)
3047 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
3048 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
3049 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
3050 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
3051 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
3052 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
3053 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
3054 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
3055 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
3056 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
3057 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
3058 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
3059 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
3060 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
3061 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
3062 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
3063 env->ivor_mask = 0x0000FFF0UL;
3064 env->ivpr_mask = 0xFFFF0000UL;
3065 /* Hardware reset vector */
3066 env->hreset_vector = 0xFFFFFFFCUL;
3067 #endif
3068 }
3069
3070 static void init_excp_601(CPUPPCState *env)
3071 {
3072 #if !defined(CONFIG_USER_ONLY)
3073 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3074 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3075 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3076 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3077 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3078 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3079 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3080 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3081 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3082 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
3083 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3084 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
3085 /* Hardware reset vector */
3086 env->hreset_vector = 0x00000100UL;
3087 #endif
3088 }
3089
3090 static void init_excp_602(CPUPPCState *env)
3091 {
3092 #if !defined(CONFIG_USER_ONLY)
3093 /* XXX: exception prefix has a special behavior on 602 */
3094 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3095 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3096 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3097 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3098 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3099 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3100 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3101 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3102 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3103 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3104 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3105 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3106 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3107 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3108 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3109 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3110 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
3111 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
3112 /* Hardware reset vector */
3113 env->hreset_vector = 0x00000100UL;