stubs: Move qemu_fd_register stub to util/main-loop.c
[qemu.git] / target / riscv / cpu.h
1 /*
2 * QEMU RISC-V CPU
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #ifndef RISCV_CPU_H
21 #define RISCV_CPU_H
22
23 #include "hw/core/cpu.h"
24 #include "hw/registerfields.h"
25 #include "exec/cpu-defs.h"
26 #include "fpu/softfloat-types.h"
27
28 #define TCG_GUEST_DEFAULT_MO 0
29
30 #define TYPE_RISCV_CPU "riscv-cpu"
31
32 #define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU
33 #define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX)
34 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
35
36 #define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any")
37 #define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
38 #define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
39 #define TYPE_RISCV_CPU_IBEX RISCV_CPU_TYPE_NAME("lowrisc-ibex")
40 #define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
41 #define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
42 #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
43 #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
44 #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
45
46 #define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2))
47 #define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2))
48
49 #if defined(TARGET_RISCV32)
50 #define RVXLEN RV32
51 #elif defined(TARGET_RISCV64)
52 #define RVXLEN RV64
53 #endif
54
55 #define RV(x) ((target_ulong)1 << (x - 'A'))
56
57 #define RVI RV('I')
58 #define RVE RV('E') /* E and I are mutually exclusive */
59 #define RVM RV('M')
60 #define RVA RV('A')
61 #define RVF RV('F')
62 #define RVD RV('D')
63 #define RVV RV('V')
64 #define RVC RV('C')
65 #define RVS RV('S')
66 #define RVU RV('U')
67 #define RVH RV('H')
68
69 /* S extension denotes that Supervisor mode exists, however it is possible
70 to have a core that support S mode but does not have an MMU and there
71 is currently no bit in misa to indicate whether an MMU exists or not
72 so a cpu features bitfield is required, likewise for optional PMP support */
73 enum {
74 RISCV_FEATURE_MMU,
75 RISCV_FEATURE_PMP,
76 RISCV_FEATURE_MISA
77 };
78
79 #define PRIV_VERSION_1_10_0 0x00011000
80 #define PRIV_VERSION_1_11_0 0x00011100
81
82 #define VEXT_VERSION_0_07_1 0x00000701
83
84 #define TRANSLATE_PMP_FAIL 2
85 #define TRANSLATE_FAIL 1
86 #define TRANSLATE_SUCCESS 0
87 #define MMU_USER_IDX 3
88
89 #define MAX_RISCV_PMPS (16)
90
91 typedef struct CPURISCVState CPURISCVState;
92
93 #include "pmp.h"
94
95 #define RV_VLEN_MAX 256
96
97 FIELD(VTYPE, VLMUL, 0, 2)
98 FIELD(VTYPE, VSEW, 2, 3)
99 FIELD(VTYPE, VEDIV, 5, 2)
100 FIELD(VTYPE, RESERVED, 7, sizeof(target_ulong) * 8 - 9)
101 FIELD(VTYPE, VILL, sizeof(target_ulong) * 8 - 1, 1)
102
103 struct CPURISCVState {
104 target_ulong gpr[32];
105 uint64_t fpr[32]; /* assume both F and D extensions */
106
107 /* vector coprocessor state. */
108 uint64_t vreg[32 * RV_VLEN_MAX / 64] QEMU_ALIGNED(16);
109 target_ulong vxrm;
110 target_ulong vxsat;
111 target_ulong vl;
112 target_ulong vstart;
113 target_ulong vtype;
114
115 target_ulong pc;
116 target_ulong load_res;
117 target_ulong load_val;
118
119 target_ulong frm;
120
121 target_ulong badaddr;
122 target_ulong guest_phys_fault_addr;
123
124 target_ulong priv_ver;
125 target_ulong vext_ver;
126 target_ulong misa;
127 target_ulong misa_mask;
128
129 uint32_t features;
130
131 #ifdef CONFIG_USER_ONLY
132 uint32_t elf_flags;
133 #endif
134
135 #ifndef CONFIG_USER_ONLY
136 target_ulong priv;
137 /* This contains QEMU specific information about the virt state. */
138 target_ulong virt;
139 target_ulong resetvec;
140
141 target_ulong mhartid;
142 target_ulong mstatus;
143
144 target_ulong mip;
145
146 #ifdef TARGET_RISCV32
147 target_ulong mstatush;
148 #endif
149
150 uint32_t miclaim;
151
152 target_ulong mie;
153 target_ulong mideleg;
154
155 target_ulong sptbr; /* until: priv-1.9.1 */
156 target_ulong satp; /* since: priv-1.10.0 */
157 target_ulong sbadaddr;
158 target_ulong mbadaddr;
159 target_ulong medeleg;
160
161 target_ulong stvec;
162 target_ulong sepc;
163 target_ulong scause;
164
165 target_ulong mtvec;
166 target_ulong mepc;
167 target_ulong mcause;
168 target_ulong mtval; /* since: priv-1.10.0 */
169
170 /* Hypervisor CSRs */
171 target_ulong hstatus;
172 target_ulong hedeleg;
173 target_ulong hideleg;
174 target_ulong hcounteren;
175 target_ulong htval;
176 target_ulong htinst;
177 target_ulong hgatp;
178 uint64_t htimedelta;
179
180 /* Virtual CSRs */
181 target_ulong vsstatus;
182 target_ulong vstvec;
183 target_ulong vsscratch;
184 target_ulong vsepc;
185 target_ulong vscause;
186 target_ulong vstval;
187 target_ulong vsatp;
188 #ifdef TARGET_RISCV32
189 target_ulong vsstatush;
190 #endif
191
192 target_ulong mtval2;
193 target_ulong mtinst;
194
195 /* HS Backup CSRs */
196 target_ulong stvec_hs;
197 target_ulong sscratch_hs;
198 target_ulong sepc_hs;
199 target_ulong scause_hs;
200 target_ulong stval_hs;
201 target_ulong satp_hs;
202 target_ulong mstatus_hs;
203 #ifdef TARGET_RISCV32
204 target_ulong mstatush_hs;
205 #endif
206
207 target_ulong scounteren;
208 target_ulong mcounteren;
209
210 target_ulong sscratch;
211 target_ulong mscratch;
212
213 /* temporary htif regs */
214 uint64_t mfromhost;
215 uint64_t mtohost;
216 uint64_t timecmp;
217
218 /* physical memory protection */
219 pmp_table_t pmp_state;
220
221 /* machine specific rdtime callback */
222 uint64_t (*rdtime_fn)(void);
223
224 /* True if in debugger mode. */
225 bool debugger;
226 #endif
227
228 float_status fp_status;
229
230 /* Fields from here on are preserved across CPU reset. */
231 QEMUTimer *timer; /* Internal timer */
232 };
233
234 #define RISCV_CPU_CLASS(klass) \
235 OBJECT_CLASS_CHECK(RISCVCPUClass, (klass), TYPE_RISCV_CPU)
236 #define RISCV_CPU(obj) \
237 OBJECT_CHECK(RISCVCPU, (obj), TYPE_RISCV_CPU)
238 #define RISCV_CPU_GET_CLASS(obj) \
239 OBJECT_GET_CLASS(RISCVCPUClass, (obj), TYPE_RISCV_CPU)
240
241 /**
242 * RISCVCPUClass:
243 * @parent_realize: The parent class' realize handler.
244 * @parent_reset: The parent class' reset handler.
245 *
246 * A RISCV CPU model.
247 */
248 typedef struct RISCVCPUClass {
249 /*< private >*/
250 CPUClass parent_class;
251 /*< public >*/
252 DeviceRealize parent_realize;
253 DeviceReset parent_reset;
254 } RISCVCPUClass;
255
256 /**
257 * RISCVCPU:
258 * @env: #CPURISCVState
259 *
260 * A RISCV CPU.
261 */
262 typedef struct RISCVCPU {
263 /*< private >*/
264 CPUState parent_obj;
265 /*< public >*/
266 CPUNegativeOffsetState neg;
267 CPURISCVState env;
268
269 /* Configuration Settings */
270 struct {
271 bool ext_i;
272 bool ext_e;
273 bool ext_g;
274 bool ext_m;
275 bool ext_a;
276 bool ext_f;
277 bool ext_d;
278 bool ext_c;
279 bool ext_s;
280 bool ext_u;
281 bool ext_h;
282 bool ext_v;
283 bool ext_counters;
284 bool ext_ifencei;
285 bool ext_icsr;
286
287 char *priv_spec;
288 char *user_spec;
289 char *vext_spec;
290 uint16_t vlen;
291 uint16_t elen;
292 bool mmu;
293 bool pmp;
294 } cfg;
295 } RISCVCPU;
296
297 static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext)
298 {
299 return (env->misa & ext) != 0;
300 }
301
302 static inline bool riscv_feature(CPURISCVState *env, int feature)
303 {
304 return env->features & (1ULL << feature);
305 }
306
307 #include "cpu_user.h"
308 #include "cpu_bits.h"
309
310 extern const char * const riscv_int_regnames[];
311 extern const char * const riscv_fpr_regnames[];
312 extern const char * const riscv_excp_names[];
313 extern const char * const riscv_intr_names[];
314
315 void riscv_cpu_do_interrupt(CPUState *cpu);
316 int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg);
317 int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
318 bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request);
319 bool riscv_cpu_fp_enabled(CPURISCVState *env);
320 bool riscv_cpu_virt_enabled(CPURISCVState *env);
321 void riscv_cpu_set_virt_enabled(CPURISCVState *env, bool enable);
322 bool riscv_cpu_force_hs_excep_enabled(CPURISCVState *env);
323 void riscv_cpu_set_force_hs_excep(CPURISCVState *env, bool enable);
324 bool riscv_cpu_two_stage_lookup(CPURISCVState *env);
325 void riscv_cpu_set_two_stage_lookup(CPURISCVState *env, bool enable);
326 int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch);
327 hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
328 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
329 MMUAccessType access_type, int mmu_idx,
330 uintptr_t retaddr);
331 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
332 MMUAccessType access_type, int mmu_idx,
333 bool probe, uintptr_t retaddr);
334 void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr,
335 vaddr addr, unsigned size,
336 MMUAccessType access_type,
337 int mmu_idx, MemTxAttrs attrs,
338 MemTxResult response, uintptr_t retaddr);
339 char *riscv_isa_string(RISCVCPU *cpu);
340 void riscv_cpu_list(void);
341
342 #define cpu_signal_handler riscv_cpu_signal_handler
343 #define cpu_list riscv_cpu_list
344 #define cpu_mmu_index riscv_cpu_mmu_index
345
346 #ifndef CONFIG_USER_ONLY
347 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
348 int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts);
349 uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
350 #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
351 void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void));
352 #endif
353 void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);
354
355 void riscv_translate_init(void);
356 int riscv_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
357 void QEMU_NORETURN riscv_raise_exception(CPURISCVState *env,
358 uint32_t exception, uintptr_t pc);
359
360 target_ulong riscv_cpu_get_fflags(CPURISCVState *env);
361 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong);
362
363 #define TB_FLAGS_MMU_MASK 3
364 #define TB_FLAGS_MSTATUS_FS MSTATUS_FS
365
366 typedef CPURISCVState CPUArchState;
367 typedef RISCVCPU ArchCPU;
368 #include "exec/cpu-all.h"
369
370 FIELD(TB_FLAGS, VL_EQ_VLMAX, 2, 1)
371 FIELD(TB_FLAGS, LMUL, 3, 2)
372 FIELD(TB_FLAGS, SEW, 5, 3)
373 FIELD(TB_FLAGS, VILL, 8, 1)
374
375 /*
376 * A simplification for VLMAX
377 * = (1 << LMUL) * VLEN / (8 * (1 << SEW))
378 * = (VLEN << LMUL) / (8 << SEW)
379 * = (VLEN << LMUL) >> (SEW + 3)
380 * = VLEN >> (SEW + 3 - LMUL)
381 */
382 static inline uint32_t vext_get_vlmax(RISCVCPU *cpu, target_ulong vtype)
383 {
384 uint8_t sew, lmul;
385
386 sew = FIELD_EX64(vtype, VTYPE, VSEW);
387 lmul = FIELD_EX64(vtype, VTYPE, VLMUL);
388 return cpu->cfg.vlen >> (sew + 3 - lmul);
389 }
390
391 static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc,
392 target_ulong *cs_base, uint32_t *pflags)
393 {
394 uint32_t flags = 0;
395
396 *pc = env->pc;
397 *cs_base = 0;
398
399 if (riscv_has_ext(env, RVV)) {
400 uint32_t vlmax = vext_get_vlmax(env_archcpu(env), env->vtype);
401 bool vl_eq_vlmax = (env->vstart == 0) && (vlmax == env->vl);
402 flags = FIELD_DP32(flags, TB_FLAGS, VILL,
403 FIELD_EX64(env->vtype, VTYPE, VILL));
404 flags = FIELD_DP32(flags, TB_FLAGS, SEW,
405 FIELD_EX64(env->vtype, VTYPE, VSEW));
406 flags = FIELD_DP32(flags, TB_FLAGS, LMUL,
407 FIELD_EX64(env->vtype, VTYPE, VLMUL));
408 flags = FIELD_DP32(flags, TB_FLAGS, VL_EQ_VLMAX, vl_eq_vlmax);
409 } else {
410 flags = FIELD_DP32(flags, TB_FLAGS, VILL, 1);
411 }
412
413 #ifdef CONFIG_USER_ONLY
414 flags |= TB_FLAGS_MSTATUS_FS;
415 #else
416 flags |= cpu_mmu_index(env, 0);
417 if (riscv_cpu_fp_enabled(env)) {
418 flags |= env->mstatus & MSTATUS_FS;
419 }
420 #endif
421 *pflags = flags;
422 }
423
424 int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
425 target_ulong new_value, target_ulong write_mask);
426 int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value,
427 target_ulong new_value, target_ulong write_mask);
428
429 static inline void riscv_csr_write(CPURISCVState *env, int csrno,
430 target_ulong val)
431 {
432 riscv_csrrw(env, csrno, NULL, val, MAKE_64BIT_MASK(0, TARGET_LONG_BITS));
433 }
434
435 static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno)
436 {
437 target_ulong val = 0;
438 riscv_csrrw(env, csrno, &val, 0, 0);
439 return val;
440 }
441
442 typedef int (*riscv_csr_predicate_fn)(CPURISCVState *env, int csrno);
443 typedef int (*riscv_csr_read_fn)(CPURISCVState *env, int csrno,
444 target_ulong *ret_value);
445 typedef int (*riscv_csr_write_fn)(CPURISCVState *env, int csrno,
446 target_ulong new_value);
447 typedef int (*riscv_csr_op_fn)(CPURISCVState *env, int csrno,
448 target_ulong *ret_value, target_ulong new_value, target_ulong write_mask);
449
450 typedef struct {
451 riscv_csr_predicate_fn predicate;
452 riscv_csr_read_fn read;
453 riscv_csr_write_fn write;
454 riscv_csr_op_fn op;
455 } riscv_csr_operations;
456
457 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
458 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
459
460 void riscv_cpu_register_gdb_regs_for_features(CPUState *cs);
461
462 #endif /* RISCV_CPU_H */