linux-user, scripts: add a script to update syscall.tbl
[qemu.git] / target / riscv / cpu_bits.h
1 /* RISC-V ISA constants */
2
3 #ifndef TARGET_RISCV_CPU_BITS_H
4 #define TARGET_RISCV_CPU_BITS_H
5
6 #define get_field(reg, mask) (((reg) & \
7 (target_ulong)(mask)) / ((mask) & ~((mask) << 1)))
8 #define set_field(reg, mask, val) (((reg) & ~(target_ulong)(mask)) | \
9 (((target_ulong)(val) * ((mask) & ~((mask) << 1))) & \
10 (target_ulong)(mask)))
11
12 /* Floating point round mode */
13 #define FSR_RD_SHIFT 5
14 #define FSR_RD (0x7 << FSR_RD_SHIFT)
15
16 /* Floating point accrued exception flags */
17 #define FPEXC_NX 0x01
18 #define FPEXC_UF 0x02
19 #define FPEXC_OF 0x04
20 #define FPEXC_DZ 0x08
21 #define FPEXC_NV 0x10
22
23 /* Floating point status register bits */
24 #define FSR_AEXC_SHIFT 0
25 #define FSR_NVA (FPEXC_NV << FSR_AEXC_SHIFT)
26 #define FSR_OFA (FPEXC_OF << FSR_AEXC_SHIFT)
27 #define FSR_UFA (FPEXC_UF << FSR_AEXC_SHIFT)
28 #define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT)
29 #define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT)
30 #define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
31
32 /* Control and Status Registers */
33
34 /* User Trap Setup */
35 #define CSR_USTATUS 0x000
36 #define CSR_UIE 0x004
37 #define CSR_UTVEC 0x005
38
39 /* User Trap Handling */
40 #define CSR_USCRATCH 0x040
41 #define CSR_UEPC 0x041
42 #define CSR_UCAUSE 0x042
43 #define CSR_UTVAL 0x043
44 #define CSR_UIP 0x044
45
46 /* User Floating-Point CSRs */
47 #define CSR_FFLAGS 0x001
48 #define CSR_FRM 0x002
49 #define CSR_FCSR 0x003
50
51 /* User Timers and Counters */
52 #define CSR_CYCLE 0xc00
53 #define CSR_TIME 0xc01
54 #define CSR_INSTRET 0xc02
55 #define CSR_HPMCOUNTER3 0xc03
56 #define CSR_HPMCOUNTER4 0xc04
57 #define CSR_HPMCOUNTER5 0xc05
58 #define CSR_HPMCOUNTER6 0xc06
59 #define CSR_HPMCOUNTER7 0xc07
60 #define CSR_HPMCOUNTER8 0xc08
61 #define CSR_HPMCOUNTER9 0xc09
62 #define CSR_HPMCOUNTER10 0xc0a
63 #define CSR_HPMCOUNTER11 0xc0b
64 #define CSR_HPMCOUNTER12 0xc0c
65 #define CSR_HPMCOUNTER13 0xc0d
66 #define CSR_HPMCOUNTER14 0xc0e
67 #define CSR_HPMCOUNTER15 0xc0f
68 #define CSR_HPMCOUNTER16 0xc10
69 #define CSR_HPMCOUNTER17 0xc11
70 #define CSR_HPMCOUNTER18 0xc12
71 #define CSR_HPMCOUNTER19 0xc13
72 #define CSR_HPMCOUNTER20 0xc14
73 #define CSR_HPMCOUNTER21 0xc15
74 #define CSR_HPMCOUNTER22 0xc16
75 #define CSR_HPMCOUNTER23 0xc17
76 #define CSR_HPMCOUNTER24 0xc18
77 #define CSR_HPMCOUNTER25 0xc19
78 #define CSR_HPMCOUNTER26 0xc1a
79 #define CSR_HPMCOUNTER27 0xc1b
80 #define CSR_HPMCOUNTER28 0xc1c
81 #define CSR_HPMCOUNTER29 0xc1d
82 #define CSR_HPMCOUNTER30 0xc1e
83 #define CSR_HPMCOUNTER31 0xc1f
84 #define CSR_CYCLEH 0xc80
85 #define CSR_TIMEH 0xc81
86 #define CSR_INSTRETH 0xc82
87 #define CSR_HPMCOUNTER3H 0xc83
88 #define CSR_HPMCOUNTER4H 0xc84
89 #define CSR_HPMCOUNTER5H 0xc85
90 #define CSR_HPMCOUNTER6H 0xc86
91 #define CSR_HPMCOUNTER7H 0xc87
92 #define CSR_HPMCOUNTER8H 0xc88
93 #define CSR_HPMCOUNTER9H 0xc89
94 #define CSR_HPMCOUNTER10H 0xc8a
95 #define CSR_HPMCOUNTER11H 0xc8b
96 #define CSR_HPMCOUNTER12H 0xc8c
97 #define CSR_HPMCOUNTER13H 0xc8d
98 #define CSR_HPMCOUNTER14H 0xc8e
99 #define CSR_HPMCOUNTER15H 0xc8f
100 #define CSR_HPMCOUNTER16H 0xc90
101 #define CSR_HPMCOUNTER17H 0xc91
102 #define CSR_HPMCOUNTER18H 0xc92
103 #define CSR_HPMCOUNTER19H 0xc93
104 #define CSR_HPMCOUNTER20H 0xc94
105 #define CSR_HPMCOUNTER21H 0xc95
106 #define CSR_HPMCOUNTER22H 0xc96
107 #define CSR_HPMCOUNTER23H 0xc97
108 #define CSR_HPMCOUNTER24H 0xc98
109 #define CSR_HPMCOUNTER25H 0xc99
110 #define CSR_HPMCOUNTER26H 0xc9a
111 #define CSR_HPMCOUNTER27H 0xc9b
112 #define CSR_HPMCOUNTER28H 0xc9c
113 #define CSR_HPMCOUNTER29H 0xc9d
114 #define CSR_HPMCOUNTER30H 0xc9e
115 #define CSR_HPMCOUNTER31H 0xc9f
116
117 /* Machine Timers and Counters */
118 #define CSR_MCYCLE 0xb00
119 #define CSR_MINSTRET 0xb02
120 #define CSR_MCYCLEH 0xb80
121 #define CSR_MINSTRETH 0xb82
122
123 /* Machine Information Registers */
124 #define CSR_MVENDORID 0xf11
125 #define CSR_MARCHID 0xf12
126 #define CSR_MIMPID 0xf13
127 #define CSR_MHARTID 0xf14
128
129 /* Machine Trap Setup */
130 #define CSR_MSTATUS 0x300
131 #define CSR_MISA 0x301
132 #define CSR_MEDELEG 0x302
133 #define CSR_MIDELEG 0x303
134 #define CSR_MIE 0x304
135 #define CSR_MTVEC 0x305
136 #define CSR_MCOUNTEREN 0x306
137
138 /* 32-bit only */
139 #define CSR_MSTATUSH 0x310
140
141 /* Legacy Counter Setup (priv v1.9.1) */
142 /* Update to #define CSR_MCOUNTINHIBIT 0x320 for 1.11.0 */
143 #define CSR_MUCOUNTEREN 0x320
144 #define CSR_MSCOUNTEREN 0x321
145 #define CSR_MHCOUNTEREN 0x322
146
147 /* Machine Trap Handling */
148 #define CSR_MSCRATCH 0x340
149 #define CSR_MEPC 0x341
150 #define CSR_MCAUSE 0x342
151 #define CSR_MTVAL 0x343
152 #define CSR_MIP 0x344
153
154 /* Legacy Machine Trap Handling (priv v1.9.1) */
155 #define CSR_MBADADDR 0x343
156
157 /* Supervisor Trap Setup */
158 #define CSR_SSTATUS 0x100
159 #define CSR_SEDELEG 0x102
160 #define CSR_SIDELEG 0x103
161 #define CSR_SIE 0x104
162 #define CSR_STVEC 0x105
163 #define CSR_SCOUNTEREN 0x106
164
165 /* Supervisor Trap Handling */
166 #define CSR_SSCRATCH 0x140
167 #define CSR_SEPC 0x141
168 #define CSR_SCAUSE 0x142
169 #define CSR_STVAL 0x143
170 #define CSR_SIP 0x144
171
172 /* Legacy Supervisor Trap Handling (priv v1.9.1) */
173 #define CSR_SBADADDR 0x143
174
175 /* Supervisor Protection and Translation */
176 #define CSR_SPTBR 0x180
177 #define CSR_SATP 0x180
178
179 /* Hpervisor CSRs */
180 #define CSR_HSTATUS 0x600
181 #define CSR_HEDELEG 0x602
182 #define CSR_HIDELEG 0x603
183 #define CSR_HIE 0x604
184 #define CSR_HCOUNTEREN 0x606
185 #define CSR_HTVAL 0x643
186 #define CSR_HIP 0x644
187 #define CSR_HTINST 0x64A
188 #define CSR_HGATP 0x680
189 #define CSR_HTIMEDELTA 0x605
190 #define CSR_HTIMEDELTAH 0x615
191
192 #if defined(TARGET_RISCV32)
193 #define HGATP_MODE SATP32_MODE
194 #define HGATP_VMID SATP32_ASID
195 #define HGATP_PPN SATP32_PPN
196 #endif
197 #if defined(TARGET_RISCV64)
198 #define HGATP_MODE SATP64_MODE
199 #define HGATP_VMID SATP64_ASID
200 #define HGATP_PPN SATP64_PPN
201 #endif
202
203 /* Virtual CSRs */
204 #define CSR_VSSTATUS 0x200
205 #define CSR_VSIE 0x204
206 #define CSR_VSTVEC 0x205
207 #define CSR_VSSCRATCH 0x240
208 #define CSR_VSEPC 0x241
209 #define CSR_VSCAUSE 0x242
210 #define CSR_VSTVAL 0x243
211 #define CSR_VSIP 0x244
212 #define CSR_VSATP 0x280
213
214 #define CSR_MTINST 0x34a
215 #define CSR_MTVAL2 0x34b
216
217 /* Physical Memory Protection */
218 #define CSR_PMPCFG0 0x3a0
219 #define CSR_PMPCFG1 0x3a1
220 #define CSR_PMPCFG2 0x3a2
221 #define CSR_PMPCFG3 0x3a3
222 #define CSR_PMPADDR0 0x3b0
223 #define CSR_PMPADDR1 0x3b1
224 #define CSR_PMPADDR2 0x3b2
225 #define CSR_PMPADDR3 0x3b3
226 #define CSR_PMPADDR4 0x3b4
227 #define CSR_PMPADDR5 0x3b5
228 #define CSR_PMPADDR6 0x3b6
229 #define CSR_PMPADDR7 0x3b7
230 #define CSR_PMPADDR8 0x3b8
231 #define CSR_PMPADDR9 0x3b9
232 #define CSR_PMPADDR10 0x3ba
233 #define CSR_PMPADDR11 0x3bb
234 #define CSR_PMPADDR12 0x3bc
235 #define CSR_PMPADDR13 0x3bd
236 #define CSR_PMPADDR14 0x3be
237 #define CSR_PMPADDR15 0x3bf
238
239 /* Debug/Trace Registers (shared with Debug Mode) */
240 #define CSR_TSELECT 0x7a0
241 #define CSR_TDATA1 0x7a1
242 #define CSR_TDATA2 0x7a2
243 #define CSR_TDATA3 0x7a3
244
245 /* Debug Mode Registers */
246 #define CSR_DCSR 0x7b0
247 #define CSR_DPC 0x7b1
248 #define CSR_DSCRATCH 0x7b2
249
250 /* Performance Counters */
251 #define CSR_MHPMCOUNTER3 0xb03
252 #define CSR_MHPMCOUNTER4 0xb04
253 #define CSR_MHPMCOUNTER5 0xb05
254 #define CSR_MHPMCOUNTER6 0xb06
255 #define CSR_MHPMCOUNTER7 0xb07
256 #define CSR_MHPMCOUNTER8 0xb08
257 #define CSR_MHPMCOUNTER9 0xb09
258 #define CSR_MHPMCOUNTER10 0xb0a
259 #define CSR_MHPMCOUNTER11 0xb0b
260 #define CSR_MHPMCOUNTER12 0xb0c
261 #define CSR_MHPMCOUNTER13 0xb0d
262 #define CSR_MHPMCOUNTER14 0xb0e
263 #define CSR_MHPMCOUNTER15 0xb0f
264 #define CSR_MHPMCOUNTER16 0xb10
265 #define CSR_MHPMCOUNTER17 0xb11
266 #define CSR_MHPMCOUNTER18 0xb12
267 #define CSR_MHPMCOUNTER19 0xb13
268 #define CSR_MHPMCOUNTER20 0xb14
269 #define CSR_MHPMCOUNTER21 0xb15
270 #define CSR_MHPMCOUNTER22 0xb16
271 #define CSR_MHPMCOUNTER23 0xb17
272 #define CSR_MHPMCOUNTER24 0xb18
273 #define CSR_MHPMCOUNTER25 0xb19
274 #define CSR_MHPMCOUNTER26 0xb1a
275 #define CSR_MHPMCOUNTER27 0xb1b
276 #define CSR_MHPMCOUNTER28 0xb1c
277 #define CSR_MHPMCOUNTER29 0xb1d
278 #define CSR_MHPMCOUNTER30 0xb1e
279 #define CSR_MHPMCOUNTER31 0xb1f
280 #define CSR_MHPMEVENT3 0x323
281 #define CSR_MHPMEVENT4 0x324
282 #define CSR_MHPMEVENT5 0x325
283 #define CSR_MHPMEVENT6 0x326
284 #define CSR_MHPMEVENT7 0x327
285 #define CSR_MHPMEVENT8 0x328
286 #define CSR_MHPMEVENT9 0x329
287 #define CSR_MHPMEVENT10 0x32a
288 #define CSR_MHPMEVENT11 0x32b
289 #define CSR_MHPMEVENT12 0x32c
290 #define CSR_MHPMEVENT13 0x32d
291 #define CSR_MHPMEVENT14 0x32e
292 #define CSR_MHPMEVENT15 0x32f
293 #define CSR_MHPMEVENT16 0x330
294 #define CSR_MHPMEVENT17 0x331
295 #define CSR_MHPMEVENT18 0x332
296 #define CSR_MHPMEVENT19 0x333
297 #define CSR_MHPMEVENT20 0x334
298 #define CSR_MHPMEVENT21 0x335
299 #define CSR_MHPMEVENT22 0x336
300 #define CSR_MHPMEVENT23 0x337
301 #define CSR_MHPMEVENT24 0x338
302 #define CSR_MHPMEVENT25 0x339
303 #define CSR_MHPMEVENT26 0x33a
304 #define CSR_MHPMEVENT27 0x33b
305 #define CSR_MHPMEVENT28 0x33c
306 #define CSR_MHPMEVENT29 0x33d
307 #define CSR_MHPMEVENT30 0x33e
308 #define CSR_MHPMEVENT31 0x33f
309 #define CSR_MHPMCOUNTER3H 0xb83
310 #define CSR_MHPMCOUNTER4H 0xb84
311 #define CSR_MHPMCOUNTER5H 0xb85
312 #define CSR_MHPMCOUNTER6H 0xb86
313 #define CSR_MHPMCOUNTER7H 0xb87
314 #define CSR_MHPMCOUNTER8H 0xb88
315 #define CSR_MHPMCOUNTER9H 0xb89
316 #define CSR_MHPMCOUNTER10H 0xb8a
317 #define CSR_MHPMCOUNTER11H 0xb8b
318 #define CSR_MHPMCOUNTER12H 0xb8c
319 #define CSR_MHPMCOUNTER13H 0xb8d
320 #define CSR_MHPMCOUNTER14H 0xb8e
321 #define CSR_MHPMCOUNTER15H 0xb8f
322 #define CSR_MHPMCOUNTER16H 0xb90
323 #define CSR_MHPMCOUNTER17H 0xb91
324 #define CSR_MHPMCOUNTER18H 0xb92
325 #define CSR_MHPMCOUNTER19H 0xb93
326 #define CSR_MHPMCOUNTER20H 0xb94
327 #define CSR_MHPMCOUNTER21H 0xb95
328 #define CSR_MHPMCOUNTER22H 0xb96
329 #define CSR_MHPMCOUNTER23H 0xb97
330 #define CSR_MHPMCOUNTER24H 0xb98
331 #define CSR_MHPMCOUNTER25H 0xb99
332 #define CSR_MHPMCOUNTER26H 0xb9a
333 #define CSR_MHPMCOUNTER27H 0xb9b
334 #define CSR_MHPMCOUNTER28H 0xb9c
335 #define CSR_MHPMCOUNTER29H 0xb9d
336 #define CSR_MHPMCOUNTER30H 0xb9e
337 #define CSR_MHPMCOUNTER31H 0xb9f
338
339 /* Legacy Machine Protection and Translation (priv v1.9.1) */
340 #define CSR_MBASE 0x380
341 #define CSR_MBOUND 0x381
342 #define CSR_MIBASE 0x382
343 #define CSR_MIBOUND 0x383
344 #define CSR_MDBASE 0x384
345 #define CSR_MDBOUND 0x385
346
347 /* mstatus CSR bits */
348 #define MSTATUS_UIE 0x00000001
349 #define MSTATUS_SIE 0x00000002
350 #define MSTATUS_MIE 0x00000008
351 #define MSTATUS_UPIE 0x00000010
352 #define MSTATUS_SPIE 0x00000020
353 #define MSTATUS_MPIE 0x00000080
354 #define MSTATUS_SPP 0x00000100
355 #define MSTATUS_MPP 0x00001800
356 #define MSTATUS_FS 0x00006000
357 #define MSTATUS_XS 0x00018000
358 #define MSTATUS_MPRV 0x00020000
359 #define MSTATUS_PUM 0x00040000 /* until: priv-1.9.1 */
360 #define MSTATUS_SUM 0x00040000 /* since: priv-1.10 */
361 #define MSTATUS_MXR 0x00080000
362 #define MSTATUS_VM 0x1F000000 /* until: priv-1.9.1 */
363 #define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */
364 #define MSTATUS_TW 0x20000000 /* since: priv-1.10 */
365 #define MSTATUS_TSR 0x40000000 /* since: priv-1.10 */
366 #if defined(TARGET_RISCV64)
367 #define MSTATUS_MTL 0x4000000000ULL
368 #define MSTATUS_MPV 0x8000000000ULL
369 #elif defined(TARGET_RISCV32)
370 #define MSTATUS_MTL 0x00000040
371 #define MSTATUS_MPV 0x00000080
372 #endif
373
374 #ifdef TARGET_RISCV32
375 # define MSTATUS_MPV_ISSET(env) get_field(env->mstatush, MSTATUS_MPV)
376 #else
377 # define MSTATUS_MPV_ISSET(env) get_field(env->mstatus, MSTATUS_MPV)
378 #endif
379
380 #define MSTATUS64_UXL 0x0000000300000000ULL
381 #define MSTATUS64_SXL 0x0000000C00000000ULL
382
383 #define MSTATUS32_SD 0x80000000
384 #define MSTATUS64_SD 0x8000000000000000ULL
385
386 #define MISA32_MXL 0xC0000000
387 #define MISA64_MXL 0xC000000000000000ULL
388
389 #define MXL_RV32 1
390 #define MXL_RV64 2
391 #define MXL_RV128 3
392
393 #if defined(TARGET_RISCV32)
394 #define MSTATUS_SD MSTATUS32_SD
395 #define MISA_MXL MISA32_MXL
396 #define MXL_VAL MXL_RV32
397 #elif defined(TARGET_RISCV64)
398 #define MSTATUS_SD MSTATUS64_SD
399 #define MISA_MXL MISA64_MXL
400 #define MXL_VAL MXL_RV64
401 #endif
402
403 /* sstatus CSR bits */
404 #define SSTATUS_UIE 0x00000001
405 #define SSTATUS_SIE 0x00000002
406 #define SSTATUS_UPIE 0x00000010
407 #define SSTATUS_SPIE 0x00000020
408 #define SSTATUS_SPP 0x00000100
409 #define SSTATUS_FS 0x00006000
410 #define SSTATUS_XS 0x00018000
411 #define SSTATUS_PUM 0x00040000 /* until: priv-1.9.1 */
412 #define SSTATUS_SUM 0x00040000 /* since: priv-1.10 */
413 #define SSTATUS_MXR 0x00080000
414
415 #define SSTATUS32_SD 0x80000000
416 #define SSTATUS64_SD 0x8000000000000000ULL
417
418 #if defined(TARGET_RISCV32)
419 #define SSTATUS_SD SSTATUS32_SD
420 #elif defined(TARGET_RISCV64)
421 #define SSTATUS_SD SSTATUS64_SD
422 #endif
423
424 /* hstatus CSR bits */
425 #define HSTATUS_SPRV 0x00000001
426 #define HSTATUS_SPV 0x00000080
427 #define HSTATUS_SP2P 0x00000100
428 #define HSTATUS_SP2V 0x00000200
429 #define HSTATUS_VTVM 0x00100000
430 #define HSTATUS_VTSR 0x00400000
431
432 #define HSTATUS32_WPRI 0xFF8FF87E
433 #define HSTATUS64_WPRI 0xFFFFFFFFFF8FF87EULL
434
435 #if defined(TARGET_RISCV32)
436 #define HSTATUS_WPRI HSTATUS32_WPRI
437 #elif defined(TARGET_RISCV64)
438 #define HSTATUS_WPRI HSTATUS64_WPRI
439 #endif
440
441 /* Privilege modes */
442 #define PRV_U 0
443 #define PRV_S 1
444 #define PRV_H 2 /* Reserved */
445 #define PRV_M 3
446
447 /* Virtulisation Register Fields */
448 #define VIRT_ONOFF 1
449 /* This is used to save state for when we take an exception. If this is set
450 * that means that we want to force a HS level exception (no matter what the
451 * delegation is set to). This will occur for things such as a second level
452 * page table fault.
453 */
454 #define FORCE_HS_EXCEP 2
455
456 /* RV32 satp CSR field masks */
457 #define SATP32_MODE 0x80000000
458 #define SATP32_ASID 0x7fc00000
459 #define SATP32_PPN 0x003fffff
460
461 /* RV64 satp CSR field masks */
462 #define SATP64_MODE 0xF000000000000000ULL
463 #define SATP64_ASID 0x0FFFF00000000000ULL
464 #define SATP64_PPN 0x00000FFFFFFFFFFFULL
465
466 #if defined(TARGET_RISCV32)
467 #define SATP_MODE SATP32_MODE
468 #define SATP_ASID SATP32_ASID
469 #define SATP_PPN SATP32_PPN
470 #endif
471 #if defined(TARGET_RISCV64)
472 #define SATP_MODE SATP64_MODE
473 #define SATP_ASID SATP64_ASID
474 #define SATP_PPN SATP64_PPN
475 #endif
476
477 /* VM modes (mstatus.vm) privileged ISA 1.9.1 */
478 #define VM_1_09_MBARE 0
479 #define VM_1_09_MBB 1
480 #define VM_1_09_MBBID 2
481 #define VM_1_09_SV32 8
482 #define VM_1_09_SV39 9
483 #define VM_1_09_SV48 10
484
485 /* VM modes (satp.mode) privileged ISA 1.10 */
486 #define VM_1_10_MBARE 0
487 #define VM_1_10_SV32 1
488 #define VM_1_10_SV39 8
489 #define VM_1_10_SV48 9
490 #define VM_1_10_SV57 10
491 #define VM_1_10_SV64 11
492
493 /* Page table entry (PTE) fields */
494 #define PTE_V 0x001 /* Valid */
495 #define PTE_R 0x002 /* Read */
496 #define PTE_W 0x004 /* Write */
497 #define PTE_X 0x008 /* Execute */
498 #define PTE_U 0x010 /* User */
499 #define PTE_G 0x020 /* Global */
500 #define PTE_A 0x040 /* Accessed */
501 #define PTE_D 0x080 /* Dirty */
502 #define PTE_SOFT 0x300 /* Reserved for Software */
503
504 /* Page table PPN shift amount */
505 #define PTE_PPN_SHIFT 10
506
507 /* Leaf page shift amount */
508 #define PGSHIFT 12
509
510 /* Default Reset Vector adress */
511 #define DEFAULT_RSTVEC 0x1000
512
513 /* Exception causes */
514 #define EXCP_NONE -1 /* sentinel value */
515 #define RISCV_EXCP_INST_ADDR_MIS 0x0
516 #define RISCV_EXCP_INST_ACCESS_FAULT 0x1
517 #define RISCV_EXCP_ILLEGAL_INST 0x2
518 #define RISCV_EXCP_BREAKPOINT 0x3
519 #define RISCV_EXCP_LOAD_ADDR_MIS 0x4
520 #define RISCV_EXCP_LOAD_ACCESS_FAULT 0x5
521 #define RISCV_EXCP_STORE_AMO_ADDR_MIS 0x6
522 #define RISCV_EXCP_STORE_AMO_ACCESS_FAULT 0x7
523 #define RISCV_EXCP_U_ECALL 0x8
524 #define RISCV_EXCP_S_ECALL 0x9
525 #define RISCV_EXCP_VS_ECALL 0xa
526 #define RISCV_EXCP_M_ECALL 0xb
527 #define RISCV_EXCP_INST_PAGE_FAULT 0xc /* since: priv-1.10.0 */
528 #define RISCV_EXCP_LOAD_PAGE_FAULT 0xd /* since: priv-1.10.0 */
529 #define RISCV_EXCP_STORE_PAGE_FAULT 0xf /* since: priv-1.10.0 */
530 #define RISCV_EXCP_INST_GUEST_PAGE_FAULT 0x14
531 #define RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT 0x15
532 #define RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT 0x17
533
534 #define RISCV_EXCP_INT_FLAG 0x80000000
535 #define RISCV_EXCP_INT_MASK 0x7fffffff
536
537 /* Interrupt causes */
538 #define IRQ_U_SOFT 0
539 #define IRQ_S_SOFT 1
540 #define IRQ_VS_SOFT 2
541 #define IRQ_M_SOFT 3
542 #define IRQ_U_TIMER 4
543 #define IRQ_S_TIMER 5
544 #define IRQ_VS_TIMER 6
545 #define IRQ_M_TIMER 7
546 #define IRQ_U_EXT 8
547 #define IRQ_S_EXT 9
548 #define IRQ_VS_EXT 10
549 #define IRQ_M_EXT 11
550
551 /* mip masks */
552 #define MIP_USIP (1 << IRQ_U_SOFT)
553 #define MIP_SSIP (1 << IRQ_S_SOFT)
554 #define MIP_VSSIP (1 << IRQ_VS_SOFT)
555 #define MIP_MSIP (1 << IRQ_M_SOFT)
556 #define MIP_UTIP (1 << IRQ_U_TIMER)
557 #define MIP_STIP (1 << IRQ_S_TIMER)
558 #define MIP_VSTIP (1 << IRQ_VS_TIMER)
559 #define MIP_MTIP (1 << IRQ_M_TIMER)
560 #define MIP_UEIP (1 << IRQ_U_EXT)
561 #define MIP_SEIP (1 << IRQ_S_EXT)
562 #define MIP_VSEIP (1 << IRQ_VS_EXT)
563 #define MIP_MEIP (1 << IRQ_M_EXT)
564
565 /* sip masks */
566 #define SIP_SSIP MIP_SSIP
567 #define SIP_STIP MIP_STIP
568 #define SIP_SEIP MIP_SEIP
569
570 /* MIE masks */
571 #define MIE_SEIE (1 << IRQ_S_EXT)
572 #define MIE_UEIE (1 << IRQ_U_EXT)
573 #define MIE_STIE (1 << IRQ_S_TIMER)
574 #define MIE_UTIE (1 << IRQ_U_TIMER)
575 #define MIE_SSIE (1 << IRQ_S_SOFT)
576 #define MIE_USIE (1 << IRQ_U_SOFT)
577 #endif