linux-user, scripts: add a script to update syscall.tbl
[qemu.git] / target / riscv / csr.c
1 /*
2 * RISC-V Control and Status Registers.
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 * Copyright (c) 2017-2018 SiFive, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2 or later, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #include "qemu/osdep.h"
21 #include "qemu/log.h"
22 #include "cpu.h"
23 #include "qemu/main-loop.h"
24 #include "exec/exec-all.h"
25
26 /* CSR function table */
27 static riscv_csr_operations csr_ops[];
28
29 /* CSR function table constants */
30 enum {
31 CSR_TABLE_SIZE = 0x1000
32 };
33
34 /* CSR function table public API */
35 void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops)
36 {
37 *ops = csr_ops[csrno & (CSR_TABLE_SIZE - 1)];
38 }
39
40 void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
41 {
42 csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops;
43 }
44
45 /* Predicates */
46 static int fs(CPURISCVState *env, int csrno)
47 {
48 #if !defined(CONFIG_USER_ONLY)
49 if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
50 return -1;
51 }
52 #endif
53 return 0;
54 }
55
56 static int ctr(CPURISCVState *env, int csrno)
57 {
58 #if !defined(CONFIG_USER_ONLY)
59 CPUState *cs = env_cpu(env);
60 RISCVCPU *cpu = RISCV_CPU(cs);
61 uint32_t ctr_en = ~0u;
62
63 if (!cpu->cfg.ext_counters) {
64 /* The Counters extensions is not enabled */
65 return -1;
66 }
67
68 /*
69 * The counters are always enabled at run time on newer priv specs, as the
70 * CSR has changed from controlling that the counters can be read to
71 * controlling that the counters increment.
72 */
73 if (env->priv_ver > PRIV_VERSION_1_09_1) {
74 return 0;
75 }
76
77 if (env->priv < PRV_M) {
78 ctr_en &= env->mcounteren;
79 }
80 if (env->priv < PRV_S) {
81 ctr_en &= env->scounteren;
82 }
83 if (!(ctr_en & (1u << (csrno & 31)))) {
84 return -1;
85 }
86 #endif
87 return 0;
88 }
89
90 #if !defined(CONFIG_USER_ONLY)
91 static int any(CPURISCVState *env, int csrno)
92 {
93 return 0;
94 }
95
96 static int smode(CPURISCVState *env, int csrno)
97 {
98 return -!riscv_has_ext(env, RVS);
99 }
100
101 static int hmode(CPURISCVState *env, int csrno)
102 {
103 if (riscv_has_ext(env, RVS) &&
104 riscv_has_ext(env, RVH)) {
105 /* Hypervisor extension is supported */
106 if ((env->priv == PRV_S && !riscv_cpu_virt_enabled(env)) ||
107 env->priv == PRV_M) {
108 return 0;
109 }
110 }
111
112 return -1;
113 }
114
115 static int pmp(CPURISCVState *env, int csrno)
116 {
117 return -!riscv_feature(env, RISCV_FEATURE_PMP);
118 }
119 #endif
120
121 /* User Floating-Point CSRs */
122 static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val)
123 {
124 #if !defined(CONFIG_USER_ONLY)
125 if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
126 return -1;
127 }
128 #endif
129 *val = riscv_cpu_get_fflags(env);
130 return 0;
131 }
132
133 static int write_fflags(CPURISCVState *env, int csrno, target_ulong val)
134 {
135 #if !defined(CONFIG_USER_ONLY)
136 if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
137 return -1;
138 }
139 env->mstatus |= MSTATUS_FS;
140 #endif
141 riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT));
142 return 0;
143 }
144
145 static int read_frm(CPURISCVState *env, int csrno, target_ulong *val)
146 {
147 #if !defined(CONFIG_USER_ONLY)
148 if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
149 return -1;
150 }
151 #endif
152 *val = env->frm;
153 return 0;
154 }
155
156 static int write_frm(CPURISCVState *env, int csrno, target_ulong val)
157 {
158 #if !defined(CONFIG_USER_ONLY)
159 if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
160 return -1;
161 }
162 env->mstatus |= MSTATUS_FS;
163 #endif
164 env->frm = val & (FSR_RD >> FSR_RD_SHIFT);
165 return 0;
166 }
167
168 static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val)
169 {
170 #if !defined(CONFIG_USER_ONLY)
171 if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
172 return -1;
173 }
174 #endif
175 *val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
176 | (env->frm << FSR_RD_SHIFT);
177 return 0;
178 }
179
180 static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val)
181 {
182 #if !defined(CONFIG_USER_ONLY)
183 if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
184 return -1;
185 }
186 env->mstatus |= MSTATUS_FS;
187 #endif
188 env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
189 riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
190 return 0;
191 }
192
193 /* User Timers and Counters */
194 static int read_instret(CPURISCVState *env, int csrno, target_ulong *val)
195 {
196 #if !defined(CONFIG_USER_ONLY)
197 if (use_icount) {
198 *val = cpu_get_icount();
199 } else {
200 *val = cpu_get_host_ticks();
201 }
202 #else
203 *val = cpu_get_host_ticks();
204 #endif
205 return 0;
206 }
207
208 #if defined(TARGET_RISCV32)
209 static int read_instreth(CPURISCVState *env, int csrno, target_ulong *val)
210 {
211 #if !defined(CONFIG_USER_ONLY)
212 if (use_icount) {
213 *val = cpu_get_icount() >> 32;
214 } else {
215 *val = cpu_get_host_ticks() >> 32;
216 }
217 #else
218 *val = cpu_get_host_ticks() >> 32;
219 #endif
220 return 0;
221 }
222 #endif /* TARGET_RISCV32 */
223
224 #if defined(CONFIG_USER_ONLY)
225 static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
226 {
227 *val = cpu_get_host_ticks();
228 return 0;
229 }
230
231 #if defined(TARGET_RISCV32)
232 static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
233 {
234 *val = cpu_get_host_ticks() >> 32;
235 return 0;
236 }
237 #endif
238
239 #else /* CONFIG_USER_ONLY */
240
241 static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
242 {
243 uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
244
245 if (!env->rdtime_fn) {
246 return -1;
247 }
248
249 *val = env->rdtime_fn() + delta;
250 return 0;
251 }
252
253 #if defined(TARGET_RISCV32)
254 static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
255 {
256 uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
257
258 if (!env->rdtime_fn) {
259 return -1;
260 }
261
262 *val = (env->rdtime_fn() + delta) >> 32;
263 return 0;
264 }
265 #endif
266
267 /* Machine constants */
268
269 #define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP)
270 #define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP)
271 #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP)
272
273 static const target_ulong delegable_ints = S_MODE_INTERRUPTS |
274 VS_MODE_INTERRUPTS;
275 static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS |
276 VS_MODE_INTERRUPTS;
277 static const target_ulong delegable_excps =
278 (1ULL << (RISCV_EXCP_INST_ADDR_MIS)) |
279 (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) |
280 (1ULL << (RISCV_EXCP_ILLEGAL_INST)) |
281 (1ULL << (RISCV_EXCP_BREAKPOINT)) |
282 (1ULL << (RISCV_EXCP_LOAD_ADDR_MIS)) |
283 (1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT)) |
284 (1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS)) |
285 (1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT)) |
286 (1ULL << (RISCV_EXCP_U_ECALL)) |
287 (1ULL << (RISCV_EXCP_S_ECALL)) |
288 (1ULL << (RISCV_EXCP_VS_ECALL)) |
289 (1ULL << (RISCV_EXCP_M_ECALL)) |
290 (1ULL << (RISCV_EXCP_INST_PAGE_FAULT)) |
291 (1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT)) |
292 (1ULL << (RISCV_EXCP_STORE_PAGE_FAULT)) |
293 (1ULL << (RISCV_EXCP_INST_GUEST_PAGE_FAULT)) |
294 (1ULL << (RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT)) |
295 (1ULL << (RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT));
296 static const target_ulong sstatus_v1_9_mask = SSTATUS_SIE | SSTATUS_SPIE |
297 SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
298 SSTATUS_SUM | SSTATUS_SD;
299 static const target_ulong sstatus_v1_10_mask = SSTATUS_SIE | SSTATUS_SPIE |
300 SSTATUS_UIE | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS |
301 SSTATUS_SUM | SSTATUS_MXR | SSTATUS_SD;
302 static const target_ulong sip_writable_mask = SIP_SSIP | MIP_USIP | MIP_UEIP;
303 static const target_ulong hip_writable_mask = MIP_VSSIP | MIP_VSTIP | MIP_VSEIP;
304 static const target_ulong vsip_writable_mask = MIP_VSSIP;
305
306 #if defined(TARGET_RISCV32)
307 static const char valid_vm_1_09[16] = {
308 [VM_1_09_MBARE] = 1,
309 [VM_1_09_SV32] = 1,
310 };
311 static const char valid_vm_1_10[16] = {
312 [VM_1_10_MBARE] = 1,
313 [VM_1_10_SV32] = 1
314 };
315 #elif defined(TARGET_RISCV64)
316 static const char valid_vm_1_09[16] = {
317 [VM_1_09_MBARE] = 1,
318 [VM_1_09_SV39] = 1,
319 [VM_1_09_SV48] = 1,
320 };
321 static const char valid_vm_1_10[16] = {
322 [VM_1_10_MBARE] = 1,
323 [VM_1_10_SV39] = 1,
324 [VM_1_10_SV48] = 1,
325 [VM_1_10_SV57] = 1
326 };
327 #endif /* CONFIG_USER_ONLY */
328
329 /* Machine Information Registers */
330 static int read_zero(CPURISCVState *env, int csrno, target_ulong *val)
331 {
332 return *val = 0;
333 }
334
335 static int read_mhartid(CPURISCVState *env, int csrno, target_ulong *val)
336 {
337 *val = env->mhartid;
338 return 0;
339 }
340
341 /* Machine Trap Setup */
342 static int read_mstatus(CPURISCVState *env, int csrno, target_ulong *val)
343 {
344 *val = env->mstatus;
345 return 0;
346 }
347
348 static int validate_vm(CPURISCVState *env, target_ulong vm)
349 {
350 return (env->priv_ver >= PRIV_VERSION_1_10_0) ?
351 valid_vm_1_10[vm & 0xf] : valid_vm_1_09[vm & 0xf];
352 }
353
354 static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val)
355 {
356 target_ulong mstatus = env->mstatus;
357 target_ulong mask = 0;
358 int dirty;
359
360 /* flush tlb on mstatus fields that affect VM */
361 if (env->priv_ver <= PRIV_VERSION_1_09_1) {
362 if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP |
363 MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_VM)) {
364 tlb_flush(env_cpu(env));
365 }
366 mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
367 MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
368 MSTATUS_MPP | MSTATUS_MXR |
369 (validate_vm(env, get_field(val, MSTATUS_VM)) ?
370 MSTATUS_VM : 0);
371 }
372 if (env->priv_ver >= PRIV_VERSION_1_10_0) {
373 if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
374 MSTATUS_MPRV | MSTATUS_SUM)) {
375 tlb_flush(env_cpu(env));
376 }
377 mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE |
378 MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
379 MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
380 MSTATUS_TW;
381 #if defined(TARGET_RISCV64)
382 /*
383 * RV32: MPV and MTL are not in mstatus. The current plan is to
384 * add them to mstatush. For now, we just don't support it.
385 */
386 mask |= MSTATUS_MTL | MSTATUS_MPV;
387 #endif
388 }
389
390 mstatus = (mstatus & ~mask) | (val & mask);
391
392 dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) |
393 ((mstatus & MSTATUS_XS) == MSTATUS_XS);
394 mstatus = set_field(mstatus, MSTATUS_SD, dirty);
395 env->mstatus = mstatus;
396
397 return 0;
398 }
399
400 #ifdef TARGET_RISCV32
401 static int read_mstatush(CPURISCVState *env, int csrno, target_ulong *val)
402 {
403 *val = env->mstatush;
404 return 0;
405 }
406
407 static int write_mstatush(CPURISCVState *env, int csrno, target_ulong val)
408 {
409 if ((val ^ env->mstatush) & (MSTATUS_MPV)) {
410 tlb_flush(env_cpu(env));
411 }
412
413 val &= MSTATUS_MPV | MSTATUS_MTL;
414
415 env->mstatush = val;
416
417 return 0;
418 }
419 #endif
420
421 static int read_misa(CPURISCVState *env, int csrno, target_ulong *val)
422 {
423 *val = env->misa;
424 return 0;
425 }
426
427 static int write_misa(CPURISCVState *env, int csrno, target_ulong val)
428 {
429 if (!riscv_feature(env, RISCV_FEATURE_MISA)) {
430 /* drop write to misa */
431 return 0;
432 }
433
434 /* 'I' or 'E' must be present */
435 if (!(val & (RVI | RVE))) {
436 /* It is not, drop write to misa */
437 return 0;
438 }
439
440 /* 'E' excludes all other extensions */
441 if (val & RVE) {
442 /* when we support 'E' we can do "val = RVE;" however
443 * for now we just drop writes if 'E' is present.
444 */
445 return 0;
446 }
447
448 /* Mask extensions that are not supported by this hart */
449 val &= env->misa_mask;
450
451 /* Mask extensions that are not supported by QEMU */
452 val &= (RVI | RVE | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
453
454 /* 'D' depends on 'F', so clear 'D' if 'F' is not present */
455 if ((val & RVD) && !(val & RVF)) {
456 val &= ~RVD;
457 }
458
459 /* Suppress 'C' if next instruction is not aligned
460 * TODO: this should check next_pc
461 */
462 if ((val & RVC) && (GETPC() & ~3) != 0) {
463 val &= ~RVC;
464 }
465
466 /* misa.MXL writes are not supported by QEMU */
467 val = (env->misa & MISA_MXL) | (val & ~MISA_MXL);
468
469 /* flush translation cache */
470 if (val != env->misa) {
471 tb_flush(env_cpu(env));
472 }
473
474 env->misa = val;
475
476 return 0;
477 }
478
479 static int read_medeleg(CPURISCVState *env, int csrno, target_ulong *val)
480 {
481 *val = env->medeleg;
482 return 0;
483 }
484
485 static int write_medeleg(CPURISCVState *env, int csrno, target_ulong val)
486 {
487 env->medeleg = (env->medeleg & ~delegable_excps) | (val & delegable_excps);
488 return 0;
489 }
490
491 static int read_mideleg(CPURISCVState *env, int csrno, target_ulong *val)
492 {
493 *val = env->mideleg;
494 return 0;
495 }
496
497 static int write_mideleg(CPURISCVState *env, int csrno, target_ulong val)
498 {
499 env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints);
500 if (riscv_has_ext(env, RVH)) {
501 env->mideleg |= VS_MODE_INTERRUPTS;
502 }
503 return 0;
504 }
505
506 static int read_mie(CPURISCVState *env, int csrno, target_ulong *val)
507 {
508 *val = env->mie;
509 return 0;
510 }
511
512 static int write_mie(CPURISCVState *env, int csrno, target_ulong val)
513 {
514 env->mie = (env->mie & ~all_ints) | (val & all_ints);
515 return 0;
516 }
517
518 static int read_mtvec(CPURISCVState *env, int csrno, target_ulong *val)
519 {
520 *val = env->mtvec;
521 return 0;
522 }
523
524 static int write_mtvec(CPURISCVState *env, int csrno, target_ulong val)
525 {
526 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
527 if ((val & 3) < 2) {
528 env->mtvec = val;
529 } else {
530 qemu_log_mask(LOG_UNIMP, "CSR_MTVEC: reserved mode not supported\n");
531 }
532 return 0;
533 }
534
535 static int read_mcounteren(CPURISCVState *env, int csrno, target_ulong *val)
536 {
537 if (env->priv_ver < PRIV_VERSION_1_10_0) {
538 return -1;
539 }
540 *val = env->mcounteren;
541 return 0;
542 }
543
544 static int write_mcounteren(CPURISCVState *env, int csrno, target_ulong val)
545 {
546 if (env->priv_ver < PRIV_VERSION_1_10_0) {
547 return -1;
548 }
549 env->mcounteren = val;
550 return 0;
551 }
552
553 /* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
554 static int read_mscounteren(CPURISCVState *env, int csrno, target_ulong *val)
555 {
556 if (env->priv_ver > PRIV_VERSION_1_09_1
557 && env->priv_ver < PRIV_VERSION_1_11_0) {
558 return -1;
559 }
560 *val = env->mcounteren;
561 return 0;
562 }
563
564 /* This regiser is replaced with CSR_MCOUNTINHIBIT in 1.11.0 */
565 static int write_mscounteren(CPURISCVState *env, int csrno, target_ulong val)
566 {
567 if (env->priv_ver > PRIV_VERSION_1_09_1
568 && env->priv_ver < PRIV_VERSION_1_11_0) {
569 return -1;
570 }
571 env->mcounteren = val;
572 return 0;
573 }
574
575 static int read_mucounteren(CPURISCVState *env, int csrno, target_ulong *val)
576 {
577 if (env->priv_ver > PRIV_VERSION_1_09_1) {
578 return -1;
579 }
580 *val = env->scounteren;
581 return 0;
582 }
583
584 static int write_mucounteren(CPURISCVState *env, int csrno, target_ulong val)
585 {
586 if (env->priv_ver > PRIV_VERSION_1_09_1) {
587 return -1;
588 }
589 env->scounteren = val;
590 return 0;
591 }
592
593 /* Machine Trap Handling */
594 static int read_mscratch(CPURISCVState *env, int csrno, target_ulong *val)
595 {
596 *val = env->mscratch;
597 return 0;
598 }
599
600 static int write_mscratch(CPURISCVState *env, int csrno, target_ulong val)
601 {
602 env->mscratch = val;
603 return 0;
604 }
605
606 static int read_mepc(CPURISCVState *env, int csrno, target_ulong *val)
607 {
608 *val = env->mepc;
609 return 0;
610 }
611
612 static int write_mepc(CPURISCVState *env, int csrno, target_ulong val)
613 {
614 env->mepc = val;
615 return 0;
616 }
617
618 static int read_mcause(CPURISCVState *env, int csrno, target_ulong *val)
619 {
620 *val = env->mcause;
621 return 0;
622 }
623
624 static int write_mcause(CPURISCVState *env, int csrno, target_ulong val)
625 {
626 env->mcause = val;
627 return 0;
628 }
629
630 static int read_mbadaddr(CPURISCVState *env, int csrno, target_ulong *val)
631 {
632 *val = env->mbadaddr;
633 return 0;
634 }
635
636 static int write_mbadaddr(CPURISCVState *env, int csrno, target_ulong val)
637 {
638 env->mbadaddr = val;
639 return 0;
640 }
641
642 static int rmw_mip(CPURISCVState *env, int csrno, target_ulong *ret_value,
643 target_ulong new_value, target_ulong write_mask)
644 {
645 RISCVCPU *cpu = env_archcpu(env);
646 /* Allow software control of delegable interrupts not claimed by hardware */
647 target_ulong mask = write_mask & delegable_ints & ~env->miclaim;
648 uint32_t old_mip;
649
650 if (mask) {
651 old_mip = riscv_cpu_update_mip(cpu, mask, (new_value & mask));
652 } else {
653 old_mip = env->mip;
654 }
655
656 if (ret_value) {
657 *ret_value = old_mip;
658 }
659
660 return 0;
661 }
662
663 /* Supervisor Trap Setup */
664 static int read_sstatus(CPURISCVState *env, int csrno, target_ulong *val)
665 {
666 target_ulong mask = ((env->priv_ver >= PRIV_VERSION_1_10_0) ?
667 sstatus_v1_10_mask : sstatus_v1_9_mask);
668 *val = env->mstatus & mask;
669 return 0;
670 }
671
672 static int write_sstatus(CPURISCVState *env, int csrno, target_ulong val)
673 {
674 target_ulong mask = ((env->priv_ver >= PRIV_VERSION_1_10_0) ?
675 sstatus_v1_10_mask : sstatus_v1_9_mask);
676 target_ulong newval = (env->mstatus & ~mask) | (val & mask);
677 return write_mstatus(env, CSR_MSTATUS, newval);
678 }
679
680 static int read_sie(CPURISCVState *env, int csrno, target_ulong *val)
681 {
682 if (riscv_cpu_virt_enabled(env)) {
683 /* Tell the guest the VS bits, shifted to the S bit locations */
684 *val = (env->mie & env->mideleg & VS_MODE_INTERRUPTS) >> 1;
685 } else {
686 *val = env->mie & env->mideleg;
687 }
688 return 0;
689 }
690
691 static int write_sie(CPURISCVState *env, int csrno, target_ulong val)
692 {
693 target_ulong newval;
694
695 if (riscv_cpu_virt_enabled(env)) {
696 /* Shift the guests S bits to VS */
697 newval = (env->mie & ~VS_MODE_INTERRUPTS) |
698 ((val << 1) & VS_MODE_INTERRUPTS);
699 } else {
700 newval = (env->mie & ~S_MODE_INTERRUPTS) | (val & S_MODE_INTERRUPTS);
701 }
702
703 return write_mie(env, CSR_MIE, newval);
704 }
705
706 static int read_stvec(CPURISCVState *env, int csrno, target_ulong *val)
707 {
708 *val = env->stvec;
709 return 0;
710 }
711
712 static int write_stvec(CPURISCVState *env, int csrno, target_ulong val)
713 {
714 /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */
715 if ((val & 3) < 2) {
716 env->stvec = val;
717 } else {
718 qemu_log_mask(LOG_UNIMP, "CSR_STVEC: reserved mode not supported\n");
719 }
720 return 0;
721 }
722
723 static int read_scounteren(CPURISCVState *env, int csrno, target_ulong *val)
724 {
725 if (env->priv_ver < PRIV_VERSION_1_10_0) {
726 return -1;
727 }
728 *val = env->scounteren;
729 return 0;
730 }
731
732 static int write_scounteren(CPURISCVState *env, int csrno, target_ulong val)
733 {
734 if (env->priv_ver < PRIV_VERSION_1_10_0) {
735 return -1;
736 }
737 env->scounteren = val;
738 return 0;
739 }
740
741 /* Supervisor Trap Handling */
742 static int read_sscratch(CPURISCVState *env, int csrno, target_ulong *val)
743 {
744 *val = env->sscratch;
745 return 0;
746 }
747
748 static int write_sscratch(CPURISCVState *env, int csrno, target_ulong val)
749 {
750 env->sscratch = val;
751 return 0;
752 }
753
754 static int read_sepc(CPURISCVState *env, int csrno, target_ulong *val)
755 {
756 *val = env->sepc;
757 return 0;
758 }
759
760 static int write_sepc(CPURISCVState *env, int csrno, target_ulong val)
761 {
762 env->sepc = val;
763 return 0;
764 }
765
766 static int read_scause(CPURISCVState *env, int csrno, target_ulong *val)
767 {
768 *val = env->scause;
769 return 0;
770 }
771
772 static int write_scause(CPURISCVState *env, int csrno, target_ulong val)
773 {
774 env->scause = val;
775 return 0;
776 }
777
778 static int read_sbadaddr(CPURISCVState *env, int csrno, target_ulong *val)
779 {
780 *val = env->sbadaddr;
781 return 0;
782 }
783
784 static int write_sbadaddr(CPURISCVState *env, int csrno, target_ulong val)
785 {
786 env->sbadaddr = val;
787 return 0;
788 }
789
790 static int rmw_sip(CPURISCVState *env, int csrno, target_ulong *ret_value,
791 target_ulong new_value, target_ulong write_mask)
792 {
793 int ret;
794
795 if (riscv_cpu_virt_enabled(env)) {
796 /* Shift the new values to line up with the VS bits */
797 ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value << 1,
798 (write_mask & sip_writable_mask) << 1 & env->mideleg);
799 ret &= vsip_writable_mask;
800 ret >>= 1;
801 } else {
802 ret = rmw_mip(env, CSR_MSTATUS, ret_value, new_value,
803 write_mask & env->mideleg & sip_writable_mask);
804 }
805
806 *ret_value &= env->mideleg;
807 return ret;
808 }
809
810 /* Supervisor Protection and Translation */
811 static int read_satp(CPURISCVState *env, int csrno, target_ulong *val)
812 {
813 if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
814 *val = 0;
815 } else if (env->priv_ver >= PRIV_VERSION_1_10_0) {
816 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
817 return -1;
818 } else {
819 *val = env->satp;
820 }
821 } else {
822 *val = env->sptbr;
823 }
824 return 0;
825 }
826
827 static int write_satp(CPURISCVState *env, int csrno, target_ulong val)
828 {
829 if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
830 return 0;
831 }
832 if (env->priv_ver <= PRIV_VERSION_1_09_1 && (val ^ env->sptbr)) {
833 tlb_flush(env_cpu(env));
834 env->sptbr = val & (((target_ulong)
835 1 << (TARGET_PHYS_ADDR_SPACE_BITS - PGSHIFT)) - 1);
836 }
837 if (env->priv_ver >= PRIV_VERSION_1_10_0 &&
838 validate_vm(env, get_field(val, SATP_MODE)) &&
839 ((val ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN)))
840 {
841 if (env->priv == PRV_S && get_field(env->mstatus, MSTATUS_TVM)) {
842 return -1;
843 } else {
844 if((val ^ env->satp) & SATP_ASID) {
845 tlb_flush(env_cpu(env));
846 }
847 env->satp = val;
848 }
849 }
850 return 0;
851 }
852
853 /* Hypervisor Extensions */
854 static int read_hstatus(CPURISCVState *env, int csrno, target_ulong *val)
855 {
856 *val = env->hstatus;
857 return 0;
858 }
859
860 static int write_hstatus(CPURISCVState *env, int csrno, target_ulong val)
861 {
862 env->hstatus = val;
863 return 0;
864 }
865
866 static int read_hedeleg(CPURISCVState *env, int csrno, target_ulong *val)
867 {
868 *val = env->hedeleg;
869 return 0;
870 }
871
872 static int write_hedeleg(CPURISCVState *env, int csrno, target_ulong val)
873 {
874 env->hedeleg = val;
875 return 0;
876 }
877
878 static int read_hideleg(CPURISCVState *env, int csrno, target_ulong *val)
879 {
880 *val = env->hideleg;
881 return 0;
882 }
883
884 static int write_hideleg(CPURISCVState *env, int csrno, target_ulong val)
885 {
886 env->hideleg = val;
887 return 0;
888 }
889
890 static int rmw_hip(CPURISCVState *env, int csrno, target_ulong *ret_value,
891 target_ulong new_value, target_ulong write_mask)
892 {
893 int ret = rmw_mip(env, 0, ret_value, new_value,
894 write_mask & hip_writable_mask);
895
896 return ret;
897 }
898
899 static int read_hie(CPURISCVState *env, int csrno, target_ulong *val)
900 {
901 *val = env->mie & VS_MODE_INTERRUPTS;
902 return 0;
903 }
904
905 static int write_hie(CPURISCVState *env, int csrno, target_ulong val)
906 {
907 target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS);
908 return write_mie(env, CSR_MIE, newval);
909 }
910
911 static int read_hcounteren(CPURISCVState *env, int csrno, target_ulong *val)
912 {
913 *val = env->hcounteren;
914 return 0;
915 }
916
917 static int write_hcounteren(CPURISCVState *env, int csrno, target_ulong val)
918 {
919 env->hcounteren = val;
920 return 0;
921 }
922
923 static int read_htval(CPURISCVState *env, int csrno, target_ulong *val)
924 {
925 *val = env->htval;
926 return 0;
927 }
928
929 static int write_htval(CPURISCVState *env, int csrno, target_ulong val)
930 {
931 env->htval = val;
932 return 0;
933 }
934
935 static int read_htinst(CPURISCVState *env, int csrno, target_ulong *val)
936 {
937 *val = env->htinst;
938 return 0;
939 }
940
941 static int write_htinst(CPURISCVState *env, int csrno, target_ulong val)
942 {
943 env->htinst = val;
944 return 0;
945 }
946
947 static int read_hgatp(CPURISCVState *env, int csrno, target_ulong *val)
948 {
949 *val = env->hgatp;
950 return 0;
951 }
952
953 static int write_hgatp(CPURISCVState *env, int csrno, target_ulong val)
954 {
955 env->hgatp = val;
956 return 0;
957 }
958
959 static int read_htimedelta(CPURISCVState *env, int csrno, target_ulong *val)
960 {
961 if (!env->rdtime_fn) {
962 return -1;
963 }
964
965 #if defined(TARGET_RISCV32)
966 *val = env->htimedelta & 0xffffffff;
967 #else
968 *val = env->htimedelta;
969 #endif
970 return 0;
971 }
972
973 static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong val)
974 {
975 if (!env->rdtime_fn) {
976 return -1;
977 }
978
979 #if defined(TARGET_RISCV32)
980 env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val);
981 #else
982 env->htimedelta = val;
983 #endif
984 return 0;
985 }
986
987 #if defined(TARGET_RISCV32)
988 static int read_htimedeltah(CPURISCVState *env, int csrno, target_ulong *val)
989 {
990 if (!env->rdtime_fn) {
991 return -1;
992 }
993
994 *val = env->htimedelta >> 32;
995 return 0;
996 }
997
998 static int write_htimedeltah(CPURISCVState *env, int csrno, target_ulong val)
999 {
1000 if (!env->rdtime_fn) {
1001 return -1;
1002 }
1003
1004 env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
1005 return 0;
1006 }
1007 #endif
1008
1009 /* Virtual CSR Registers */
1010 static int read_vsstatus(CPURISCVState *env, int csrno, target_ulong *val)
1011 {
1012 *val = env->vsstatus;
1013 return 0;
1014 }
1015
1016 static int write_vsstatus(CPURISCVState *env, int csrno, target_ulong val)
1017 {
1018 env->vsstatus = val;
1019 return 0;
1020 }
1021
1022 static int rmw_vsip(CPURISCVState *env, int csrno, target_ulong *ret_value,
1023 target_ulong new_value, target_ulong write_mask)
1024 {
1025 int ret = rmw_mip(env, 0, ret_value, new_value,
1026 write_mask & env->mideleg & vsip_writable_mask);
1027 return ret;
1028 }
1029
1030 static int read_vsie(CPURISCVState *env, int csrno, target_ulong *val)
1031 {
1032 *val = env->mie & env->mideleg & VS_MODE_INTERRUPTS;
1033 return 0;
1034 }
1035
1036 static int write_vsie(CPURISCVState *env, int csrno, target_ulong val)
1037 {
1038 target_ulong newval = (env->mie & ~env->mideleg) | (val & env->mideleg & MIP_VSSIP);
1039 return write_mie(env, CSR_MIE, newval);
1040 }
1041
1042 static int read_vstvec(CPURISCVState *env, int csrno, target_ulong *val)
1043 {
1044 *val = env->vstvec;
1045 return 0;
1046 }
1047
1048 static int write_vstvec(CPURISCVState *env, int csrno, target_ulong val)
1049 {
1050 env->vstvec = val;
1051 return 0;
1052 }
1053
1054 static int read_vsscratch(CPURISCVState *env, int csrno, target_ulong *val)
1055 {
1056 *val = env->vsscratch;
1057 return 0;
1058 }
1059
1060 static int write_vsscratch(CPURISCVState *env, int csrno, target_ulong val)
1061 {
1062 env->vsscratch = val;
1063 return 0;
1064 }
1065
1066 static int read_vsepc(CPURISCVState *env, int csrno, target_ulong *val)
1067 {
1068 *val = env->vsepc;
1069 return 0;
1070 }
1071
1072 static int write_vsepc(CPURISCVState *env, int csrno, target_ulong val)
1073 {
1074 env->vsepc = val;
1075 return 0;
1076 }
1077
1078 static int read_vscause(CPURISCVState *env, int csrno, target_ulong *val)
1079 {
1080 *val = env->vscause;
1081 return 0;
1082 }
1083
1084 static int write_vscause(CPURISCVState *env, int csrno, target_ulong val)
1085 {
1086 env->vscause = val;
1087 return 0;
1088 }
1089
1090 static int read_vstval(CPURISCVState *env, int csrno, target_ulong *val)
1091 {
1092 *val = env->vstval;
1093 return 0;
1094 }
1095
1096 static int write_vstval(CPURISCVState *env, int csrno, target_ulong val)
1097 {
1098 env->vstval = val;
1099 return 0;
1100 }
1101
1102 static int read_vsatp(CPURISCVState *env, int csrno, target_ulong *val)
1103 {
1104 *val = env->vsatp;
1105 return 0;
1106 }
1107
1108 static int write_vsatp(CPURISCVState *env, int csrno, target_ulong val)
1109 {
1110 env->vsatp = val;
1111 return 0;
1112 }
1113
1114 static int read_mtval2(CPURISCVState *env, int csrno, target_ulong *val)
1115 {
1116 *val = env->mtval2;
1117 return 0;
1118 }
1119
1120 static int write_mtval2(CPURISCVState *env, int csrno, target_ulong val)
1121 {
1122 env->mtval2 = val;
1123 return 0;
1124 }
1125
1126 static int read_mtinst(CPURISCVState *env, int csrno, target_ulong *val)
1127 {
1128 *val = env->mtinst;
1129 return 0;
1130 }
1131
1132 static int write_mtinst(CPURISCVState *env, int csrno, target_ulong val)
1133 {
1134 env->mtinst = val;
1135 return 0;
1136 }
1137
1138 /* Physical Memory Protection */
1139 static int read_pmpcfg(CPURISCVState *env, int csrno, target_ulong *val)
1140 {
1141 *val = pmpcfg_csr_read(env, csrno - CSR_PMPCFG0);
1142 return 0;
1143 }
1144
1145 static int write_pmpcfg(CPURISCVState *env, int csrno, target_ulong val)
1146 {
1147 pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val);
1148 return 0;
1149 }
1150
1151 static int read_pmpaddr(CPURISCVState *env, int csrno, target_ulong *val)
1152 {
1153 *val = pmpaddr_csr_read(env, csrno - CSR_PMPADDR0);
1154 return 0;
1155 }
1156
1157 static int write_pmpaddr(CPURISCVState *env, int csrno, target_ulong val)
1158 {
1159 pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val);
1160 return 0;
1161 }
1162
1163 #endif
1164
1165 /*
1166 * riscv_csrrw - read and/or update control and status register
1167 *
1168 * csrr <-> riscv_csrrw(env, csrno, ret_value, 0, 0);
1169 * csrrw <-> riscv_csrrw(env, csrno, ret_value, value, -1);
1170 * csrrs <-> riscv_csrrw(env, csrno, ret_value, -1, value);
1171 * csrrc <-> riscv_csrrw(env, csrno, ret_value, 0, value);
1172 */
1173
1174 int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value,
1175 target_ulong new_value, target_ulong write_mask)
1176 {
1177 int ret;
1178 target_ulong old_value;
1179 RISCVCPU *cpu = env_archcpu(env);
1180
1181 /* check privileges and return -1 if check fails */
1182 #if !defined(CONFIG_USER_ONLY)
1183 int effective_priv = env->priv;
1184 int read_only = get_field(csrno, 0xC00) == 3;
1185
1186 if (riscv_has_ext(env, RVH) &&
1187 env->priv == PRV_S &&
1188 !riscv_cpu_virt_enabled(env)) {
1189 /*
1190 * We are in S mode without virtualisation, therefore we are in HS Mode.
1191 * Add 1 to the effective privledge level to allow us to access the
1192 * Hypervisor CSRs.
1193 */
1194 effective_priv++;
1195 }
1196
1197 if ((write_mask && read_only) ||
1198 (!env->debugger && (effective_priv < get_field(csrno, 0x300)))) {
1199 return -1;
1200 }
1201 #endif
1202
1203 /* ensure the CSR extension is enabled. */
1204 if (!cpu->cfg.ext_icsr) {
1205 return -1;
1206 }
1207
1208 /* check predicate */
1209 if (!csr_ops[csrno].predicate || csr_ops[csrno].predicate(env, csrno) < 0) {
1210 return -1;
1211 }
1212
1213 /* execute combined read/write operation if it exists */
1214 if (csr_ops[csrno].op) {
1215 return csr_ops[csrno].op(env, csrno, ret_value, new_value, write_mask);
1216 }
1217
1218 /* if no accessor exists then return failure */
1219 if (!csr_ops[csrno].read) {
1220 return -1;
1221 }
1222
1223 /* read old value */
1224 ret = csr_ops[csrno].read(env, csrno, &old_value);
1225 if (ret < 0) {
1226 return ret;
1227 }
1228
1229 /* write value if writable and write mask set, otherwise drop writes */
1230 if (write_mask) {
1231 new_value = (old_value & ~write_mask) | (new_value & write_mask);
1232 if (csr_ops[csrno].write) {
1233 ret = csr_ops[csrno].write(env, csrno, new_value);
1234 if (ret < 0) {
1235 return ret;
1236 }
1237 }
1238 }
1239
1240 /* return old value */
1241 if (ret_value) {
1242 *ret_value = old_value;
1243 }
1244
1245 return 0;
1246 }
1247
1248 /*
1249 * Debugger support. If not in user mode, set env->debugger before the
1250 * riscv_csrrw call and clear it after the call.
1251 */
1252 int riscv_csrrw_debug(CPURISCVState *env, int csrno, target_ulong *ret_value,
1253 target_ulong new_value, target_ulong write_mask)
1254 {
1255 int ret;
1256 #if !defined(CONFIG_USER_ONLY)
1257 env->debugger = true;
1258 #endif
1259 ret = riscv_csrrw(env, csrno, ret_value, new_value, write_mask);
1260 #if !defined(CONFIG_USER_ONLY)
1261 env->debugger = false;
1262 #endif
1263 return ret;
1264 }
1265
1266 /* Control and Status Register function table */
1267 static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
1268 /* User Floating-Point CSRs */
1269 [CSR_FFLAGS] = { fs, read_fflags, write_fflags },
1270 [CSR_FRM] = { fs, read_frm, write_frm },
1271 [CSR_FCSR] = { fs, read_fcsr, write_fcsr },
1272
1273 /* User Timers and Counters */
1274 [CSR_CYCLE] = { ctr, read_instret },
1275 [CSR_INSTRET] = { ctr, read_instret },
1276 #if defined(TARGET_RISCV32)
1277 [CSR_CYCLEH] = { ctr, read_instreth },
1278 [CSR_INSTRETH] = { ctr, read_instreth },
1279 #endif
1280
1281 /* In privileged mode, the monitor will have to emulate TIME CSRs only if
1282 * rdtime callback is not provided by machine/platform emulation */
1283 [CSR_TIME] = { ctr, read_time },
1284 #if defined(TARGET_RISCV32)
1285 [CSR_TIMEH] = { ctr, read_timeh },
1286 #endif
1287
1288 #if !defined(CONFIG_USER_ONLY)
1289 /* Machine Timers and Counters */
1290 [CSR_MCYCLE] = { any, read_instret },
1291 [CSR_MINSTRET] = { any, read_instret },
1292 #if defined(TARGET_RISCV32)
1293 [CSR_MCYCLEH] = { any, read_instreth },
1294 [CSR_MINSTRETH] = { any, read_instreth },
1295 #endif
1296
1297 /* Machine Information Registers */
1298 [CSR_MVENDORID] = { any, read_zero },
1299 [CSR_MARCHID] = { any, read_zero },
1300 [CSR_MIMPID] = { any, read_zero },
1301 [CSR_MHARTID] = { any, read_mhartid },
1302
1303 /* Machine Trap Setup */
1304 [CSR_MSTATUS] = { any, read_mstatus, write_mstatus },
1305 [CSR_MISA] = { any, read_misa, write_misa },
1306 [CSR_MIDELEG] = { any, read_mideleg, write_mideleg },
1307 [CSR_MEDELEG] = { any, read_medeleg, write_medeleg },
1308 [CSR_MIE] = { any, read_mie, write_mie },
1309 [CSR_MTVEC] = { any, read_mtvec, write_mtvec },
1310 [CSR_MCOUNTEREN] = { any, read_mcounteren, write_mcounteren },
1311
1312 #if defined(TARGET_RISCV32)
1313 [CSR_MSTATUSH] = { any, read_mstatush, write_mstatush },
1314 #endif
1315
1316 /* Legacy Counter Setup (priv v1.9.1) */
1317 [CSR_MUCOUNTEREN] = { any, read_mucounteren, write_mucounteren },
1318 [CSR_MSCOUNTEREN] = { any, read_mscounteren, write_mscounteren },
1319
1320 /* Machine Trap Handling */
1321 [CSR_MSCRATCH] = { any, read_mscratch, write_mscratch },
1322 [CSR_MEPC] = { any, read_mepc, write_mepc },
1323 [CSR_MCAUSE] = { any, read_mcause, write_mcause },
1324 [CSR_MBADADDR] = { any, read_mbadaddr, write_mbadaddr },
1325 [CSR_MIP] = { any, NULL, NULL, rmw_mip },
1326
1327 /* Supervisor Trap Setup */
1328 [CSR_SSTATUS] = { smode, read_sstatus, write_sstatus },
1329 [CSR_SIE] = { smode, read_sie, write_sie },
1330 [CSR_STVEC] = { smode, read_stvec, write_stvec },
1331 [CSR_SCOUNTEREN] = { smode, read_scounteren, write_scounteren },
1332
1333 /* Supervisor Trap Handling */
1334 [CSR_SSCRATCH] = { smode, read_sscratch, write_sscratch },
1335 [CSR_SEPC] = { smode, read_sepc, write_sepc },
1336 [CSR_SCAUSE] = { smode, read_scause, write_scause },
1337 [CSR_SBADADDR] = { smode, read_sbadaddr, write_sbadaddr },
1338 [CSR_SIP] = { smode, NULL, NULL, rmw_sip },
1339
1340 /* Supervisor Protection and Translation */
1341 [CSR_SATP] = { smode, read_satp, write_satp },
1342
1343 [CSR_HSTATUS] = { hmode, read_hstatus, write_hstatus },
1344 [CSR_HEDELEG] = { hmode, read_hedeleg, write_hedeleg },
1345 [CSR_HIDELEG] = { hmode, read_hideleg, write_hideleg },
1346 [CSR_HIP] = { hmode, NULL, NULL, rmw_hip },
1347 [CSR_HIE] = { hmode, read_hie, write_hie },
1348 [CSR_HCOUNTEREN] = { hmode, read_hcounteren, write_hcounteren },
1349 [CSR_HTVAL] = { hmode, read_htval, write_htval },
1350 [CSR_HTINST] = { hmode, read_htinst, write_htinst },
1351 [CSR_HGATP] = { hmode, read_hgatp, write_hgatp },
1352 [CSR_HTIMEDELTA] = { hmode, read_htimedelta, write_htimedelta },
1353 #if defined(TARGET_RISCV32)
1354 [CSR_HTIMEDELTAH] = { hmode, read_htimedeltah, write_htimedeltah},
1355 #endif
1356
1357 [CSR_VSSTATUS] = { hmode, read_vsstatus, write_vsstatus },
1358 [CSR_VSIP] = { hmode, NULL, NULL, rmw_vsip },
1359 [CSR_VSIE] = { hmode, read_vsie, write_vsie },
1360 [CSR_VSTVEC] = { hmode, read_vstvec, write_vstvec },
1361 [CSR_VSSCRATCH] = { hmode, read_vsscratch, write_vsscratch },
1362 [CSR_VSEPC] = { hmode, read_vsepc, write_vsepc },
1363 [CSR_VSCAUSE] = { hmode, read_vscause, write_vscause },
1364 [CSR_VSTVAL] = { hmode, read_vstval, write_vstval },
1365 [CSR_VSATP] = { hmode, read_vsatp, write_vsatp },
1366
1367 [CSR_MTVAL2] = { hmode, read_mtval2, write_mtval2 },
1368 [CSR_MTINST] = { hmode, read_mtinst, write_mtinst },
1369
1370 /* Physical Memory Protection */
1371 [CSR_PMPCFG0 ... CSR_PMPADDR9] = { pmp, read_pmpcfg, write_pmpcfg },
1372 [CSR_PMPADDR0 ... CSR_PMPADDR15] = { pmp, read_pmpaddr, write_pmpaddr },
1373
1374 /* Performance Counters */
1375 [CSR_HPMCOUNTER3 ... CSR_HPMCOUNTER31] = { ctr, read_zero },
1376 [CSR_MHPMCOUNTER3 ... CSR_MHPMCOUNTER31] = { any, read_zero },
1377 [CSR_MHPMEVENT3 ... CSR_MHPMEVENT31] = { any, read_zero },
1378 #if defined(TARGET_RISCV32)
1379 [CSR_HPMCOUNTER3H ... CSR_HPMCOUNTER31H] = { ctr, read_zero },
1380 [CSR_MHPMCOUNTER3H ... CSR_MHPMCOUNTER31H] = { any, read_zero },
1381 #endif
1382 #endif /* !CONFIG_USER_ONLY */
1383 };