target/riscv: Generate nanboxed results from fp helpers
[qemu.git] / target / riscv / fpu_helper.c
1 /*
2 * RISC-V FPU Emulation Helpers for QEMU.
3 *
4 * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19 #include "qemu/osdep.h"
20 #include "cpu.h"
21 #include "qemu/host-utils.h"
22 #include "exec/exec-all.h"
23 #include "exec/helper-proto.h"
24 #include "fpu/softfloat.h"
25 #include "internals.h"
26
27 target_ulong riscv_cpu_get_fflags(CPURISCVState *env)
28 {
29 int soft = get_float_exception_flags(&env->fp_status);
30 target_ulong hard = 0;
31
32 hard |= (soft & float_flag_inexact) ? FPEXC_NX : 0;
33 hard |= (soft & float_flag_underflow) ? FPEXC_UF : 0;
34 hard |= (soft & float_flag_overflow) ? FPEXC_OF : 0;
35 hard |= (soft & float_flag_divbyzero) ? FPEXC_DZ : 0;
36 hard |= (soft & float_flag_invalid) ? FPEXC_NV : 0;
37
38 return hard;
39 }
40
41 void riscv_cpu_set_fflags(CPURISCVState *env, target_ulong hard)
42 {
43 int soft = 0;
44
45 soft |= (hard & FPEXC_NX) ? float_flag_inexact : 0;
46 soft |= (hard & FPEXC_UF) ? float_flag_underflow : 0;
47 soft |= (hard & FPEXC_OF) ? float_flag_overflow : 0;
48 soft |= (hard & FPEXC_DZ) ? float_flag_divbyzero : 0;
49 soft |= (hard & FPEXC_NV) ? float_flag_invalid : 0;
50
51 set_float_exception_flags(soft, &env->fp_status);
52 }
53
54 void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm)
55 {
56 int softrm;
57
58 if (rm == 7) {
59 rm = env->frm;
60 }
61 switch (rm) {
62 case 0:
63 softrm = float_round_nearest_even;
64 break;
65 case 1:
66 softrm = float_round_to_zero;
67 break;
68 case 2:
69 softrm = float_round_down;
70 break;
71 case 3:
72 softrm = float_round_up;
73 break;
74 case 4:
75 softrm = float_round_ties_away;
76 break;
77 default:
78 riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC());
79 }
80
81 set_float_rounding_mode(softrm, &env->fp_status);
82 }
83
84 static uint64_t do_fmadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
85 uint64_t frs3, int flags)
86 {
87 return nanbox_s(float32_muladd(frs1, frs2, frs3, flags, &env->fp_status));
88 }
89
90 uint64_t helper_fmadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
91 uint64_t frs3)
92 {
93 return do_fmadd_s(env, frs1, frs2, frs3, 0);
94 }
95
96 uint64_t helper_fmadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
97 uint64_t frs3)
98 {
99 return float64_muladd(frs1, frs2, frs3, 0, &env->fp_status);
100 }
101
102 uint64_t helper_fmsub_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
103 uint64_t frs3)
104 {
105 return do_fmadd_s(env, frs1, frs2, frs3, float_muladd_negate_c);
106 }
107
108 uint64_t helper_fmsub_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
109 uint64_t frs3)
110 {
111 return float64_muladd(frs1, frs2, frs3, float_muladd_negate_c,
112 &env->fp_status);
113 }
114
115 uint64_t helper_fnmsub_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
116 uint64_t frs3)
117 {
118 return do_fmadd_s(env, frs1, frs2, frs3, float_muladd_negate_product);
119 }
120
121 uint64_t helper_fnmsub_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
122 uint64_t frs3)
123 {
124 return float64_muladd(frs1, frs2, frs3, float_muladd_negate_product,
125 &env->fp_status);
126 }
127
128 uint64_t helper_fnmadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
129 uint64_t frs3)
130 {
131 return do_fmadd_s(env, frs1, frs2, frs3,
132 float_muladd_negate_c | float_muladd_negate_product);
133 }
134
135 uint64_t helper_fnmadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2,
136 uint64_t frs3)
137 {
138 return float64_muladd(frs1, frs2, frs3, float_muladd_negate_c |
139 float_muladd_negate_product, &env->fp_status);
140 }
141
142 uint64_t helper_fadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
143 {
144 return nanbox_s(float32_add(frs1, frs2, &env->fp_status));
145 }
146
147 uint64_t helper_fsub_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
148 {
149 return nanbox_s(float32_sub(frs1, frs2, &env->fp_status));
150 }
151
152 uint64_t helper_fmul_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
153 {
154 return nanbox_s(float32_mul(frs1, frs2, &env->fp_status));
155 }
156
157 uint64_t helper_fdiv_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
158 {
159 return nanbox_s(float32_div(frs1, frs2, &env->fp_status));
160 }
161
162 uint64_t helper_fmin_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
163 {
164 return nanbox_s(float32_minnum(frs1, frs2, &env->fp_status));
165 }
166
167 uint64_t helper_fmax_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
168 {
169 return nanbox_s(float32_maxnum(frs1, frs2, &env->fp_status));
170 }
171
172 uint64_t helper_fsqrt_s(CPURISCVState *env, uint64_t frs1)
173 {
174 return nanbox_s(float32_sqrt(frs1, &env->fp_status));
175 }
176
177 target_ulong helper_fle_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
178 {
179 return float32_le(frs1, frs2, &env->fp_status);
180 }
181
182 target_ulong helper_flt_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
183 {
184 return float32_lt(frs1, frs2, &env->fp_status);
185 }
186
187 target_ulong helper_feq_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
188 {
189 return float32_eq_quiet(frs1, frs2, &env->fp_status);
190 }
191
192 target_ulong helper_fcvt_w_s(CPURISCVState *env, uint64_t frs1)
193 {
194 return float32_to_int32(frs1, &env->fp_status);
195 }
196
197 target_ulong helper_fcvt_wu_s(CPURISCVState *env, uint64_t frs1)
198 {
199 return (int32_t)float32_to_uint32(frs1, &env->fp_status);
200 }
201
202 #if defined(TARGET_RISCV64)
203 uint64_t helper_fcvt_l_s(CPURISCVState *env, uint64_t frs1)
204 {
205 return float32_to_int64(frs1, &env->fp_status);
206 }
207
208 uint64_t helper_fcvt_lu_s(CPURISCVState *env, uint64_t frs1)
209 {
210 return float32_to_uint64(frs1, &env->fp_status);
211 }
212 #endif
213
214 uint64_t helper_fcvt_s_w(CPURISCVState *env, target_ulong rs1)
215 {
216 return nanbox_s(int32_to_float32((int32_t)rs1, &env->fp_status));
217 }
218
219 uint64_t helper_fcvt_s_wu(CPURISCVState *env, target_ulong rs1)
220 {
221 return nanbox_s(uint32_to_float32((uint32_t)rs1, &env->fp_status));
222 }
223
224 #if defined(TARGET_RISCV64)
225 uint64_t helper_fcvt_s_l(CPURISCVState *env, uint64_t rs1)
226 {
227 return nanbox_s(int64_to_float32(rs1, &env->fp_status));
228 }
229
230 uint64_t helper_fcvt_s_lu(CPURISCVState *env, uint64_t rs1)
231 {
232 return nanbox_s(uint64_to_float32(rs1, &env->fp_status));
233 }
234 #endif
235
236 target_ulong helper_fclass_s(uint64_t frs1)
237 {
238 return fclass_s(frs1);
239 }
240
241 uint64_t helper_fadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
242 {
243 return float64_add(frs1, frs2, &env->fp_status);
244 }
245
246 uint64_t helper_fsub_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
247 {
248 return float64_sub(frs1, frs2, &env->fp_status);
249 }
250
251 uint64_t helper_fmul_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
252 {
253 return float64_mul(frs1, frs2, &env->fp_status);
254 }
255
256 uint64_t helper_fdiv_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
257 {
258 return float64_div(frs1, frs2, &env->fp_status);
259 }
260
261 uint64_t helper_fmin_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
262 {
263 return float64_minnum(frs1, frs2, &env->fp_status);
264 }
265
266 uint64_t helper_fmax_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
267 {
268 return float64_maxnum(frs1, frs2, &env->fp_status);
269 }
270
271 uint64_t helper_fcvt_s_d(CPURISCVState *env, uint64_t rs1)
272 {
273 return nanbox_s(float64_to_float32(rs1, &env->fp_status));
274 }
275
276 uint64_t helper_fcvt_d_s(CPURISCVState *env, uint64_t rs1)
277 {
278 return float32_to_float64(rs1, &env->fp_status);
279 }
280
281 uint64_t helper_fsqrt_d(CPURISCVState *env, uint64_t frs1)
282 {
283 return float64_sqrt(frs1, &env->fp_status);
284 }
285
286 target_ulong helper_fle_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
287 {
288 return float64_le(frs1, frs2, &env->fp_status);
289 }
290
291 target_ulong helper_flt_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
292 {
293 return float64_lt(frs1, frs2, &env->fp_status);
294 }
295
296 target_ulong helper_feq_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2)
297 {
298 return float64_eq_quiet(frs1, frs2, &env->fp_status);
299 }
300
301 target_ulong helper_fcvt_w_d(CPURISCVState *env, uint64_t frs1)
302 {
303 return float64_to_int32(frs1, &env->fp_status);
304 }
305
306 target_ulong helper_fcvt_wu_d(CPURISCVState *env, uint64_t frs1)
307 {
308 return (int32_t)float64_to_uint32(frs1, &env->fp_status);
309 }
310
311 #if defined(TARGET_RISCV64)
312 uint64_t helper_fcvt_l_d(CPURISCVState *env, uint64_t frs1)
313 {
314 return float64_to_int64(frs1, &env->fp_status);
315 }
316
317 uint64_t helper_fcvt_lu_d(CPURISCVState *env, uint64_t frs1)
318 {
319 return float64_to_uint64(frs1, &env->fp_status);
320 }
321 #endif
322
323 uint64_t helper_fcvt_d_w(CPURISCVState *env, target_ulong rs1)
324 {
325 return int32_to_float64((int32_t)rs1, &env->fp_status);
326 }
327
328 uint64_t helper_fcvt_d_wu(CPURISCVState *env, target_ulong rs1)
329 {
330 return uint32_to_float64((uint32_t)rs1, &env->fp_status);
331 }
332
333 #if defined(TARGET_RISCV64)
334 uint64_t helper_fcvt_d_l(CPURISCVState *env, uint64_t rs1)
335 {
336 return int64_to_float64(rs1, &env->fp_status);
337 }
338
339 uint64_t helper_fcvt_d_lu(CPURISCVState *env, uint64_t rs1)
340 {
341 return uint64_to_float64(rs1, &env->fp_status);
342 }
343 #endif
344
345 target_ulong helper_fclass_d(uint64_t frs1)
346 {
347 return fclass_d(frs1);
348 }