target/riscv: add vector stride load and store instructions
[qemu.git] / target / riscv / internals.h
1 /*
2 * QEMU RISC-V CPU -- internal functions and types
3 *
4 * Copyright (c) 2020 T-Head Semiconductor Co., Ltd. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2 or later, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along with
16 * this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19 #ifndef RISCV_CPU_INTERNALS_H
20 #define RISCV_CPU_INTERNALS_H
21
22 #include "hw/registerfields.h"
23
24 /* share data between vector helpers and decode code */
25 FIELD(VDATA, MLEN, 0, 8)
26 FIELD(VDATA, VM, 8, 1)
27 FIELD(VDATA, LMUL, 9, 2)
28 FIELD(VDATA, NF, 11, 4)
29 #endif