s390: guest support for diagnose 0x318
[qemu.git] / target / s390x / cpu.h
1 /*
2 * S/390 virtual CPU header
3 *
4 * For details on the s390x architecture and used definitions (e.g.,
5 * PSW, PER and DAT (Dynamic Address Translation)), please refer to
6 * the "z/Architecture Principles of Operations" - a.k.a. PoP.
7 *
8 * Copyright (c) 2009 Ulrich Hecht
9 * Copyright IBM Corp. 2012, 2018
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <http://www.gnu.org/licenses/>.
23 */
24
25 #ifndef S390X_CPU_H
26 #define S390X_CPU_H
27
28 #include "cpu-qom.h"
29 #include "cpu_models.h"
30 #include "exec/cpu-defs.h"
31
32 #define ELF_MACHINE_UNAME "S390X"
33
34 /* The z/Architecture has a strong memory model with some store-after-load re-ordering */
35 #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD)
36
37 #define TARGET_INSN_START_EXTRA_WORDS 2
38
39 #define MMU_USER_IDX 0
40
41 #define S390_MAX_CPUS 248
42
43 typedef struct PSW {
44 uint64_t mask;
45 uint64_t addr;
46 } PSW;
47
48 struct CPUS390XState {
49 uint64_t regs[16]; /* GP registers */
50 /*
51 * The floating point registers are part of the vector registers.
52 * vregs[0][0] -> vregs[15][0] are 16 floating point registers
53 */
54 uint64_t vregs[32][2] QEMU_ALIGNED(16); /* vector registers */
55 uint32_t aregs[16]; /* access registers */
56 uint64_t gscb[4]; /* guarded storage control */
57 uint64_t etoken; /* etoken */
58 uint64_t etoken_extension; /* etoken extension */
59
60 /* Fields up to this point are not cleared by initial CPU reset */
61 struct {} start_initial_reset_fields;
62
63 uint32_t fpc; /* floating-point control register */
64 uint32_t cc_op;
65 bool bpbc; /* branch prediction blocking */
66
67 float_status fpu_status; /* passed to softfloat lib */
68
69 /* The low part of a 128-bit return, or remainder of a divide. */
70 uint64_t retxl;
71
72 PSW psw;
73
74 S390CrashReason crash_reason;
75
76 uint64_t cc_src;
77 uint64_t cc_dst;
78 uint64_t cc_vr;
79
80 uint64_t ex_value;
81
82 uint64_t __excp_addr;
83 uint64_t psa;
84
85 uint32_t int_pgm_code;
86 uint32_t int_pgm_ilen;
87
88 uint32_t int_svc_code;
89 uint32_t int_svc_ilen;
90
91 uint64_t per_address;
92 uint16_t per_perc_atmid;
93
94 uint64_t cregs[16]; /* control registers */
95
96 uint64_t ckc;
97 uint64_t cputm;
98 uint32_t todpr;
99
100 uint64_t pfault_token;
101 uint64_t pfault_compare;
102 uint64_t pfault_select;
103
104 uint64_t gbea;
105 uint64_t pp;
106
107 /* Fields up to this point are not cleared by normal CPU reset */
108 struct {} start_normal_reset_fields;
109 uint8_t riccb[64]; /* runtime instrumentation control */
110
111 int pending_int;
112 uint16_t external_call_addr;
113 DECLARE_BITMAP(emergency_signals, S390_MAX_CPUS);
114
115 uint64_t diag318_info;
116
117 /* Fields up to this point are cleared by a CPU reset */
118 struct {} end_reset_fields;
119
120 #if !defined(CONFIG_USER_ONLY)
121 uint32_t core_id; /* PoP "CPU address", same as cpu_index */
122 uint64_t cpuid;
123 #endif
124
125 QEMUTimer *tod_timer;
126
127 QEMUTimer *cpu_timer;
128
129 /*
130 * The cpu state represents the logical state of a cpu. In contrast to other
131 * architectures, there is a difference between a halt and a stop on s390.
132 * If all cpus are either stopped (including check stop) or in the disabled
133 * wait state, the vm can be shut down.
134 * The acceptable cpu_state values are defined in the CpuInfoS390State
135 * enum.
136 */
137 uint8_t cpu_state;
138
139 /* currently processed sigp order */
140 uint8_t sigp_order;
141
142 };
143
144 static inline uint64_t *get_freg(CPUS390XState *cs, int nr)
145 {
146 return &cs->vregs[nr][0];
147 }
148
149 /**
150 * S390CPU:
151 * @env: #CPUS390XState.
152 *
153 * An S/390 CPU.
154 */
155 struct S390CPU {
156 /*< private >*/
157 CPUState parent_obj;
158 /*< public >*/
159
160 CPUNegativeOffsetState neg;
161 CPUS390XState env;
162 S390CPUModel *model;
163 /* needed for live migration */
164 void *irqstate;
165 uint32_t irqstate_saved_size;
166 };
167
168
169 #ifndef CONFIG_USER_ONLY
170 extern const VMStateDescription vmstate_s390_cpu;
171 #endif
172
173 /* distinguish between 24 bit and 31 bit addressing */
174 #define HIGH_ORDER_BIT 0x80000000
175
176 /* Interrupt Codes */
177 /* Program Interrupts */
178 #define PGM_OPERATION 0x0001
179 #define PGM_PRIVILEGED 0x0002
180 #define PGM_EXECUTE 0x0003
181 #define PGM_PROTECTION 0x0004
182 #define PGM_ADDRESSING 0x0005
183 #define PGM_SPECIFICATION 0x0006
184 #define PGM_DATA 0x0007
185 #define PGM_FIXPT_OVERFLOW 0x0008
186 #define PGM_FIXPT_DIVIDE 0x0009
187 #define PGM_DEC_OVERFLOW 0x000a
188 #define PGM_DEC_DIVIDE 0x000b
189 #define PGM_HFP_EXP_OVERFLOW 0x000c
190 #define PGM_HFP_EXP_UNDERFLOW 0x000d
191 #define PGM_HFP_SIGNIFICANCE 0x000e
192 #define PGM_HFP_DIVIDE 0x000f
193 #define PGM_SEGMENT_TRANS 0x0010
194 #define PGM_PAGE_TRANS 0x0011
195 #define PGM_TRANS_SPEC 0x0012
196 #define PGM_SPECIAL_OP 0x0013
197 #define PGM_OPERAND 0x0015
198 #define PGM_TRACE_TABLE 0x0016
199 #define PGM_VECTOR_PROCESSING 0x001b
200 #define PGM_SPACE_SWITCH 0x001c
201 #define PGM_HFP_SQRT 0x001d
202 #define PGM_PC_TRANS_SPEC 0x001f
203 #define PGM_AFX_TRANS 0x0020
204 #define PGM_ASX_TRANS 0x0021
205 #define PGM_LX_TRANS 0x0022
206 #define PGM_EX_TRANS 0x0023
207 #define PGM_PRIM_AUTH 0x0024
208 #define PGM_SEC_AUTH 0x0025
209 #define PGM_ALET_SPEC 0x0028
210 #define PGM_ALEN_SPEC 0x0029
211 #define PGM_ALE_SEQ 0x002a
212 #define PGM_ASTE_VALID 0x002b
213 #define PGM_ASTE_SEQ 0x002c
214 #define PGM_EXT_AUTH 0x002d
215 #define PGM_STACK_FULL 0x0030
216 #define PGM_STACK_EMPTY 0x0031
217 #define PGM_STACK_SPEC 0x0032
218 #define PGM_STACK_TYPE 0x0033
219 #define PGM_STACK_OP 0x0034
220 #define PGM_ASCE_TYPE 0x0038
221 #define PGM_REG_FIRST_TRANS 0x0039
222 #define PGM_REG_SEC_TRANS 0x003a
223 #define PGM_REG_THIRD_TRANS 0x003b
224 #define PGM_MONITOR 0x0040
225 #define PGM_PER 0x0080
226 #define PGM_CRYPTO 0x0119
227
228 /* External Interrupts */
229 #define EXT_INTERRUPT_KEY 0x0040
230 #define EXT_CLOCK_COMP 0x1004
231 #define EXT_CPU_TIMER 0x1005
232 #define EXT_MALFUNCTION 0x1200
233 #define EXT_EMERGENCY 0x1201
234 #define EXT_EXTERNAL_CALL 0x1202
235 #define EXT_ETR 0x1406
236 #define EXT_SERVICE 0x2401
237 #define EXT_VIRTIO 0x2603
238
239 /* PSW defines */
240 #undef PSW_MASK_PER
241 #undef PSW_MASK_UNUSED_2
242 #undef PSW_MASK_UNUSED_3
243 #undef PSW_MASK_DAT
244 #undef PSW_MASK_IO
245 #undef PSW_MASK_EXT
246 #undef PSW_MASK_KEY
247 #undef PSW_SHIFT_KEY
248 #undef PSW_MASK_MCHECK
249 #undef PSW_MASK_WAIT
250 #undef PSW_MASK_PSTATE
251 #undef PSW_MASK_ASC
252 #undef PSW_SHIFT_ASC
253 #undef PSW_MASK_CC
254 #undef PSW_MASK_PM
255 #undef PSW_MASK_RI
256 #undef PSW_SHIFT_MASK_PM
257 #undef PSW_MASK_64
258 #undef PSW_MASK_32
259 #undef PSW_MASK_ESA_ADDR
260
261 #define PSW_MASK_PER 0x4000000000000000ULL
262 #define PSW_MASK_UNUSED_2 0x2000000000000000ULL
263 #define PSW_MASK_UNUSED_3 0x1000000000000000ULL
264 #define PSW_MASK_DAT 0x0400000000000000ULL
265 #define PSW_MASK_IO 0x0200000000000000ULL
266 #define PSW_MASK_EXT 0x0100000000000000ULL
267 #define PSW_MASK_KEY 0x00F0000000000000ULL
268 #define PSW_SHIFT_KEY 52
269 #define PSW_MASK_SHORTPSW 0x0008000000000000ULL
270 #define PSW_MASK_MCHECK 0x0004000000000000ULL
271 #define PSW_MASK_WAIT 0x0002000000000000ULL
272 #define PSW_MASK_PSTATE 0x0001000000000000ULL
273 #define PSW_MASK_ASC 0x0000C00000000000ULL
274 #define PSW_SHIFT_ASC 46
275 #define PSW_MASK_CC 0x0000300000000000ULL
276 #define PSW_MASK_PM 0x00000F0000000000ULL
277 #define PSW_SHIFT_MASK_PM 40
278 #define PSW_MASK_RI 0x0000008000000000ULL
279 #define PSW_MASK_64 0x0000000100000000ULL
280 #define PSW_MASK_32 0x0000000080000000ULL
281 #define PSW_MASK_SHORT_ADDR 0x000000007fffffffULL
282 #define PSW_MASK_SHORT_CTRL 0xffffffff80000000ULL
283
284 #undef PSW_ASC_PRIMARY
285 #undef PSW_ASC_ACCREG
286 #undef PSW_ASC_SECONDARY
287 #undef PSW_ASC_HOME
288
289 #define PSW_ASC_PRIMARY 0x0000000000000000ULL
290 #define PSW_ASC_ACCREG 0x0000400000000000ULL
291 #define PSW_ASC_SECONDARY 0x0000800000000000ULL
292 #define PSW_ASC_HOME 0x0000C00000000000ULL
293
294 /* the address space values shifted */
295 #define AS_PRIMARY 0
296 #define AS_ACCREG 1
297 #define AS_SECONDARY 2
298 #define AS_HOME 3
299
300 /* tb flags */
301
302 #define FLAG_MASK_PSW_SHIFT 31
303 #define FLAG_MASK_PER (PSW_MASK_PER >> FLAG_MASK_PSW_SHIFT)
304 #define FLAG_MASK_DAT (PSW_MASK_DAT >> FLAG_MASK_PSW_SHIFT)
305 #define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT)
306 #define FLAG_MASK_ASC (PSW_MASK_ASC >> FLAG_MASK_PSW_SHIFT)
307 #define FLAG_MASK_64 (PSW_MASK_64 >> FLAG_MASK_PSW_SHIFT)
308 #define FLAG_MASK_32 (PSW_MASK_32 >> FLAG_MASK_PSW_SHIFT)
309 #define FLAG_MASK_PSW (FLAG_MASK_PER | FLAG_MASK_DAT | FLAG_MASK_PSTATE \
310 | FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32)
311
312 /* we'll use some unused PSW positions to store CR flags in tb flags */
313 #define FLAG_MASK_AFP (PSW_MASK_UNUSED_2 >> FLAG_MASK_PSW_SHIFT)
314 #define FLAG_MASK_VECTOR (PSW_MASK_UNUSED_3 >> FLAG_MASK_PSW_SHIFT)
315
316 /* Control register 0 bits */
317 #define CR0_LOWPROT 0x0000000010000000ULL
318 #define CR0_SECONDARY 0x0000000004000000ULL
319 #define CR0_EDAT 0x0000000000800000ULL
320 #define CR0_AFP 0x0000000000040000ULL
321 #define CR0_VECTOR 0x0000000000020000ULL
322 #define CR0_IEP 0x0000000000100000ULL
323 #define CR0_EMERGENCY_SIGNAL_SC 0x0000000000004000ULL
324 #define CR0_EXTERNAL_CALL_SC 0x0000000000002000ULL
325 #define CR0_CKC_SC 0x0000000000000800ULL
326 #define CR0_CPU_TIMER_SC 0x0000000000000400ULL
327 #define CR0_SERVICE_SC 0x0000000000000200ULL
328
329 /* Control register 14 bits */
330 #define CR14_CHANNEL_REPORT_SC 0x0000000010000000ULL
331
332 /* MMU */
333 #define MMU_PRIMARY_IDX 0
334 #define MMU_SECONDARY_IDX 1
335 #define MMU_HOME_IDX 2
336 #define MMU_REAL_IDX 3
337
338 static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch)
339 {
340 #ifdef CONFIG_USER_ONLY
341 return MMU_USER_IDX;
342 #else
343 if (!(env->psw.mask & PSW_MASK_DAT)) {
344 return MMU_REAL_IDX;
345 }
346
347 if (ifetch) {
348 if ((env->psw.mask & PSW_MASK_ASC) == PSW_ASC_HOME) {
349 return MMU_HOME_IDX;
350 }
351 return MMU_PRIMARY_IDX;
352 }
353
354 switch (env->psw.mask & PSW_MASK_ASC) {
355 case PSW_ASC_PRIMARY:
356 return MMU_PRIMARY_IDX;
357 case PSW_ASC_SECONDARY:
358 return MMU_SECONDARY_IDX;
359 case PSW_ASC_HOME:
360 return MMU_HOME_IDX;
361 case PSW_ASC_ACCREG:
362 /* Fallthrough: access register mode is not yet supported */
363 default:
364 abort();
365 }
366 #endif
367 }
368
369 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
370 target_ulong *cs_base, uint32_t *flags)
371 {
372 *pc = env->psw.addr;
373 *cs_base = env->ex_value;
374 *flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW;
375 if (env->cregs[0] & CR0_AFP) {
376 *flags |= FLAG_MASK_AFP;
377 }
378 if (env->cregs[0] & CR0_VECTOR) {
379 *flags |= FLAG_MASK_VECTOR;
380 }
381 }
382
383 /* PER bits from control register 9 */
384 #define PER_CR9_EVENT_BRANCH 0x80000000
385 #define PER_CR9_EVENT_IFETCH 0x40000000
386 #define PER_CR9_EVENT_STORE 0x20000000
387 #define PER_CR9_EVENT_STORE_REAL 0x08000000
388 #define PER_CR9_EVENT_NULLIFICATION 0x01000000
389 #define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000
390 #define PER_CR9_CONTROL_ALTERATION 0x00200000
391
392 /* PER bits from the PER CODE/ATMID/AI in lowcore */
393 #define PER_CODE_EVENT_BRANCH 0x8000
394 #define PER_CODE_EVENT_IFETCH 0x4000
395 #define PER_CODE_EVENT_STORE 0x2000
396 #define PER_CODE_EVENT_STORE_REAL 0x0800
397 #define PER_CODE_EVENT_NULLIFICATION 0x0100
398
399 #define EXCP_EXT 1 /* external interrupt */
400 #define EXCP_SVC 2 /* supervisor call (syscall) */
401 #define EXCP_PGM 3 /* program interruption */
402 #define EXCP_RESTART 4 /* restart interrupt */
403 #define EXCP_STOP 5 /* stop interrupt */
404 #define EXCP_IO 7 /* I/O interrupt */
405 #define EXCP_MCHK 8 /* machine check */
406
407 #define INTERRUPT_EXT_CPU_TIMER (1 << 3)
408 #define INTERRUPT_EXT_CLOCK_COMPARATOR (1 << 4)
409 #define INTERRUPT_EXTERNAL_CALL (1 << 5)
410 #define INTERRUPT_EMERGENCY_SIGNAL (1 << 6)
411 #define INTERRUPT_RESTART (1 << 7)
412 #define INTERRUPT_STOP (1 << 8)
413
414 /* Program Status Word. */
415 #define S390_PSWM_REGNUM 0
416 #define S390_PSWA_REGNUM 1
417 /* General Purpose Registers. */
418 #define S390_R0_REGNUM 2
419 #define S390_R1_REGNUM 3
420 #define S390_R2_REGNUM 4
421 #define S390_R3_REGNUM 5
422 #define S390_R4_REGNUM 6
423 #define S390_R5_REGNUM 7
424 #define S390_R6_REGNUM 8
425 #define S390_R7_REGNUM 9
426 #define S390_R8_REGNUM 10
427 #define S390_R9_REGNUM 11
428 #define S390_R10_REGNUM 12
429 #define S390_R11_REGNUM 13
430 #define S390_R12_REGNUM 14
431 #define S390_R13_REGNUM 15
432 #define S390_R14_REGNUM 16
433 #define S390_R15_REGNUM 17
434 /* Total Core Registers. */
435 #define S390_NUM_CORE_REGS 18
436
437 static inline void setcc(S390CPU *cpu, uint64_t cc)
438 {
439 CPUS390XState *env = &cpu->env;
440
441 env->psw.mask &= ~(3ull << 44);
442 env->psw.mask |= (cc & 3) << 44;
443 env->cc_op = cc;
444 }
445
446 /* STSI */
447 #define STSI_R0_FC_MASK 0x00000000f0000000ULL
448 #define STSI_R0_FC_CURRENT 0x0000000000000000ULL
449 #define STSI_R0_FC_LEVEL_1 0x0000000010000000ULL
450 #define STSI_R0_FC_LEVEL_2 0x0000000020000000ULL
451 #define STSI_R0_FC_LEVEL_3 0x0000000030000000ULL
452 #define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL
453 #define STSI_R0_SEL1_MASK 0x00000000000000ffULL
454 #define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL
455 #define STSI_R1_SEL2_MASK 0x000000000000ffffULL
456
457 /* Basic Machine Configuration */
458 typedef struct SysIB_111 {
459 uint8_t res1[32];
460 uint8_t manuf[16];
461 uint8_t type[4];
462 uint8_t res2[12];
463 uint8_t model[16];
464 uint8_t sequence[16];
465 uint8_t plant[4];
466 uint8_t res3[3996];
467 } SysIB_111;
468 QEMU_BUILD_BUG_ON(sizeof(SysIB_111) != 4096);
469
470 /* Basic Machine CPU */
471 typedef struct SysIB_121 {
472 uint8_t res1[80];
473 uint8_t sequence[16];
474 uint8_t plant[4];
475 uint8_t res2[2];
476 uint16_t cpu_addr;
477 uint8_t res3[3992];
478 } SysIB_121;
479 QEMU_BUILD_BUG_ON(sizeof(SysIB_121) != 4096);
480
481 /* Basic Machine CPUs */
482 typedef struct SysIB_122 {
483 uint8_t res1[32];
484 uint32_t capability;
485 uint16_t total_cpus;
486 uint16_t conf_cpus;
487 uint16_t standby_cpus;
488 uint16_t reserved_cpus;
489 uint16_t adjustments[2026];
490 } SysIB_122;
491 QEMU_BUILD_BUG_ON(sizeof(SysIB_122) != 4096);
492
493 /* LPAR CPU */
494 typedef struct SysIB_221 {
495 uint8_t res1[80];
496 uint8_t sequence[16];
497 uint8_t plant[4];
498 uint16_t cpu_id;
499 uint16_t cpu_addr;
500 uint8_t res3[3992];
501 } SysIB_221;
502 QEMU_BUILD_BUG_ON(sizeof(SysIB_221) != 4096);
503
504 /* LPAR CPUs */
505 typedef struct SysIB_222 {
506 uint8_t res1[32];
507 uint16_t lpar_num;
508 uint8_t res2;
509 uint8_t lcpuc;
510 uint16_t total_cpus;
511 uint16_t conf_cpus;
512 uint16_t standby_cpus;
513 uint16_t reserved_cpus;
514 uint8_t name[8];
515 uint32_t caf;
516 uint8_t res3[16];
517 uint16_t dedicated_cpus;
518 uint16_t shared_cpus;
519 uint8_t res4[4020];
520 } SysIB_222;
521 QEMU_BUILD_BUG_ON(sizeof(SysIB_222) != 4096);
522
523 /* VM CPUs */
524 typedef struct SysIB_322 {
525 uint8_t res1[31];
526 uint8_t count;
527 struct {
528 uint8_t res2[4];
529 uint16_t total_cpus;
530 uint16_t conf_cpus;
531 uint16_t standby_cpus;
532 uint16_t reserved_cpus;
533 uint8_t name[8];
534 uint32_t caf;
535 uint8_t cpi[16];
536 uint8_t res5[3];
537 uint8_t ext_name_encoding;
538 uint32_t res3;
539 uint8_t uuid[16];
540 } vm[8];
541 uint8_t res4[1504];
542 uint8_t ext_names[8][256];
543 } SysIB_322;
544 QEMU_BUILD_BUG_ON(sizeof(SysIB_322) != 4096);
545
546 typedef union SysIB {
547 SysIB_111 sysib_111;
548 SysIB_121 sysib_121;
549 SysIB_122 sysib_122;
550 SysIB_221 sysib_221;
551 SysIB_222 sysib_222;
552 SysIB_322 sysib_322;
553 } SysIB;
554 QEMU_BUILD_BUG_ON(sizeof(SysIB) != 4096);
555
556 /* MMU defines */
557 #define ASCE_ORIGIN (~0xfffULL) /* segment table origin */
558 #define ASCE_SUBSPACE 0x200 /* subspace group control */
559 #define ASCE_PRIVATE_SPACE 0x100 /* private space control */
560 #define ASCE_ALT_EVENT 0x80 /* storage alteration event control */
561 #define ASCE_SPACE_SWITCH 0x40 /* space switch event */
562 #define ASCE_REAL_SPACE 0x20 /* real space control */
563 #define ASCE_TYPE_MASK 0x0c /* asce table type mask */
564 #define ASCE_TYPE_REGION1 0x0c /* region first table type */
565 #define ASCE_TYPE_REGION2 0x08 /* region second table type */
566 #define ASCE_TYPE_REGION3 0x04 /* region third table type */
567 #define ASCE_TYPE_SEGMENT 0x00 /* segment table type */
568 #define ASCE_TABLE_LENGTH 0x03 /* region table length */
569
570 #define REGION_ENTRY_ORIGIN 0xfffffffffffff000ULL
571 #define REGION_ENTRY_P 0x0000000000000200ULL
572 #define REGION_ENTRY_TF 0x00000000000000c0ULL
573 #define REGION_ENTRY_I 0x0000000000000020ULL
574 #define REGION_ENTRY_TT 0x000000000000000cULL
575 #define REGION_ENTRY_TL 0x0000000000000003ULL
576
577 #define REGION_ENTRY_TT_REGION1 0x000000000000000cULL
578 #define REGION_ENTRY_TT_REGION2 0x0000000000000008ULL
579 #define REGION_ENTRY_TT_REGION3 0x0000000000000004ULL
580
581 #define REGION3_ENTRY_RFAA 0xffffffff80000000ULL
582 #define REGION3_ENTRY_AV 0x0000000000010000ULL
583 #define REGION3_ENTRY_ACC 0x000000000000f000ULL
584 #define REGION3_ENTRY_F 0x0000000000000800ULL
585 #define REGION3_ENTRY_FC 0x0000000000000400ULL
586 #define REGION3_ENTRY_IEP 0x0000000000000100ULL
587 #define REGION3_ENTRY_CR 0x0000000000000010ULL
588
589 #define SEGMENT_ENTRY_ORIGIN 0xfffffffffffff800ULL
590 #define SEGMENT_ENTRY_SFAA 0xfffffffffff00000ULL
591 #define SEGMENT_ENTRY_AV 0x0000000000010000ULL
592 #define SEGMENT_ENTRY_ACC 0x000000000000f000ULL
593 #define SEGMENT_ENTRY_F 0x0000000000000800ULL
594 #define SEGMENT_ENTRY_FC 0x0000000000000400ULL
595 #define SEGMENT_ENTRY_P 0x0000000000000200ULL
596 #define SEGMENT_ENTRY_IEP 0x0000000000000100ULL
597 #define SEGMENT_ENTRY_I 0x0000000000000020ULL
598 #define SEGMENT_ENTRY_CS 0x0000000000000010ULL
599 #define SEGMENT_ENTRY_TT 0x000000000000000cULL
600
601 #define SEGMENT_ENTRY_TT_SEGMENT 0x0000000000000000ULL
602
603 #define PAGE_ENTRY_0 0x0000000000000800ULL
604 #define PAGE_ENTRY_I 0x0000000000000400ULL
605 #define PAGE_ENTRY_P 0x0000000000000200ULL
606 #define PAGE_ENTRY_IEP 0x0000000000000100ULL
607
608 #define VADDR_REGION1_TX_MASK 0xffe0000000000000ULL
609 #define VADDR_REGION2_TX_MASK 0x001ffc0000000000ULL
610 #define VADDR_REGION3_TX_MASK 0x000003ff80000000ULL
611 #define VADDR_SEGMENT_TX_MASK 0x000000007ff00000ULL
612 #define VADDR_PAGE_TX_MASK 0x00000000000ff000ULL
613
614 #define VADDR_REGION1_TX(vaddr) (((vaddr) & VADDR_REGION1_TX_MASK) >> 53)
615 #define VADDR_REGION2_TX(vaddr) (((vaddr) & VADDR_REGION2_TX_MASK) >> 42)
616 #define VADDR_REGION3_TX(vaddr) (((vaddr) & VADDR_REGION3_TX_MASK) >> 31)
617 #define VADDR_SEGMENT_TX(vaddr) (((vaddr) & VADDR_SEGMENT_TX_MASK) >> 20)
618 #define VADDR_PAGE_TX(vaddr) (((vaddr) & VADDR_PAGE_TX_MASK) >> 12)
619
620 #define VADDR_REGION1_TL(vaddr) (((vaddr) & 0xc000000000000000ULL) >> 62)
621 #define VADDR_REGION2_TL(vaddr) (((vaddr) & 0x0018000000000000ULL) >> 51)
622 #define VADDR_REGION3_TL(vaddr) (((vaddr) & 0x0000030000000000ULL) >> 40)
623 #define VADDR_SEGMENT_TL(vaddr) (((vaddr) & 0x0000000060000000ULL) >> 29)
624
625 #define SK_C (0x1 << 1)
626 #define SK_R (0x1 << 2)
627 #define SK_F (0x1 << 3)
628 #define SK_ACC_MASK (0xf << 4)
629
630 /* SIGP order codes */
631 #define SIGP_SENSE 0x01
632 #define SIGP_EXTERNAL_CALL 0x02
633 #define SIGP_EMERGENCY 0x03
634 #define SIGP_START 0x04
635 #define SIGP_STOP 0x05
636 #define SIGP_RESTART 0x06
637 #define SIGP_STOP_STORE_STATUS 0x09
638 #define SIGP_INITIAL_CPU_RESET 0x0b
639 #define SIGP_CPU_RESET 0x0c
640 #define SIGP_SET_PREFIX 0x0d
641 #define SIGP_STORE_STATUS_ADDR 0x0e
642 #define SIGP_SET_ARCH 0x12
643 #define SIGP_COND_EMERGENCY 0x13
644 #define SIGP_SENSE_RUNNING 0x15
645 #define SIGP_STORE_ADTL_STATUS 0x17
646
647 /* SIGP condition codes */
648 #define SIGP_CC_ORDER_CODE_ACCEPTED 0
649 #define SIGP_CC_STATUS_STORED 1
650 #define SIGP_CC_BUSY 2
651 #define SIGP_CC_NOT_OPERATIONAL 3
652
653 /* SIGP status bits */
654 #define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL
655 #define SIGP_STAT_NOT_RUNNING 0x00000400UL
656 #define SIGP_STAT_INCORRECT_STATE 0x00000200UL
657 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
658 #define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL
659 #define SIGP_STAT_STOPPED 0x00000040UL
660 #define SIGP_STAT_OPERATOR_INTERV 0x00000020UL
661 #define SIGP_STAT_CHECK_STOP 0x00000010UL
662 #define SIGP_STAT_INOPERATIVE 0x00000004UL
663 #define SIGP_STAT_INVALID_ORDER 0x00000002UL
664 #define SIGP_STAT_RECEIVER_CHECK 0x00000001UL
665
666 /* SIGP SET ARCHITECTURE modes */
667 #define SIGP_MODE_ESA_S390 0
668 #define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1
669 #define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2
670
671 /* SIGP order code mask corresponding to bit positions 56-63 */
672 #define SIGP_ORDER_MASK 0x000000ff
673
674 /* machine check interruption code */
675
676 /* subclasses */
677 #define MCIC_SC_SD 0x8000000000000000ULL
678 #define MCIC_SC_PD 0x4000000000000000ULL
679 #define MCIC_SC_SR 0x2000000000000000ULL
680 #define MCIC_SC_CD 0x0800000000000000ULL
681 #define MCIC_SC_ED 0x0400000000000000ULL
682 #define MCIC_SC_DG 0x0100000000000000ULL
683 #define MCIC_SC_W 0x0080000000000000ULL
684 #define MCIC_SC_CP 0x0040000000000000ULL
685 #define MCIC_SC_SP 0x0020000000000000ULL
686 #define MCIC_SC_CK 0x0010000000000000ULL
687
688 /* subclass modifiers */
689 #define MCIC_SCM_B 0x0002000000000000ULL
690 #define MCIC_SCM_DA 0x0000000020000000ULL
691 #define MCIC_SCM_AP 0x0000000000080000ULL
692
693 /* storage errors */
694 #define MCIC_SE_SE 0x0000800000000000ULL
695 #define MCIC_SE_SC 0x0000400000000000ULL
696 #define MCIC_SE_KE 0x0000200000000000ULL
697 #define MCIC_SE_DS 0x0000100000000000ULL
698 #define MCIC_SE_IE 0x0000000080000000ULL
699
700 /* validity bits */
701 #define MCIC_VB_WP 0x0000080000000000ULL
702 #define MCIC_VB_MS 0x0000040000000000ULL
703 #define MCIC_VB_PM 0x0000020000000000ULL
704 #define MCIC_VB_IA 0x0000010000000000ULL
705 #define MCIC_VB_FA 0x0000008000000000ULL
706 #define MCIC_VB_VR 0x0000004000000000ULL
707 #define MCIC_VB_EC 0x0000002000000000ULL
708 #define MCIC_VB_FP 0x0000001000000000ULL
709 #define MCIC_VB_GR 0x0000000800000000ULL
710 #define MCIC_VB_CR 0x0000000400000000ULL
711 #define MCIC_VB_ST 0x0000000100000000ULL
712 #define MCIC_VB_AR 0x0000000040000000ULL
713 #define MCIC_VB_GS 0x0000000008000000ULL
714 #define MCIC_VB_PR 0x0000000000200000ULL
715 #define MCIC_VB_FC 0x0000000000100000ULL
716 #define MCIC_VB_CT 0x0000000000020000ULL
717 #define MCIC_VB_CC 0x0000000000010000ULL
718
719 static inline uint64_t s390_build_validity_mcic(void)
720 {
721 uint64_t mcic;
722
723 /*
724 * Indicate all validity bits (no damage) only. Other bits have to be
725 * added by the caller. (storage errors, subclasses and subclass modifiers)
726 */
727 mcic = MCIC_VB_WP | MCIC_VB_MS | MCIC_VB_PM | MCIC_VB_IA | MCIC_VB_FP |
728 MCIC_VB_GR | MCIC_VB_CR | MCIC_VB_ST | MCIC_VB_AR | MCIC_VB_PR |
729 MCIC_VB_FC | MCIC_VB_CT | MCIC_VB_CC;
730 if (s390_has_feat(S390_FEAT_VECTOR)) {
731 mcic |= MCIC_VB_VR;
732 }
733 if (s390_has_feat(S390_FEAT_GUARDED_STORAGE)) {
734 mcic |= MCIC_VB_GS;
735 }
736 return mcic;
737 }
738
739 static inline void s390_do_cpu_full_reset(CPUState *cs, run_on_cpu_data arg)
740 {
741 cpu_reset(cs);
742 }
743
744 static inline void s390_do_cpu_reset(CPUState *cs, run_on_cpu_data arg)
745 {
746 S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
747
748 scc->reset(cs, S390_CPU_RESET_NORMAL);
749 }
750
751 static inline void s390_do_cpu_initial_reset(CPUState *cs, run_on_cpu_data arg)
752 {
753 S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
754
755 scc->reset(cs, S390_CPU_RESET_INITIAL);
756 }
757
758 static inline void s390_do_cpu_load_normal(CPUState *cs, run_on_cpu_data arg)
759 {
760 S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
761
762 scc->load_normal(cs);
763 }
764
765
766 /* cpu.c */
767 void s390_crypto_reset(void);
768 int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit);
769 void s390_set_max_pagesize(uint64_t pagesize, Error **errp);
770 void s390_cmma_reset(void);
771 void s390_enable_css_support(S390CPU *cpu);
772 int s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch_id,
773 int vq, bool assign);
774 #ifndef CONFIG_USER_ONLY
775 unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
776 #else
777 static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
778 {
779 return 0;
780 }
781 #endif /* CONFIG_USER_ONLY */
782 static inline uint8_t s390_cpu_get_state(S390CPU *cpu)
783 {
784 return cpu->env.cpu_state;
785 }
786
787
788 /* cpu_models.c */
789 void s390_cpu_list(void);
790 #define cpu_list s390_cpu_list
791 void s390_set_qemu_cpu_model(uint16_t type, uint8_t gen, uint8_t ec_ga,
792 const S390FeatInit feat_init);
793
794
795 /* helper.c */
796 #define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU
797 #define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX)
798 #define CPU_RESOLVING_TYPE TYPE_S390_CPU
799
800 /* you can call this signal handler from your SIGBUS and SIGSEGV
801 signal handlers to inform the virtual CPU of exceptions. non zero
802 is returned if the signal was handled by the virtual CPU. */
803 int cpu_s390x_signal_handler(int host_signum, void *pinfo, void *puc);
804 #define cpu_signal_handler cpu_s390x_signal_handler
805
806
807 /* interrupt.c */
808 void s390_crw_mchk(void);
809 void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr,
810 uint32_t io_int_parm, uint32_t io_int_word);
811 #define RA_IGNORED 0
812 void s390_program_interrupt(CPUS390XState *env, uint32_t code, uintptr_t ra);
813 /* service interrupts are floating therefore we must not pass an cpustate */
814 void s390_sclp_extint(uint32_t parm);
815
816 /* mmu_helper.c */
817 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
818 int len, bool is_write);
819 #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len) \
820 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false)
821 #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \
822 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true)
823 #define s390_cpu_virt_mem_check_read(cpu, laddr, ar, len) \
824 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, false)
825 #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \
826 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true)
827 void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, uintptr_t ra);
828 int s390_cpu_pv_mem_rw(S390CPU *cpu, unsigned int offset, void *hostbuf,
829 int len, bool is_write);
830 #define s390_cpu_pv_mem_read(cpu, offset, dest, len) \
831 s390_cpu_pv_mem_rw(cpu, offset, dest, len, false)
832 #define s390_cpu_pv_mem_write(cpu, offset, dest, len) \
833 s390_cpu_pv_mem_rw(cpu, offset, dest, len, true)
834
835 /* sigp.c */
836 int s390_cpu_restart(S390CPU *cpu);
837 void s390_init_sigp(void);
838
839
840 /* outside of target/s390x/ */
841 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
842
843 typedef CPUS390XState CPUArchState;
844 typedef S390CPU ArchCPU;
845
846 #include "exec/cpu-all.h"
847
848 #endif