hw/arm/virt: Merge VirtBoardInfo and VirtMachineState
[qemu.git] / target / s390x / cpu.h
1 /*
2 * S/390 virtual CPU header
3 *
4 * Copyright (c) 2009 Ulrich Hecht
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * Contributions after 2012-10-29 are licensed under the terms of the
17 * GNU GPL, version 2 or (at your option) any later version.
18 *
19 * You should have received a copy of the GNU (Lesser) General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
21 */
22
23 #ifndef S390X_CPU_H
24 #define S390X_CPU_H
25
26 #include "qemu-common.h"
27 #include "cpu-qom.h"
28
29 #define TARGET_LONG_BITS 64
30
31 #define ELF_MACHINE_UNAME "S390X"
32
33 #define CPUArchState struct CPUS390XState
34
35 #include "exec/cpu-defs.h"
36 #define TARGET_PAGE_BITS 12
37
38 #define TARGET_PHYS_ADDR_SPACE_BITS 64
39 #define TARGET_VIRT_ADDR_SPACE_BITS 64
40
41 #include "exec/cpu-all.h"
42
43 #include "fpu/softfloat.h"
44
45 #define NB_MMU_MODES 3
46 #define TARGET_INSN_START_EXTRA_WORDS 1
47
48 #define MMU_MODE0_SUFFIX _primary
49 #define MMU_MODE1_SUFFIX _secondary
50 #define MMU_MODE2_SUFFIX _home
51
52 #define MMU_USER_IDX 0
53
54 #define MAX_EXT_QUEUE 16
55 #define MAX_IO_QUEUE 16
56 #define MAX_MCHK_QUEUE 16
57
58 #define PSW_MCHK_MASK 0x0004000000000000
59 #define PSW_IO_MASK 0x0200000000000000
60
61 typedef struct PSW {
62 uint64_t mask;
63 uint64_t addr;
64 } PSW;
65
66 typedef struct ExtQueue {
67 uint32_t code;
68 uint32_t param;
69 uint32_t param64;
70 } ExtQueue;
71
72 typedef struct IOIntQueue {
73 uint16_t id;
74 uint16_t nr;
75 uint32_t parm;
76 uint32_t word;
77 } IOIntQueue;
78
79 typedef struct MchkQueue {
80 uint16_t type;
81 } MchkQueue;
82
83 typedef struct CPUS390XState {
84 uint64_t regs[16]; /* GP registers */
85 /*
86 * The floating point registers are part of the vector registers.
87 * vregs[0][0] -> vregs[15][0] are 16 floating point registers
88 */
89 CPU_DoubleU vregs[32][2]; /* vector registers */
90 uint32_t aregs[16]; /* access registers */
91
92 uint32_t fpc; /* floating-point control register */
93 uint32_t cc_op;
94
95 float_status fpu_status; /* passed to softfloat lib */
96
97 /* The low part of a 128-bit return, or remainder of a divide. */
98 uint64_t retxl;
99
100 PSW psw;
101
102 uint64_t cc_src;
103 uint64_t cc_dst;
104 uint64_t cc_vr;
105
106 uint64_t __excp_addr;
107 uint64_t psa;
108
109 uint32_t int_pgm_code;
110 uint32_t int_pgm_ilen;
111
112 uint32_t int_svc_code;
113 uint32_t int_svc_ilen;
114
115 uint64_t per_address;
116 uint16_t per_perc_atmid;
117
118 uint64_t cregs[16]; /* control registers */
119
120 ExtQueue ext_queue[MAX_EXT_QUEUE];
121 IOIntQueue io_queue[MAX_IO_QUEUE][8];
122 MchkQueue mchk_queue[MAX_MCHK_QUEUE];
123
124 int pending_int;
125 int ext_index;
126 int io_index[8];
127 int mchk_index;
128
129 uint64_t ckc;
130 uint64_t cputm;
131 uint32_t todpr;
132
133 uint64_t pfault_token;
134 uint64_t pfault_compare;
135 uint64_t pfault_select;
136
137 uint64_t gbea;
138 uint64_t pp;
139
140 uint8_t riccb[64];
141
142 CPU_COMMON
143
144 /* reset does memset(0) up to here */
145
146 uint32_t cpu_num;
147 uint32_t machine_type;
148
149 uint64_t tod_offset;
150 uint64_t tod_basetime;
151 QEMUTimer *tod_timer;
152
153 QEMUTimer *cpu_timer;
154
155 /*
156 * The cpu state represents the logical state of a cpu. In contrast to other
157 * architectures, there is a difference between a halt and a stop on s390.
158 * If all cpus are either stopped (including check stop) or in the disabled
159 * wait state, the vm can be shut down.
160 */
161 #define CPU_STATE_UNINITIALIZED 0x00
162 #define CPU_STATE_STOPPED 0x01
163 #define CPU_STATE_CHECK_STOP 0x02
164 #define CPU_STATE_OPERATING 0x03
165 #define CPU_STATE_LOAD 0x04
166 uint8_t cpu_state;
167
168 /* currently processed sigp order */
169 uint8_t sigp_order;
170
171 } CPUS390XState;
172
173 static inline CPU_DoubleU *get_freg(CPUS390XState *cs, int nr)
174 {
175 return &cs->vregs[nr][0];
176 }
177
178 /**
179 * S390CPU:
180 * @env: #CPUS390XState.
181 *
182 * An S/390 CPU.
183 */
184 struct S390CPU {
185 /*< private >*/
186 CPUState parent_obj;
187 /*< public >*/
188
189 CPUS390XState env;
190 int64_t id;
191 S390CPUModel *model;
192 /* needed for live migration */
193 void *irqstate;
194 uint32_t irqstate_saved_size;
195 };
196
197 static inline S390CPU *s390_env_get_cpu(CPUS390XState *env)
198 {
199 return container_of(env, S390CPU, env);
200 }
201
202 #define ENV_GET_CPU(e) CPU(s390_env_get_cpu(e))
203
204 #define ENV_OFFSET offsetof(S390CPU, env)
205
206 #ifndef CONFIG_USER_ONLY
207 extern const struct VMStateDescription vmstate_s390_cpu;
208 #endif
209
210 void s390_cpu_do_interrupt(CPUState *cpu);
211 bool s390_cpu_exec_interrupt(CPUState *cpu, int int_req);
212 void s390_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
213 int flags);
214 int s390_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
215 int cpuid, void *opaque);
216
217 hwaddr s390_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
218 hwaddr s390_cpu_get_phys_addr_debug(CPUState *cpu, vaddr addr);
219 int s390_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
220 int s390_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
221 void s390_cpu_gdb_init(CPUState *cs);
222 void s390x_cpu_debug_excp_handler(CPUState *cs);
223
224 #include "sysemu/kvm.h"
225
226 /* distinguish between 24 bit and 31 bit addressing */
227 #define HIGH_ORDER_BIT 0x80000000
228
229 /* Interrupt Codes */
230 /* Program Interrupts */
231 #define PGM_OPERATION 0x0001
232 #define PGM_PRIVILEGED 0x0002
233 #define PGM_EXECUTE 0x0003
234 #define PGM_PROTECTION 0x0004
235 #define PGM_ADDRESSING 0x0005
236 #define PGM_SPECIFICATION 0x0006
237 #define PGM_DATA 0x0007
238 #define PGM_FIXPT_OVERFLOW 0x0008
239 #define PGM_FIXPT_DIVIDE 0x0009
240 #define PGM_DEC_OVERFLOW 0x000a
241 #define PGM_DEC_DIVIDE 0x000b
242 #define PGM_HFP_EXP_OVERFLOW 0x000c
243 #define PGM_HFP_EXP_UNDERFLOW 0x000d
244 #define PGM_HFP_SIGNIFICANCE 0x000e
245 #define PGM_HFP_DIVIDE 0x000f
246 #define PGM_SEGMENT_TRANS 0x0010
247 #define PGM_PAGE_TRANS 0x0011
248 #define PGM_TRANS_SPEC 0x0012
249 #define PGM_SPECIAL_OP 0x0013
250 #define PGM_OPERAND 0x0015
251 #define PGM_TRACE_TABLE 0x0016
252 #define PGM_SPACE_SWITCH 0x001c
253 #define PGM_HFP_SQRT 0x001d
254 #define PGM_PC_TRANS_SPEC 0x001f
255 #define PGM_AFX_TRANS 0x0020
256 #define PGM_ASX_TRANS 0x0021
257 #define PGM_LX_TRANS 0x0022
258 #define PGM_EX_TRANS 0x0023
259 #define PGM_PRIM_AUTH 0x0024
260 #define PGM_SEC_AUTH 0x0025
261 #define PGM_ALET_SPEC 0x0028
262 #define PGM_ALEN_SPEC 0x0029
263 #define PGM_ALE_SEQ 0x002a
264 #define PGM_ASTE_VALID 0x002b
265 #define PGM_ASTE_SEQ 0x002c
266 #define PGM_EXT_AUTH 0x002d
267 #define PGM_STACK_FULL 0x0030
268 #define PGM_STACK_EMPTY 0x0031
269 #define PGM_STACK_SPEC 0x0032
270 #define PGM_STACK_TYPE 0x0033
271 #define PGM_STACK_OP 0x0034
272 #define PGM_ASCE_TYPE 0x0038
273 #define PGM_REG_FIRST_TRANS 0x0039
274 #define PGM_REG_SEC_TRANS 0x003a
275 #define PGM_REG_THIRD_TRANS 0x003b
276 #define PGM_MONITOR 0x0040
277 #define PGM_PER 0x0080
278 #define PGM_CRYPTO 0x0119
279
280 /* External Interrupts */
281 #define EXT_INTERRUPT_KEY 0x0040
282 #define EXT_CLOCK_COMP 0x1004
283 #define EXT_CPU_TIMER 0x1005
284 #define EXT_MALFUNCTION 0x1200
285 #define EXT_EMERGENCY 0x1201
286 #define EXT_EXTERNAL_CALL 0x1202
287 #define EXT_ETR 0x1406
288 #define EXT_SERVICE 0x2401
289 #define EXT_VIRTIO 0x2603
290
291 /* PSW defines */
292 #undef PSW_MASK_PER
293 #undef PSW_MASK_DAT
294 #undef PSW_MASK_IO
295 #undef PSW_MASK_EXT
296 #undef PSW_MASK_KEY
297 #undef PSW_SHIFT_KEY
298 #undef PSW_MASK_MCHECK
299 #undef PSW_MASK_WAIT
300 #undef PSW_MASK_PSTATE
301 #undef PSW_MASK_ASC
302 #undef PSW_MASK_CC
303 #undef PSW_MASK_PM
304 #undef PSW_MASK_64
305 #undef PSW_MASK_32
306 #undef PSW_MASK_ESA_ADDR
307
308 #define PSW_MASK_PER 0x4000000000000000ULL
309 #define PSW_MASK_DAT 0x0400000000000000ULL
310 #define PSW_MASK_IO 0x0200000000000000ULL
311 #define PSW_MASK_EXT 0x0100000000000000ULL
312 #define PSW_MASK_KEY 0x00F0000000000000ULL
313 #define PSW_SHIFT_KEY 56
314 #define PSW_MASK_MCHECK 0x0004000000000000ULL
315 #define PSW_MASK_WAIT 0x0002000000000000ULL
316 #define PSW_MASK_PSTATE 0x0001000000000000ULL
317 #define PSW_MASK_ASC 0x0000C00000000000ULL
318 #define PSW_MASK_CC 0x0000300000000000ULL
319 #define PSW_MASK_PM 0x00000F0000000000ULL
320 #define PSW_MASK_64 0x0000000100000000ULL
321 #define PSW_MASK_32 0x0000000080000000ULL
322 #define PSW_MASK_ESA_ADDR 0x000000007fffffffULL
323
324 #undef PSW_ASC_PRIMARY
325 #undef PSW_ASC_ACCREG
326 #undef PSW_ASC_SECONDARY
327 #undef PSW_ASC_HOME
328
329 #define PSW_ASC_PRIMARY 0x0000000000000000ULL
330 #define PSW_ASC_ACCREG 0x0000400000000000ULL
331 #define PSW_ASC_SECONDARY 0x0000800000000000ULL
332 #define PSW_ASC_HOME 0x0000C00000000000ULL
333
334 /* tb flags */
335
336 #define FLAG_MASK_PER (PSW_MASK_PER >> 32)
337 #define FLAG_MASK_DAT (PSW_MASK_DAT >> 32)
338 #define FLAG_MASK_IO (PSW_MASK_IO >> 32)
339 #define FLAG_MASK_EXT (PSW_MASK_EXT >> 32)
340 #define FLAG_MASK_KEY (PSW_MASK_KEY >> 32)
341 #define FLAG_MASK_MCHECK (PSW_MASK_MCHECK >> 32)
342 #define FLAG_MASK_WAIT (PSW_MASK_WAIT >> 32)
343 #define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> 32)
344 #define FLAG_MASK_ASC (PSW_MASK_ASC >> 32)
345 #define FLAG_MASK_CC (PSW_MASK_CC >> 32)
346 #define FLAG_MASK_PM (PSW_MASK_PM >> 32)
347 #define FLAG_MASK_64 (PSW_MASK_64 >> 32)
348 #define FLAG_MASK_32 0x00001000
349
350 /* Control register 0 bits */
351 #define CR0_LOWPROT 0x0000000010000000ULL
352 #define CR0_EDAT 0x0000000000800000ULL
353
354 /* MMU */
355 #define MMU_PRIMARY_IDX 0
356 #define MMU_SECONDARY_IDX 1
357 #define MMU_HOME_IDX 2
358
359 static inline int cpu_mmu_index (CPUS390XState *env, bool ifetch)
360 {
361 switch (env->psw.mask & PSW_MASK_ASC) {
362 case PSW_ASC_PRIMARY:
363 return MMU_PRIMARY_IDX;
364 case PSW_ASC_SECONDARY:
365 return MMU_SECONDARY_IDX;
366 case PSW_ASC_HOME:
367 return MMU_HOME_IDX;
368 case PSW_ASC_ACCREG:
369 /* Fallthrough: access register mode is not yet supported */
370 default:
371 abort();
372 }
373 }
374
375 static inline uint64_t cpu_mmu_idx_to_asc(int mmu_idx)
376 {
377 switch (mmu_idx) {
378 case MMU_PRIMARY_IDX:
379 return PSW_ASC_PRIMARY;
380 case MMU_SECONDARY_IDX:
381 return PSW_ASC_SECONDARY;
382 case MMU_HOME_IDX:
383 return PSW_ASC_HOME;
384 default:
385 abort();
386 }
387 }
388
389 static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
390 target_ulong *cs_base, uint32_t *flags)
391 {
392 *pc = env->psw.addr;
393 *cs_base = 0;
394 *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
395 ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
396 }
397
398 #define MAX_ILEN 6
399
400 /* While the PoO talks about ILC (a number between 1-3) what is actually
401 stored in LowCore is shifted left one bit (an even between 2-6). As
402 this is the actual length of the insn and therefore more useful, that
403 is what we want to pass around and manipulate. To make sure that we
404 have applied this distinction universally, rename the "ILC" to "ILEN". */
405 static inline int get_ilen(uint8_t opc)
406 {
407 switch (opc >> 6) {
408 case 0:
409 return 2;
410 case 1:
411 case 2:
412 return 4;
413 default:
414 return 6;
415 }
416 }
417
418 /* PER bits from control register 9 */
419 #define PER_CR9_EVENT_BRANCH 0x80000000
420 #define PER_CR9_EVENT_IFETCH 0x40000000
421 #define PER_CR9_EVENT_STORE 0x20000000
422 #define PER_CR9_EVENT_STORE_REAL 0x08000000
423 #define PER_CR9_EVENT_NULLIFICATION 0x01000000
424 #define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000
425 #define PER_CR9_CONTROL_ALTERATION 0x00200000
426
427 /* PER bits from the PER CODE/ATMID/AI in lowcore */
428 #define PER_CODE_EVENT_BRANCH 0x8000
429 #define PER_CODE_EVENT_IFETCH 0x4000
430 #define PER_CODE_EVENT_STORE 0x2000
431 #define PER_CODE_EVENT_STORE_REAL 0x0800
432 #define PER_CODE_EVENT_NULLIFICATION 0x0100
433
434 /* Compute the ATMID field that is stored in the per_perc_atmid lowcore
435 entry when a PER exception is triggered. */
436 static inline uint8_t get_per_atmid(CPUS390XState *env)
437 {
438 return ((env->psw.mask & PSW_MASK_64) ? (1 << 7) : 0) |
439 ( (1 << 6) ) |
440 ((env->psw.mask & PSW_MASK_32) ? (1 << 5) : 0) |
441 ((env->psw.mask & PSW_MASK_DAT)? (1 << 4) : 0) |
442 ((env->psw.mask & PSW_ASC_SECONDARY)? (1 << 3) : 0) |
443 ((env->psw.mask & PSW_ASC_ACCREG)? (1 << 2) : 0);
444 }
445
446 /* Check if an address is within the PER starting address and the PER
447 ending address. The address range might loop. */
448 static inline bool get_per_in_range(CPUS390XState *env, uint64_t addr)
449 {
450 if (env->cregs[10] <= env->cregs[11]) {
451 return env->cregs[10] <= addr && addr <= env->cregs[11];
452 } else {
453 return env->cregs[10] <= addr || addr <= env->cregs[11];
454 }
455 }
456
457 #ifndef CONFIG_USER_ONLY
458 /* In several cases of runtime exceptions, we havn't recorded the true
459 instruction length. Use these codes when raising exceptions in order
460 to re-compute the length by examining the insn in memory. */
461 #define ILEN_LATER 0x20
462 #define ILEN_LATER_INC 0x21
463 void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilen);
464 #endif
465
466 S390CPU *cpu_s390x_init(const char *cpu_model);
467 S390CPU *s390x_new_cpu(const char *cpu_model, int64_t id, Error **errp);
468 S390CPU *cpu_s390x_create(const char *cpu_model, Error **errp);
469 void s390x_translate_init(void);
470
471 /* you can call this signal handler from your SIGBUS and SIGSEGV
472 signal handlers to inform the virtual CPU of exceptions. non zero
473 is returned if the signal was handled by the virtual CPU. */
474 int cpu_s390x_signal_handler(int host_signum, void *pinfo,
475 void *puc);
476 int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
477 int mmu_idx);
478
479
480 #ifndef CONFIG_USER_ONLY
481 void do_restart_interrupt(CPUS390XState *env);
482
483 static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb,
484 uint8_t *ar)
485 {
486 hwaddr addr = 0;
487 uint8_t reg;
488
489 reg = ipb >> 28;
490 if (reg > 0) {
491 addr = env->regs[reg];
492 }
493 addr += (ipb >> 16) & 0xfff;
494 if (ar) {
495 *ar = reg;
496 }
497
498 return addr;
499 }
500
501 /* Base/displacement are at the same locations. */
502 #define decode_basedisp_rs decode_basedisp_s
503
504 /* helper functions for run_on_cpu() */
505 static inline void s390_do_cpu_reset(CPUState *cs, run_on_cpu_data arg)
506 {
507 S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
508
509 scc->cpu_reset(cs);
510 }
511 static inline void s390_do_cpu_full_reset(CPUState *cs, run_on_cpu_data arg)
512 {
513 cpu_reset(cs);
514 }
515
516 void s390x_tod_timer(void *opaque);
517 void s390x_cpu_timer(void *opaque);
518
519 int s390_virtio_hypercall(CPUS390XState *env);
520
521 #ifdef CONFIG_KVM
522 void kvm_s390_service_interrupt(uint32_t parm);
523 void kvm_s390_vcpu_interrupt(S390CPU *cpu, struct kvm_s390_irq *irq);
524 void kvm_s390_floating_interrupt(struct kvm_s390_irq *irq);
525 int kvm_s390_inject_flic(struct kvm_s390_irq *irq);
526 void kvm_s390_access_exception(S390CPU *cpu, uint16_t code, uint64_t te_code);
527 int kvm_s390_mem_op(S390CPU *cpu, vaddr addr, uint8_t ar, void *hostbuf,
528 int len, bool is_write);
529 int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_clock);
530 int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_clock);
531 #else
532 static inline void kvm_s390_service_interrupt(uint32_t parm)
533 {
534 }
535 static inline int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_low)
536 {
537 return -ENOSYS;
538 }
539 static inline int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_low)
540 {
541 return -ENOSYS;
542 }
543 static inline int kvm_s390_mem_op(S390CPU *cpu, vaddr addr, uint8_t ar,
544 void *hostbuf, int len, bool is_write)
545 {
546 return -ENOSYS;
547 }
548 static inline void kvm_s390_access_exception(S390CPU *cpu, uint16_t code,
549 uint64_t te_code)
550 {
551 }
552 #endif
553
554 static inline int s390_get_clock(uint8_t *tod_high, uint64_t *tod_low)
555 {
556 if (kvm_enabled()) {
557 return kvm_s390_get_clock(tod_high, tod_low);
558 }
559 /* Fixme TCG */
560 *tod_high = 0;
561 *tod_low = 0;
562 return 0;
563 }
564
565 static inline int s390_set_clock(uint8_t *tod_high, uint64_t *tod_low)
566 {
567 if (kvm_enabled()) {
568 return kvm_s390_set_clock(tod_high, tod_low);
569 }
570 /* Fixme TCG */
571 return 0;
572 }
573
574 S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
575 unsigned int s390_cpu_halt(S390CPU *cpu);
576 void s390_cpu_unhalt(S390CPU *cpu);
577 unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
578 static inline uint8_t s390_cpu_get_state(S390CPU *cpu)
579 {
580 return cpu->env.cpu_state;
581 }
582
583 void gtod_save(QEMUFile *f, void *opaque);
584 int gtod_load(QEMUFile *f, void *opaque, int version_id);
585
586 void cpu_inject_ext(S390CPU *cpu, uint32_t code, uint32_t param,
587 uint64_t param64);
588
589 /* ioinst.c */
590 void ioinst_handle_xsch(S390CPU *cpu, uint64_t reg1);
591 void ioinst_handle_csch(S390CPU *cpu, uint64_t reg1);
592 void ioinst_handle_hsch(S390CPU *cpu, uint64_t reg1);
593 void ioinst_handle_msch(S390CPU *cpu, uint64_t reg1, uint32_t ipb);
594 void ioinst_handle_ssch(S390CPU *cpu, uint64_t reg1, uint32_t ipb);
595 void ioinst_handle_stcrw(S390CPU *cpu, uint32_t ipb);
596 void ioinst_handle_stsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb);
597 int ioinst_handle_tsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb);
598 void ioinst_handle_chsc(S390CPU *cpu, uint32_t ipb);
599 int ioinst_handle_tpi(S390CPU *cpu, uint32_t ipb);
600 void ioinst_handle_schm(S390CPU *cpu, uint64_t reg1, uint64_t reg2,
601 uint32_t ipb);
602 void ioinst_handle_rsch(S390CPU *cpu, uint64_t reg1);
603 void ioinst_handle_rchp(S390CPU *cpu, uint64_t reg1);
604 void ioinst_handle_sal(S390CPU *cpu, uint64_t reg1);
605
606 /* service interrupts are floating therefore we must not pass an cpustate */
607 void s390_sclp_extint(uint32_t parm);
608
609 #else
610 static inline unsigned int s390_cpu_halt(S390CPU *cpu)
611 {
612 return 0;
613 }
614
615 static inline void s390_cpu_unhalt(S390CPU *cpu)
616 {
617 }
618
619 static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
620 {
621 return 0;
622 }
623 #endif
624
625 extern void subsystem_reset(void);
626
627 #define cpu_init(model) CPU(cpu_s390x_init(model))
628 #define cpu_signal_handler cpu_s390x_signal_handler
629
630 void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
631 #define cpu_list s390_cpu_list
632 void s390_cpu_model_register_props(Object *obj);
633 void s390_cpu_model_class_register_props(ObjectClass *oc);
634 void s390_realize_cpu_model(CPUState *cs, Error **errp);
635 ObjectClass *s390_cpu_class_by_name(const char *name);
636
637 #define EXCP_EXT 1 /* external interrupt */
638 #define EXCP_SVC 2 /* supervisor call (syscall) */
639 #define EXCP_PGM 3 /* program interruption */
640 #define EXCP_IO 7 /* I/O interrupt */
641 #define EXCP_MCHK 8 /* machine check */
642
643 #define INTERRUPT_EXT (1 << 0)
644 #define INTERRUPT_TOD (1 << 1)
645 #define INTERRUPT_CPUTIMER (1 << 2)
646 #define INTERRUPT_IO (1 << 3)
647 #define INTERRUPT_MCHK (1 << 4)
648
649 /* Program Status Word. */
650 #define S390_PSWM_REGNUM 0
651 #define S390_PSWA_REGNUM 1
652 /* General Purpose Registers. */
653 #define S390_R0_REGNUM 2
654 #define S390_R1_REGNUM 3
655 #define S390_R2_REGNUM 4
656 #define S390_R3_REGNUM 5
657 #define S390_R4_REGNUM 6
658 #define S390_R5_REGNUM 7
659 #define S390_R6_REGNUM 8
660 #define S390_R7_REGNUM 9
661 #define S390_R8_REGNUM 10
662 #define S390_R9_REGNUM 11
663 #define S390_R10_REGNUM 12
664 #define S390_R11_REGNUM 13
665 #define S390_R12_REGNUM 14
666 #define S390_R13_REGNUM 15
667 #define S390_R14_REGNUM 16
668 #define S390_R15_REGNUM 17
669 /* Total Core Registers. */
670 #define S390_NUM_CORE_REGS 18
671
672 /* CC optimization */
673
674 /* Instead of computing the condition codes after each x86 instruction,
675 * QEMU just stores the result (called CC_DST), the type of operation
676 * (called CC_OP) and whatever operands are needed (CC_SRC and possibly
677 * CC_VR). When the condition codes are needed, the condition codes can
678 * be calculated using this information. Condition codes are not generated
679 * if they are only needed for conditional branches.
680 */
681 enum cc_op {
682 CC_OP_CONST0 = 0, /* CC is 0 */
683 CC_OP_CONST1, /* CC is 1 */
684 CC_OP_CONST2, /* CC is 2 */
685 CC_OP_CONST3, /* CC is 3 */
686
687 CC_OP_DYNAMIC, /* CC calculation defined by env->cc_op */
688 CC_OP_STATIC, /* CC value is env->cc_op */
689
690 CC_OP_NZ, /* env->cc_dst != 0 */
691 CC_OP_LTGT_32, /* signed less/greater than (32bit) */
692 CC_OP_LTGT_64, /* signed less/greater than (64bit) */
693 CC_OP_LTUGTU_32, /* unsigned less/greater than (32bit) */
694 CC_OP_LTUGTU_64, /* unsigned less/greater than (64bit) */
695 CC_OP_LTGT0_32, /* signed less/greater than 0 (32bit) */
696 CC_OP_LTGT0_64, /* signed less/greater than 0 (64bit) */
697
698 CC_OP_ADD_64, /* overflow on add (64bit) */
699 CC_OP_ADDU_64, /* overflow on unsigned add (64bit) */
700 CC_OP_ADDC_64, /* overflow on unsigned add-carry (64bit) */
701 CC_OP_SUB_64, /* overflow on subtraction (64bit) */
702 CC_OP_SUBU_64, /* overflow on unsigned subtraction (64bit) */
703 CC_OP_SUBB_64, /* overflow on unsigned sub-borrow (64bit) */
704 CC_OP_ABS_64, /* sign eval on abs (64bit) */
705 CC_OP_NABS_64, /* sign eval on nabs (64bit) */
706
707 CC_OP_ADD_32, /* overflow on add (32bit) */
708 CC_OP_ADDU_32, /* overflow on unsigned add (32bit) */
709 CC_OP_ADDC_32, /* overflow on unsigned add-carry (32bit) */
710 CC_OP_SUB_32, /* overflow on subtraction (32bit) */
711 CC_OP_SUBU_32, /* overflow on unsigned subtraction (32bit) */
712 CC_OP_SUBB_32, /* overflow on unsigned sub-borrow (32bit) */
713 CC_OP_ABS_32, /* sign eval on abs (64bit) */
714 CC_OP_NABS_32, /* sign eval on nabs (64bit) */
715
716 CC_OP_COMP_32, /* complement */
717 CC_OP_COMP_64, /* complement */
718
719 CC_OP_TM_32, /* test under mask (32bit) */
720 CC_OP_TM_64, /* test under mask (64bit) */
721
722 CC_OP_NZ_F32, /* FP dst != 0 (32bit) */
723 CC_OP_NZ_F64, /* FP dst != 0 (64bit) */
724 CC_OP_NZ_F128, /* FP dst != 0 (128bit) */
725
726 CC_OP_ICM, /* insert characters under mask */
727 CC_OP_SLA_32, /* Calculate shift left signed (32bit) */
728 CC_OP_SLA_64, /* Calculate shift left signed (64bit) */
729 CC_OP_FLOGR, /* find leftmost one */
730 CC_OP_MAX
731 };
732
733 static const char *cc_names[] = {
734 [CC_OP_CONST0] = "CC_OP_CONST0",
735 [CC_OP_CONST1] = "CC_OP_CONST1",
736 [CC_OP_CONST2] = "CC_OP_CONST2",
737 [CC_OP_CONST3] = "CC_OP_CONST3",
738 [CC_OP_DYNAMIC] = "CC_OP_DYNAMIC",
739 [CC_OP_STATIC] = "CC_OP_STATIC",
740 [CC_OP_NZ] = "CC_OP_NZ",
741 [CC_OP_LTGT_32] = "CC_OP_LTGT_32",
742 [CC_OP_LTGT_64] = "CC_OP_LTGT_64",
743 [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
744 [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
745 [CC_OP_LTGT0_32] = "CC_OP_LTGT0_32",
746 [CC_OP_LTGT0_64] = "CC_OP_LTGT0_64",
747 [CC_OP_ADD_64] = "CC_OP_ADD_64",
748 [CC_OP_ADDU_64] = "CC_OP_ADDU_64",
749 [CC_OP_ADDC_64] = "CC_OP_ADDC_64",
750 [CC_OP_SUB_64] = "CC_OP_SUB_64",
751 [CC_OP_SUBU_64] = "CC_OP_SUBU_64",
752 [CC_OP_SUBB_64] = "CC_OP_SUBB_64",
753 [CC_OP_ABS_64] = "CC_OP_ABS_64",
754 [CC_OP_NABS_64] = "CC_OP_NABS_64",
755 [CC_OP_ADD_32] = "CC_OP_ADD_32",
756 [CC_OP_ADDU_32] = "CC_OP_ADDU_32",
757 [CC_OP_ADDC_32] = "CC_OP_ADDC_32",
758 [CC_OP_SUB_32] = "CC_OP_SUB_32",
759 [CC_OP_SUBU_32] = "CC_OP_SUBU_32",
760 [CC_OP_SUBB_32] = "CC_OP_SUBB_32",
761 [CC_OP_ABS_32] = "CC_OP_ABS_32",
762 [CC_OP_NABS_32] = "CC_OP_NABS_32",
763 [CC_OP_COMP_32] = "CC_OP_COMP_32",
764 [CC_OP_COMP_64] = "CC_OP_COMP_64",
765 [CC_OP_TM_32] = "CC_OP_TM_32",
766 [CC_OP_TM_64] = "CC_OP_TM_64",
767 [CC_OP_NZ_F32] = "CC_OP_NZ_F32",
768 [CC_OP_NZ_F64] = "CC_OP_NZ_F64",
769 [CC_OP_NZ_F128] = "CC_OP_NZ_F128",
770 [CC_OP_ICM] = "CC_OP_ICM",
771 [CC_OP_SLA_32] = "CC_OP_SLA_32",
772 [CC_OP_SLA_64] = "CC_OP_SLA_64",
773 [CC_OP_FLOGR] = "CC_OP_FLOGR",
774 };
775
776 static inline const char *cc_name(int cc_op)
777 {
778 return cc_names[cc_op];
779 }
780
781 static inline void setcc(S390CPU *cpu, uint64_t cc)
782 {
783 CPUS390XState *env = &cpu->env;
784
785 env->psw.mask &= ~(3ull << 44);
786 env->psw.mask |= (cc & 3) << 44;
787 env->cc_op = cc;
788 }
789
790 typedef struct LowCore
791 {
792 /* prefix area: defined by architecture */
793 uint32_t ccw1[2]; /* 0x000 */
794 uint32_t ccw2[4]; /* 0x008 */
795 uint8_t pad1[0x80-0x18]; /* 0x018 */
796 uint32_t ext_params; /* 0x080 */
797 uint16_t cpu_addr; /* 0x084 */
798 uint16_t ext_int_code; /* 0x086 */
799 uint16_t svc_ilen; /* 0x088 */
800 uint16_t svc_code; /* 0x08a */
801 uint16_t pgm_ilen; /* 0x08c */
802 uint16_t pgm_code; /* 0x08e */
803 uint32_t data_exc_code; /* 0x090 */
804 uint16_t mon_class_num; /* 0x094 */
805 uint16_t per_perc_atmid; /* 0x096 */
806 uint64_t per_address; /* 0x098 */
807 uint8_t exc_access_id; /* 0x0a0 */
808 uint8_t per_access_id; /* 0x0a1 */
809 uint8_t op_access_id; /* 0x0a2 */
810 uint8_t ar_access_id; /* 0x0a3 */
811 uint8_t pad2[0xA8-0xA4]; /* 0x0a4 */
812 uint64_t trans_exc_code; /* 0x0a8 */
813 uint64_t monitor_code; /* 0x0b0 */
814 uint16_t subchannel_id; /* 0x0b8 */
815 uint16_t subchannel_nr; /* 0x0ba */
816 uint32_t io_int_parm; /* 0x0bc */
817 uint32_t io_int_word; /* 0x0c0 */
818 uint8_t pad3[0xc8-0xc4]; /* 0x0c4 */
819 uint32_t stfl_fac_list; /* 0x0c8 */
820 uint8_t pad4[0xe8-0xcc]; /* 0x0cc */
821 uint32_t mcck_interruption_code[2]; /* 0x0e8 */
822 uint8_t pad5[0xf4-0xf0]; /* 0x0f0 */
823 uint32_t external_damage_code; /* 0x0f4 */
824 uint64_t failing_storage_address; /* 0x0f8 */
825 uint8_t pad6[0x110-0x100]; /* 0x100 */
826 uint64_t per_breaking_event_addr; /* 0x110 */
827 uint8_t pad7[0x120-0x118]; /* 0x118 */
828 PSW restart_old_psw; /* 0x120 */
829 PSW external_old_psw; /* 0x130 */
830 PSW svc_old_psw; /* 0x140 */
831 PSW program_old_psw; /* 0x150 */
832 PSW mcck_old_psw; /* 0x160 */
833 PSW io_old_psw; /* 0x170 */
834 uint8_t pad8[0x1a0-0x180]; /* 0x180 */
835 PSW restart_new_psw; /* 0x1a0 */
836 PSW external_new_psw; /* 0x1b0 */
837 PSW svc_new_psw; /* 0x1c0 */
838 PSW program_new_psw; /* 0x1d0 */
839 PSW mcck_new_psw; /* 0x1e0 */
840 PSW io_new_psw; /* 0x1f0 */
841 PSW return_psw; /* 0x200 */
842 uint8_t irb[64]; /* 0x210 */
843 uint64_t sync_enter_timer; /* 0x250 */
844 uint64_t async_enter_timer; /* 0x258 */
845 uint64_t exit_timer; /* 0x260 */
846 uint64_t last_update_timer; /* 0x268 */
847 uint64_t user_timer; /* 0x270 */
848 uint64_t system_timer; /* 0x278 */
849 uint64_t last_update_clock; /* 0x280 */
850 uint64_t steal_clock; /* 0x288 */
851 PSW return_mcck_psw; /* 0x290 */
852 uint8_t pad9[0xc00-0x2a0]; /* 0x2a0 */
853 /* System info area */
854 uint64_t save_area[16]; /* 0xc00 */
855 uint8_t pad10[0xd40-0xc80]; /* 0xc80 */
856 uint64_t kernel_stack; /* 0xd40 */
857 uint64_t thread_info; /* 0xd48 */
858 uint64_t async_stack; /* 0xd50 */
859 uint64_t kernel_asce; /* 0xd58 */
860 uint64_t user_asce; /* 0xd60 */
861 uint64_t panic_stack; /* 0xd68 */
862 uint64_t user_exec_asce; /* 0xd70 */
863 uint8_t pad11[0xdc0-0xd78]; /* 0xd78 */
864
865 /* SMP info area: defined by DJB */
866 uint64_t clock_comparator; /* 0xdc0 */
867 uint64_t ext_call_fast; /* 0xdc8 */
868 uint64_t percpu_offset; /* 0xdd0 */
869 uint64_t current_task; /* 0xdd8 */
870 uint32_t softirq_pending; /* 0xde0 */
871 uint32_t pad_0x0de4; /* 0xde4 */
872 uint64_t int_clock; /* 0xde8 */
873 uint8_t pad12[0xe00-0xdf0]; /* 0xdf0 */
874
875 /* 0xe00 is used as indicator for dump tools */
876 /* whether the kernel died with panic() or not */
877 uint32_t panic_magic; /* 0xe00 */
878
879 uint8_t pad13[0x11b8-0xe04]; /* 0xe04 */
880
881 /* 64 bit extparam used for pfault, diag 250 etc */
882 uint64_t ext_params2; /* 0x11B8 */
883
884 uint8_t pad14[0x1200-0x11C0]; /* 0x11C0 */
885
886 /* System info area */
887
888 uint64_t floating_pt_save_area[16]; /* 0x1200 */
889 uint64_t gpregs_save_area[16]; /* 0x1280 */
890 uint32_t st_status_fixed_logout[4]; /* 0x1300 */
891 uint8_t pad15[0x1318-0x1310]; /* 0x1310 */
892 uint32_t prefixreg_save_area; /* 0x1318 */
893 uint32_t fpt_creg_save_area; /* 0x131c */
894 uint8_t pad16[0x1324-0x1320]; /* 0x1320 */
895 uint32_t tod_progreg_save_area; /* 0x1324 */
896 uint32_t cpu_timer_save_area[2]; /* 0x1328 */
897 uint32_t clock_comp_save_area[2]; /* 0x1330 */
898 uint8_t pad17[0x1340-0x1338]; /* 0x1338 */
899 uint32_t access_regs_save_area[16]; /* 0x1340 */
900 uint64_t cregs_save_area[16]; /* 0x1380 */
901
902 /* align to the top of the prefix area */
903
904 uint8_t pad18[0x2000-0x1400]; /* 0x1400 */
905 } QEMU_PACKED LowCore;
906
907 /* STSI */
908 #define STSI_LEVEL_MASK 0x00000000f0000000ULL
909 #define STSI_LEVEL_CURRENT 0x0000000000000000ULL
910 #define STSI_LEVEL_1 0x0000000010000000ULL
911 #define STSI_LEVEL_2 0x0000000020000000ULL
912 #define STSI_LEVEL_3 0x0000000030000000ULL
913 #define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL
914 #define STSI_R0_SEL1_MASK 0x00000000000000ffULL
915 #define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL
916 #define STSI_R1_SEL2_MASK 0x000000000000ffffULL
917
918 /* Basic Machine Configuration */
919 struct sysib_111 {
920 uint32_t res1[8];
921 uint8_t manuf[16];
922 uint8_t type[4];
923 uint8_t res2[12];
924 uint8_t model[16];
925 uint8_t sequence[16];
926 uint8_t plant[4];
927 uint8_t res3[156];
928 };
929
930 /* Basic Machine CPU */
931 struct sysib_121 {
932 uint32_t res1[80];
933 uint8_t sequence[16];
934 uint8_t plant[4];
935 uint8_t res2[2];
936 uint16_t cpu_addr;
937 uint8_t res3[152];
938 };
939
940 /* Basic Machine CPUs */
941 struct sysib_122 {
942 uint8_t res1[32];
943 uint32_t capability;
944 uint16_t total_cpus;
945 uint16_t active_cpus;
946 uint16_t standby_cpus;
947 uint16_t reserved_cpus;
948 uint16_t adjustments[2026];
949 };
950
951 /* LPAR CPU */
952 struct sysib_221 {
953 uint32_t res1[80];
954 uint8_t sequence[16];
955 uint8_t plant[4];
956 uint16_t cpu_id;
957 uint16_t cpu_addr;
958 uint8_t res3[152];
959 };
960
961 /* LPAR CPUs */
962 struct sysib_222 {
963 uint32_t res1[32];
964 uint16_t lpar_num;
965 uint8_t res2;
966 uint8_t lcpuc;
967 uint16_t total_cpus;
968 uint16_t conf_cpus;
969 uint16_t standby_cpus;
970 uint16_t reserved_cpus;
971 uint8_t name[8];
972 uint32_t caf;
973 uint8_t res3[16];
974 uint16_t dedicated_cpus;
975 uint16_t shared_cpus;
976 uint8_t res4[180];
977 };
978
979 /* VM CPUs */
980 struct sysib_322 {
981 uint8_t res1[31];
982 uint8_t count;
983 struct {
984 uint8_t res2[4];
985 uint16_t total_cpus;
986 uint16_t conf_cpus;
987 uint16_t standby_cpus;
988 uint16_t reserved_cpus;
989 uint8_t name[8];
990 uint32_t caf;
991 uint8_t cpi[16];
992 uint8_t res5[3];
993 uint8_t ext_name_encoding;
994 uint32_t res3;
995 uint8_t uuid[16];
996 } vm[8];
997 uint8_t res4[1504];
998 uint8_t ext_names[8][256];
999 };
1000
1001 /* MMU defines */
1002 #define _ASCE_ORIGIN ~0xfffULL /* segment table origin */
1003 #define _ASCE_SUBSPACE 0x200 /* subspace group control */
1004 #define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
1005 #define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
1006 #define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
1007 #define _ASCE_REAL_SPACE 0x20 /* real space control */
1008 #define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
1009 #define _ASCE_TYPE_REGION1 0x0c /* region first table type */
1010 #define _ASCE_TYPE_REGION2 0x08 /* region second table type */
1011 #define _ASCE_TYPE_REGION3 0x04 /* region third table type */
1012 #define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
1013 #define _ASCE_TABLE_LENGTH 0x03 /* region table length */
1014
1015 #define _REGION_ENTRY_ORIGIN ~0xfffULL /* region/segment table origin */
1016 #define _REGION_ENTRY_RO 0x200 /* region/segment protection bit */
1017 #define _REGION_ENTRY_TF 0xc0 /* region/segment table offset */
1018 #define _REGION_ENTRY_INV 0x20 /* invalid region table entry */
1019 #define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
1020 #define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
1021 #define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
1022 #define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
1023 #define _REGION_ENTRY_LENGTH 0x03 /* region third length */
1024
1025 #define _SEGMENT_ENTRY_ORIGIN ~0x7ffULL /* segment table origin */
1026 #define _SEGMENT_ENTRY_FC 0x400 /* format control */
1027 #define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
1028 #define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
1029
1030 #define _PAGE_RO 0x200 /* HW read-only bit */
1031 #define _PAGE_INVALID 0x400 /* HW invalid bit */
1032 #define _PAGE_RES0 0x800 /* bit must be zero */
1033
1034 #define SK_C (0x1 << 1)
1035 #define SK_R (0x1 << 2)
1036 #define SK_F (0x1 << 3)
1037 #define SK_ACC_MASK (0xf << 4)
1038
1039 /* SIGP order codes */
1040 #define SIGP_SENSE 0x01
1041 #define SIGP_EXTERNAL_CALL 0x02
1042 #define SIGP_EMERGENCY 0x03
1043 #define SIGP_START 0x04
1044 #define SIGP_STOP 0x05
1045 #define SIGP_RESTART 0x06
1046 #define SIGP_STOP_STORE_STATUS 0x09
1047 #define SIGP_INITIAL_CPU_RESET 0x0b
1048 #define SIGP_CPU_RESET 0x0c
1049 #define SIGP_SET_PREFIX 0x0d
1050 #define SIGP_STORE_STATUS_ADDR 0x0e
1051 #define SIGP_SET_ARCH 0x12
1052 #define SIGP_STORE_ADTL_STATUS 0x17
1053
1054 /* SIGP condition codes */
1055 #define SIGP_CC_ORDER_CODE_ACCEPTED 0
1056 #define SIGP_CC_STATUS_STORED 1
1057 #define SIGP_CC_BUSY 2
1058 #define SIGP_CC_NOT_OPERATIONAL 3
1059
1060 /* SIGP status bits */
1061 #define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL
1062 #define SIGP_STAT_INCORRECT_STATE 0x00000200UL
1063 #define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
1064 #define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL
1065 #define SIGP_STAT_STOPPED 0x00000040UL
1066 #define SIGP_STAT_OPERATOR_INTERV 0x00000020UL
1067 #define SIGP_STAT_CHECK_STOP 0x00000010UL
1068 #define SIGP_STAT_INOPERATIVE 0x00000004UL
1069 #define SIGP_STAT_INVALID_ORDER 0x00000002UL
1070 #define SIGP_STAT_RECEIVER_CHECK 0x00000001UL
1071
1072 /* SIGP SET ARCHITECTURE modes */
1073 #define SIGP_MODE_ESA_S390 0
1074 #define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1
1075 #define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2
1076
1077 void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
1078 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
1079 target_ulong *raddr, int *flags, bool exc);
1080 int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code);
1081 uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
1082 uint64_t vr);
1083 void s390_cpu_recompute_watchpoints(CPUState *cs);
1084
1085 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
1086 int len, bool is_write);
1087
1088 #define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len) \
1089 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false)
1090 #define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \
1091 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true)
1092 #define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \
1093 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true)
1094
1095 /* The value of the TOD clock for 1.1.1970. */
1096 #define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
1097
1098 /* Converts ns to s390's clock format */
1099 static inline uint64_t time2tod(uint64_t ns) {
1100 return (ns << 9) / 125;
1101 }
1102
1103 /* Converts s390's clock format to ns */
1104 static inline uint64_t tod2time(uint64_t t) {
1105 return (t * 125) >> 9;
1106 }
1107
1108 /* from s390-virtio-ccw */
1109 #define MEM_SECTION_SIZE 0x10000000UL
1110 #define MAX_AVAIL_SLOTS 32
1111
1112 /* fpu_helper.c */
1113 uint32_t set_cc_nz_f32(float32 v);
1114 uint32_t set_cc_nz_f64(float64 v);
1115 uint32_t set_cc_nz_f128(float128 v);
1116
1117 /* misc_helper.c */
1118 #ifndef CONFIG_USER_ONLY
1119 int handle_diag_288(CPUS390XState *env, uint64_t r1, uint64_t r3);
1120 void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3);
1121 #endif
1122 void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
1123 void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
1124 uintptr_t retaddr);
1125
1126 #ifdef CONFIG_KVM
1127 void kvm_s390_io_interrupt(uint16_t subchannel_id,
1128 uint16_t subchannel_nr, uint32_t io_int_parm,
1129 uint32_t io_int_word);
1130 void kvm_s390_crw_mchk(void);
1131 void kvm_s390_enable_css_support(S390CPU *cpu);
1132 int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch,
1133 int vq, bool assign);
1134 int kvm_s390_cpu_restart(S390CPU *cpu);
1135 int kvm_s390_get_memslot_count(KVMState *s);
1136 void kvm_s390_cmma_reset(void);
1137 int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state);
1138 void kvm_s390_reset_vcpu(S390CPU *cpu);
1139 int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit, uint64_t *hw_limit);
1140 void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu);
1141 int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu);
1142 int kvm_s390_get_ri(void);
1143 void kvm_s390_crypto_reset(void);
1144 #else
1145 static inline void kvm_s390_io_interrupt(uint16_t subchannel_id,
1146 uint16_t subchannel_nr,
1147 uint32_t io_int_parm,
1148 uint32_t io_int_word)
1149 {
1150 }
1151 static inline void kvm_s390_crw_mchk(void)
1152 {
1153 }
1154 static inline void kvm_s390_enable_css_support(S390CPU *cpu)
1155 {
1156 }
1157 static inline int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier,
1158 uint32_t sch, int vq,
1159 bool assign)
1160 {
1161 return -ENOSYS;
1162 }
1163 static inline int kvm_s390_cpu_restart(S390CPU *cpu)
1164 {
1165 return -ENOSYS;
1166 }
1167 static inline void kvm_s390_cmma_reset(void)
1168 {
1169 }
1170 static inline int kvm_s390_get_memslot_count(KVMState *s)
1171 {
1172 return MAX_AVAIL_SLOTS;
1173 }
1174 static inline int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state)
1175 {
1176 return -ENOSYS;
1177 }
1178 static inline void kvm_s390_reset_vcpu(S390CPU *cpu)
1179 {
1180 }
1181 static inline int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit,
1182 uint64_t *hw_limit)
1183 {
1184 return 0;
1185 }
1186 static inline void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu)
1187 {
1188 }
1189 static inline int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu)
1190 {
1191 return 0;
1192 }
1193 static inline int kvm_s390_get_ri(void)
1194 {
1195 return 0;
1196 }
1197 static inline void kvm_s390_crypto_reset(void)
1198 {
1199 }
1200 #endif
1201
1202 static inline int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit)
1203 {
1204 if (kvm_enabled()) {
1205 return kvm_s390_set_mem_limit(kvm_state, new_limit, hw_limit);
1206 }
1207 return 0;
1208 }
1209
1210 static inline void s390_cmma_reset(void)
1211 {
1212 if (kvm_enabled()) {
1213 kvm_s390_cmma_reset();
1214 }
1215 }
1216
1217 static inline int s390_cpu_restart(S390CPU *cpu)
1218 {
1219 if (kvm_enabled()) {
1220 return kvm_s390_cpu_restart(cpu);
1221 }
1222 return -ENOSYS;
1223 }
1224
1225 static inline int s390_get_memslot_count(KVMState *s)
1226 {
1227 if (kvm_enabled()) {
1228 return kvm_s390_get_memslot_count(s);
1229 } else {
1230 return MAX_AVAIL_SLOTS;
1231 }
1232 }
1233
1234 void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr,
1235 uint32_t io_int_parm, uint32_t io_int_word);
1236 void s390_crw_mchk(void);
1237
1238 static inline int s390_assign_subch_ioeventfd(EventNotifier *notifier,
1239 uint32_t sch_id, int vq,
1240 bool assign)
1241 {
1242 return kvm_s390_assign_subch_ioeventfd(notifier, sch_id, vq, assign);
1243 }
1244
1245 static inline void s390_crypto_reset(void)
1246 {
1247 if (kvm_enabled()) {
1248 kvm_s390_crypto_reset();
1249 }
1250 }
1251
1252 /* machine check interruption code */
1253
1254 /* subclasses */
1255 #define MCIC_SC_SD 0x8000000000000000ULL
1256 #define MCIC_SC_PD 0x4000000000000000ULL
1257 #define MCIC_SC_SR 0x2000000000000000ULL
1258 #define MCIC_SC_CD 0x0800000000000000ULL
1259 #define MCIC_SC_ED 0x0400000000000000ULL
1260 #define MCIC_SC_DG 0x0100000000000000ULL
1261 #define MCIC_SC_W 0x0080000000000000ULL
1262 #define MCIC_SC_CP 0x0040000000000000ULL
1263 #define MCIC_SC_SP 0x0020000000000000ULL
1264 #define MCIC_SC_CK 0x0010000000000000ULL
1265
1266 /* subclass modifiers */
1267 #define MCIC_SCM_B 0x0002000000000000ULL
1268 #define MCIC_SCM_DA 0x0000000020000000ULL
1269 #define MCIC_SCM_AP 0x0000000000080000ULL
1270
1271 /* storage errors */
1272 #define MCIC_SE_SE 0x0000800000000000ULL
1273 #define MCIC_SE_SC 0x0000400000000000ULL
1274 #define MCIC_SE_KE 0x0000200000000000ULL
1275 #define MCIC_SE_DS 0x0000100000000000ULL
1276 #define MCIC_SE_IE 0x0000000080000000ULL
1277
1278 /* validity bits */
1279 #define MCIC_VB_WP 0x0000080000000000ULL
1280 #define MCIC_VB_MS 0x0000040000000000ULL
1281 #define MCIC_VB_PM 0x0000020000000000ULL
1282 #define MCIC_VB_IA 0x0000010000000000ULL
1283 #define MCIC_VB_FA 0x0000008000000000ULL
1284 #define MCIC_VB_VR 0x0000004000000000ULL
1285 #define MCIC_VB_EC 0x0000002000000000ULL
1286 #define MCIC_VB_FP 0x0000001000000000ULL
1287 #define MCIC_VB_GR 0x0000000800000000ULL
1288 #define MCIC_VB_CR 0x0000000400000000ULL
1289 #define MCIC_VB_ST 0x0000000100000000ULL
1290 #define MCIC_VB_AR 0x0000000040000000ULL
1291 #define MCIC_VB_PR 0x0000000000200000ULL
1292 #define MCIC_VB_FC 0x0000000000100000ULL
1293 #define MCIC_VB_CT 0x0000000000020000ULL
1294 #define MCIC_VB_CC 0x0000000000010000ULL
1295
1296 #endif