Update version for v6.2.0-rc4 release
[qemu.git] / target / s390x / mmu_helper.c
1 /*
2 * S390x MMU related functions
3 *
4 * Copyright (c) 2011 Alexander Graf
5 * Copyright (c) 2015 Thomas Huth, IBM Corporation
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include "qemu/osdep.h"
19 #include "qemu/error-report.h"
20 #include "exec/address-spaces.h"
21 #include "cpu.h"
22 #include "internal.h"
23 #include "kvm_s390x.h"
24 #include "sysemu/kvm.h"
25 #include "sysemu/tcg.h"
26 #include "exec/exec-all.h"
27 #include "trace.h"
28 #include "hw/hw.h"
29 #include "hw/s390x/storage-keys.h"
30 #include "hw/boards.h"
31
32 /* Fetch/store bits in the translation exception code: */
33 #define FS_READ 0x800
34 #define FS_WRITE 0x400
35
36 static void trigger_access_exception(CPUS390XState *env, uint32_t type,
37 uint64_t tec)
38 {
39 S390CPU *cpu = env_archcpu(env);
40
41 if (kvm_enabled()) {
42 kvm_s390_access_exception(cpu, type, tec);
43 } else {
44 CPUState *cs = env_cpu(env);
45 if (type != PGM_ADDRESSING) {
46 stq_phys(cs->as, env->psa + offsetof(LowCore, trans_exc_code), tec);
47 }
48 trigger_pgm_exception(env, type);
49 }
50 }
51
52 /* check whether the address would be proteted by Low-Address Protection */
53 static bool is_low_address(uint64_t addr)
54 {
55 return addr <= 511 || (addr >= 4096 && addr <= 4607);
56 }
57
58 /* check whether Low-Address Protection is enabled for mmu_translate() */
59 static bool lowprot_enabled(const CPUS390XState *env, uint64_t asc)
60 {
61 if (!(env->cregs[0] & CR0_LOWPROT)) {
62 return false;
63 }
64 if (!(env->psw.mask & PSW_MASK_DAT)) {
65 return true;
66 }
67
68 /* Check the private-space control bit */
69 switch (asc) {
70 case PSW_ASC_PRIMARY:
71 return !(env->cregs[1] & ASCE_PRIVATE_SPACE);
72 case PSW_ASC_SECONDARY:
73 return !(env->cregs[7] & ASCE_PRIVATE_SPACE);
74 case PSW_ASC_HOME:
75 return !(env->cregs[13] & ASCE_PRIVATE_SPACE);
76 default:
77 /* We don't support access register mode */
78 error_report("unsupported addressing mode");
79 exit(1);
80 }
81 }
82
83 /**
84 * Translate real address to absolute (= physical)
85 * address by taking care of the prefix mapping.
86 */
87 target_ulong mmu_real2abs(CPUS390XState *env, target_ulong raddr)
88 {
89 if (raddr < 0x2000) {
90 return raddr + env->psa; /* Map the lowcore. */
91 } else if (raddr >= env->psa && raddr < env->psa + 0x2000) {
92 return raddr - env->psa; /* Map the 0 page. */
93 }
94 return raddr;
95 }
96
97 static inline bool read_table_entry(CPUS390XState *env, hwaddr gaddr,
98 uint64_t *entry)
99 {
100 CPUState *cs = env_cpu(env);
101
102 /*
103 * According to the PoP, these table addresses are "unpredictably real
104 * or absolute". Also, "it is unpredictable whether the address wraps
105 * or an addressing exception is recognized".
106 *
107 * We treat them as absolute addresses and don't wrap them.
108 */
109 if (unlikely(address_space_read(cs->as, gaddr, MEMTXATTRS_UNSPECIFIED,
110 entry, sizeof(*entry)) !=
111 MEMTX_OK)) {
112 return false;
113 }
114 *entry = be64_to_cpu(*entry);
115 return true;
116 }
117
118 static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
119 uint64_t asc, uint64_t asce, target_ulong *raddr,
120 int *flags, int rw)
121 {
122 const bool edat1 = (env->cregs[0] & CR0_EDAT) &&
123 s390_has_feat(S390_FEAT_EDAT);
124 const bool edat2 = edat1 && s390_has_feat(S390_FEAT_EDAT_2);
125 const bool iep = (env->cregs[0] & CR0_IEP) &&
126 s390_has_feat(S390_FEAT_INSTRUCTION_EXEC_PROT);
127 const int asce_tl = asce & ASCE_TABLE_LENGTH;
128 const int asce_p = asce & ASCE_PRIVATE_SPACE;
129 hwaddr gaddr = asce & ASCE_ORIGIN;
130 uint64_t entry;
131
132 if (asce & ASCE_REAL_SPACE) {
133 /* direct mapping */
134 *raddr = vaddr;
135 return 0;
136 }
137
138 switch (asce & ASCE_TYPE_MASK) {
139 case ASCE_TYPE_REGION1:
140 if (VADDR_REGION1_TL(vaddr) > asce_tl) {
141 return PGM_REG_FIRST_TRANS;
142 }
143 gaddr += VADDR_REGION1_TX(vaddr) * 8;
144 break;
145 case ASCE_TYPE_REGION2:
146 if (VADDR_REGION1_TX(vaddr)) {
147 return PGM_ASCE_TYPE;
148 }
149 if (VADDR_REGION2_TL(vaddr) > asce_tl) {
150 return PGM_REG_SEC_TRANS;
151 }
152 gaddr += VADDR_REGION2_TX(vaddr) * 8;
153 break;
154 case ASCE_TYPE_REGION3:
155 if (VADDR_REGION1_TX(vaddr) || VADDR_REGION2_TX(vaddr)) {
156 return PGM_ASCE_TYPE;
157 }
158 if (VADDR_REGION3_TL(vaddr) > asce_tl) {
159 return PGM_REG_THIRD_TRANS;
160 }
161 gaddr += VADDR_REGION3_TX(vaddr) * 8;
162 break;
163 case ASCE_TYPE_SEGMENT:
164 if (VADDR_REGION1_TX(vaddr) || VADDR_REGION2_TX(vaddr) ||
165 VADDR_REGION3_TX(vaddr)) {
166 return PGM_ASCE_TYPE;
167 }
168 if (VADDR_SEGMENT_TL(vaddr) > asce_tl) {
169 return PGM_SEGMENT_TRANS;
170 }
171 gaddr += VADDR_SEGMENT_TX(vaddr) * 8;
172 break;
173 }
174
175 switch (asce & ASCE_TYPE_MASK) {
176 case ASCE_TYPE_REGION1:
177 if (!read_table_entry(env, gaddr, &entry)) {
178 return PGM_ADDRESSING;
179 }
180 if (entry & REGION_ENTRY_I) {
181 return PGM_REG_FIRST_TRANS;
182 }
183 if ((entry & REGION_ENTRY_TT) != REGION_ENTRY_TT_REGION1) {
184 return PGM_TRANS_SPEC;
185 }
186 if (VADDR_REGION2_TL(vaddr) < (entry & REGION_ENTRY_TF) >> 6 ||
187 VADDR_REGION2_TL(vaddr) > (entry & REGION_ENTRY_TL)) {
188 return PGM_REG_SEC_TRANS;
189 }
190 if (edat1 && (entry & REGION_ENTRY_P)) {
191 *flags &= ~PAGE_WRITE;
192 }
193 gaddr = (entry & REGION_ENTRY_ORIGIN) + VADDR_REGION2_TX(vaddr) * 8;
194 /* fall through */
195 case ASCE_TYPE_REGION2:
196 if (!read_table_entry(env, gaddr, &entry)) {
197 return PGM_ADDRESSING;
198 }
199 if (entry & REGION_ENTRY_I) {
200 return PGM_REG_SEC_TRANS;
201 }
202 if ((entry & REGION_ENTRY_TT) != REGION_ENTRY_TT_REGION2) {
203 return PGM_TRANS_SPEC;
204 }
205 if (VADDR_REGION3_TL(vaddr) < (entry & REGION_ENTRY_TF) >> 6 ||
206 VADDR_REGION3_TL(vaddr) > (entry & REGION_ENTRY_TL)) {
207 return PGM_REG_THIRD_TRANS;
208 }
209 if (edat1 && (entry & REGION_ENTRY_P)) {
210 *flags &= ~PAGE_WRITE;
211 }
212 gaddr = (entry & REGION_ENTRY_ORIGIN) + VADDR_REGION3_TX(vaddr) * 8;
213 /* fall through */
214 case ASCE_TYPE_REGION3:
215 if (!read_table_entry(env, gaddr, &entry)) {
216 return PGM_ADDRESSING;
217 }
218 if (entry & REGION_ENTRY_I) {
219 return PGM_REG_THIRD_TRANS;
220 }
221 if ((entry & REGION_ENTRY_TT) != REGION_ENTRY_TT_REGION3) {
222 return PGM_TRANS_SPEC;
223 }
224 if (edat2 && (entry & REGION3_ENTRY_CR) && asce_p) {
225 return PGM_TRANS_SPEC;
226 }
227 if (edat1 && (entry & REGION_ENTRY_P)) {
228 *flags &= ~PAGE_WRITE;
229 }
230 if (edat2 && (entry & REGION3_ENTRY_FC)) {
231 if (iep && (entry & REGION3_ENTRY_IEP)) {
232 *flags &= ~PAGE_EXEC;
233 }
234 *raddr = (entry & REGION3_ENTRY_RFAA) |
235 (vaddr & ~REGION3_ENTRY_RFAA);
236 return 0;
237 }
238 if (VADDR_SEGMENT_TL(vaddr) < (entry & REGION_ENTRY_TF) >> 6 ||
239 VADDR_SEGMENT_TL(vaddr) > (entry & REGION_ENTRY_TL)) {
240 return PGM_SEGMENT_TRANS;
241 }
242 gaddr = (entry & REGION_ENTRY_ORIGIN) + VADDR_SEGMENT_TX(vaddr) * 8;
243 /* fall through */
244 case ASCE_TYPE_SEGMENT:
245 if (!read_table_entry(env, gaddr, &entry)) {
246 return PGM_ADDRESSING;
247 }
248 if (entry & SEGMENT_ENTRY_I) {
249 return PGM_SEGMENT_TRANS;
250 }
251 if ((entry & SEGMENT_ENTRY_TT) != SEGMENT_ENTRY_TT_SEGMENT) {
252 return PGM_TRANS_SPEC;
253 }
254 if ((entry & SEGMENT_ENTRY_CS) && asce_p) {
255 return PGM_TRANS_SPEC;
256 }
257 if (entry & SEGMENT_ENTRY_P) {
258 *flags &= ~PAGE_WRITE;
259 }
260 if (edat1 && (entry & SEGMENT_ENTRY_FC)) {
261 if (iep && (entry & SEGMENT_ENTRY_IEP)) {
262 *flags &= ~PAGE_EXEC;
263 }
264 *raddr = (entry & SEGMENT_ENTRY_SFAA) |
265 (vaddr & ~SEGMENT_ENTRY_SFAA);
266 return 0;
267 }
268 gaddr = (entry & SEGMENT_ENTRY_ORIGIN) + VADDR_PAGE_TX(vaddr) * 8;
269 break;
270 }
271
272 if (!read_table_entry(env, gaddr, &entry)) {
273 return PGM_ADDRESSING;
274 }
275 if (entry & PAGE_ENTRY_I) {
276 return PGM_PAGE_TRANS;
277 }
278 if (entry & PAGE_ENTRY_0) {
279 return PGM_TRANS_SPEC;
280 }
281 if (entry & PAGE_ENTRY_P) {
282 *flags &= ~PAGE_WRITE;
283 }
284 if (iep && (entry & PAGE_ENTRY_IEP)) {
285 *flags &= ~PAGE_EXEC;
286 }
287
288 *raddr = entry & TARGET_PAGE_MASK;
289 return 0;
290 }
291
292 static void mmu_handle_skey(target_ulong addr, int rw, int *flags)
293 {
294 static S390SKeysClass *skeyclass;
295 static S390SKeysState *ss;
296 MachineState *ms = MACHINE(qdev_get_machine());
297 uint8_t key;
298 int rc;
299
300 if (unlikely(addr >= ms->ram_size)) {
301 return;
302 }
303
304 if (unlikely(!ss)) {
305 ss = s390_get_skeys_device();
306 skeyclass = S390_SKEYS_GET_CLASS(ss);
307 }
308
309 /*
310 * Whenever we create a new TLB entry, we set the storage key reference
311 * bit. In case we allow write accesses, we set the storage key change
312 * bit. Whenever the guest changes the storage key, we have to flush the
313 * TLBs of all CPUs (the whole TLB or all affected entries), so that the
314 * next reference/change will result in an MMU fault and make us properly
315 * update the storage key here.
316 *
317 * Note 1: "record of references ... is not necessarily accurate",
318 * "change bit may be set in case no storing has occurred".
319 * -> We can set reference/change bits even on exceptions.
320 * Note 2: certain accesses seem to ignore storage keys. For example,
321 * DAT translation does not set reference bits for table accesses.
322 *
323 * TODO: key-controlled protection. Only CPU accesses make use of the
324 * PSW key. CSS accesses are different - we have to pass in the key.
325 *
326 * TODO: we have races between getting and setting the key.
327 */
328 rc = skeyclass->get_skeys(ss, addr / TARGET_PAGE_SIZE, 1, &key);
329 if (rc) {
330 trace_get_skeys_nonzero(rc);
331 return;
332 }
333
334 switch (rw) {
335 case MMU_DATA_LOAD:
336 case MMU_INST_FETCH:
337 /*
338 * The TLB entry has to remain write-protected on read-faults if
339 * the storage key does not indicate a change already. Otherwise
340 * we might miss setting the change bit on write accesses.
341 */
342 if (!(key & SK_C)) {
343 *flags &= ~PAGE_WRITE;
344 }
345 break;
346 case MMU_DATA_STORE:
347 key |= SK_C;
348 break;
349 default:
350 g_assert_not_reached();
351 }
352
353 /* Any store/fetch sets the reference bit */
354 key |= SK_R;
355
356 rc = skeyclass->set_skeys(ss, addr / TARGET_PAGE_SIZE, 1, &key);
357 if (rc) {
358 trace_set_skeys_nonzero(rc);
359 }
360 }
361
362 /**
363 * Translate a virtual (logical) address into a physical (absolute) address.
364 * @param vaddr the virtual address
365 * @param rw 0 = read, 1 = write, 2 = code fetch
366 * @param asc address space control (one of the PSW_ASC_* modes)
367 * @param raddr the translated address is stored to this pointer
368 * @param flags the PAGE_READ/WRITE/EXEC flags are stored to this pointer
369 * @param exc true = inject a program check if a fault occurred
370 * @return 0 = success, != 0, the exception to raise
371 */
372 int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
373 target_ulong *raddr, int *flags, uint64_t *tec)
374 {
375 uint64_t asce;
376 int r;
377
378 *tec = (vaddr & TARGET_PAGE_MASK) | (asc >> 46) |
379 (rw == MMU_DATA_STORE ? FS_WRITE : FS_READ);
380 *flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
381
382 if (is_low_address(vaddr & TARGET_PAGE_MASK) && lowprot_enabled(env, asc)) {
383 /*
384 * If any part of this page is currently protected, make sure the
385 * TLB entry will not be reused.
386 *
387 * As the protected range is always the first 512 bytes of the
388 * two first pages, we are able to catch all writes to these areas
389 * just by looking at the start address (triggering the tlb miss).
390 */
391 *flags |= PAGE_WRITE_INV;
392 if (is_low_address(vaddr) && rw == MMU_DATA_STORE) {
393 /* LAP sets bit 56 */
394 *tec |= 0x80;
395 return PGM_PROTECTION;
396 }
397 }
398
399 vaddr &= TARGET_PAGE_MASK;
400
401 if (!(env->psw.mask & PSW_MASK_DAT)) {
402 *raddr = vaddr;
403 goto nodat;
404 }
405
406 switch (asc) {
407 case PSW_ASC_PRIMARY:
408 asce = env->cregs[1];
409 break;
410 case PSW_ASC_HOME:
411 asce = env->cregs[13];
412 break;
413 case PSW_ASC_SECONDARY:
414 asce = env->cregs[7];
415 break;
416 case PSW_ASC_ACCREG:
417 default:
418 hw_error("guest switched to unknown asc mode\n");
419 break;
420 }
421
422 /* perform the DAT translation */
423 r = mmu_translate_asce(env, vaddr, asc, asce, raddr, flags, rw);
424 if (unlikely(r)) {
425 return r;
426 }
427
428 /* check for DAT protection */
429 if (unlikely(rw == MMU_DATA_STORE && !(*flags & PAGE_WRITE))) {
430 /* DAT sets bit 61 only */
431 *tec |= 0x4;
432 return PGM_PROTECTION;
433 }
434
435 /* check for Instruction-Execution-Protection */
436 if (unlikely(rw == MMU_INST_FETCH && !(*flags & PAGE_EXEC))) {
437 /* IEP sets bit 56 and 61 */
438 *tec |= 0x84;
439 return PGM_PROTECTION;
440 }
441
442 nodat:
443 /* Convert real address -> absolute address */
444 *raddr = mmu_real2abs(env, *raddr);
445
446 mmu_handle_skey(*raddr, rw, flags);
447 return 0;
448 }
449
450 /**
451 * translate_pages: Translate a set of consecutive logical page addresses
452 * to absolute addresses. This function is used for TCG and old KVM without
453 * the MEMOP interface.
454 */
455 static int translate_pages(S390CPU *cpu, vaddr addr, int nr_pages,
456 target_ulong *pages, bool is_write, uint64_t *tec)
457 {
458 uint64_t asc = cpu->env.psw.mask & PSW_MASK_ASC;
459 CPUS390XState *env = &cpu->env;
460 int ret, i, pflags;
461
462 for (i = 0; i < nr_pages; i++) {
463 ret = mmu_translate(env, addr, is_write, asc, &pages[i], &pflags, tec);
464 if (ret) {
465 return ret;
466 }
467 if (!address_space_access_valid(&address_space_memory, pages[i],
468 TARGET_PAGE_SIZE, is_write,
469 MEMTXATTRS_UNSPECIFIED)) {
470 *tec = 0; /* unused */
471 return PGM_ADDRESSING;
472 }
473 addr += TARGET_PAGE_SIZE;
474 }
475
476 return 0;
477 }
478
479 int s390_cpu_pv_mem_rw(S390CPU *cpu, unsigned int offset, void *hostbuf,
480 int len, bool is_write)
481 {
482 int ret;
483
484 if (kvm_enabled()) {
485 ret = kvm_s390_mem_op_pv(cpu, offset, hostbuf, len, is_write);
486 } else {
487 /* Protected Virtualization is a KVM/Hardware only feature */
488 g_assert_not_reached();
489 }
490 return ret;
491 }
492
493 /**
494 * s390_cpu_virt_mem_rw:
495 * @laddr: the logical start address
496 * @ar: the access register number
497 * @hostbuf: buffer in host memory. NULL = do only checks w/o copying
498 * @len: length that should be transferred
499 * @is_write: true = write, false = read
500 * Returns: 0 on success, non-zero if an exception occurred
501 *
502 * Copy from/to guest memory using logical addresses. Note that we inject a
503 * program interrupt in case there is an error while accessing the memory.
504 *
505 * This function will always return (also for TCG), make sure to call
506 * s390_cpu_virt_mem_handle_exc() to properly exit the CPU loop.
507 */
508 int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
509 int len, bool is_write)
510 {
511 int currlen, nr_pages, i;
512 target_ulong *pages;
513 uint64_t tec;
514 int ret;
515
516 if (kvm_enabled()) {
517 ret = kvm_s390_mem_op(cpu, laddr, ar, hostbuf, len, is_write);
518 if (ret >= 0) {
519 return ret;
520 }
521 }
522
523 nr_pages = (((laddr & ~TARGET_PAGE_MASK) + len - 1) >> TARGET_PAGE_BITS)
524 + 1;
525 pages = g_malloc(nr_pages * sizeof(*pages));
526
527 ret = translate_pages(cpu, laddr, nr_pages, pages, is_write, &tec);
528 if (ret) {
529 trigger_access_exception(&cpu->env, ret, tec);
530 } else if (hostbuf != NULL) {
531 /* Copy data by stepping through the area page by page */
532 for (i = 0; i < nr_pages; i++) {
533 currlen = MIN(len, TARGET_PAGE_SIZE - (laddr % TARGET_PAGE_SIZE));
534 cpu_physical_memory_rw(pages[i] | (laddr & ~TARGET_PAGE_MASK),
535 hostbuf, currlen, is_write);
536 laddr += currlen;
537 hostbuf += currlen;
538 len -= currlen;
539 }
540 }
541
542 g_free(pages);
543 return ret;
544 }
545
546 void s390_cpu_virt_mem_handle_exc(S390CPU *cpu, uintptr_t ra)
547 {
548 /* KVM will handle the interrupt automatically, TCG has to exit the TB */
549 #ifdef CONFIG_TCG
550 if (tcg_enabled()) {
551 cpu_loop_exit_restore(CPU(cpu), ra);
552 }
553 #endif
554 }
555
556 /**
557 * Translate a real address into a physical (absolute) address.
558 * @param raddr the real address
559 * @param rw 0 = read, 1 = write, 2 = code fetch
560 * @param addr the translated address is stored to this pointer
561 * @param flags the PAGE_READ/WRITE/EXEC flags are stored to this pointer
562 * @return 0 = success, != 0, the exception to raise
563 */
564 int mmu_translate_real(CPUS390XState *env, target_ulong raddr, int rw,
565 target_ulong *addr, int *flags, uint64_t *tec)
566 {
567 const bool lowprot_enabled = env->cregs[0] & CR0_LOWPROT;
568
569 *flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
570 if (is_low_address(raddr & TARGET_PAGE_MASK) && lowprot_enabled) {
571 /* see comment in mmu_translate() how this works */
572 *flags |= PAGE_WRITE_INV;
573 if (is_low_address(raddr) && rw == MMU_DATA_STORE) {
574 /* LAP sets bit 56 */
575 *tec = (raddr & TARGET_PAGE_MASK) | FS_WRITE | 0x80;
576 return PGM_PROTECTION;
577 }
578 }
579
580 *addr = mmu_real2abs(env, raddr & TARGET_PAGE_MASK);
581
582 mmu_handle_skey(*addr, rw, flags);
583 return 0;
584 }