migration: increase max-bandwidth to 128 MiB/s (1 Gib/s)
[qemu.git] / target / sh4 / cpu.c
1 /*
2 * QEMU SuperH CPU
3 *
4 * Copyright (c) 2005 Samuel Tardieu
5 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2.1 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see
19 * <http://www.gnu.org/licenses/lgpl-2.1.html>
20 */
21
22 #include "qemu/osdep.h"
23 #include "qapi/error.h"
24 #include "qemu/qemu-print.h"
25 #include "cpu.h"
26 #include "migration/vmstate.h"
27 #include "exec/exec-all.h"
28 #include "fpu/softfloat-helpers.h"
29
30 static void superh_cpu_set_pc(CPUState *cs, vaddr value)
31 {
32 SuperHCPU *cpu = SUPERH_CPU(cs);
33
34 cpu->env.pc = value;
35 }
36
37 static void superh_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
38 {
39 SuperHCPU *cpu = SUPERH_CPU(cs);
40
41 cpu->env.pc = tb->pc;
42 cpu->env.flags = tb->flags & TB_FLAG_ENVFLAGS_MASK;
43 }
44
45 static bool superh_cpu_has_work(CPUState *cs)
46 {
47 return cs->interrupt_request & CPU_INTERRUPT_HARD;
48 }
49
50 static void superh_cpu_reset(DeviceState *dev)
51 {
52 CPUState *s = CPU(dev);
53 SuperHCPU *cpu = SUPERH_CPU(s);
54 SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu);
55 CPUSH4State *env = &cpu->env;
56
57 scc->parent_reset(dev);
58
59 memset(env, 0, offsetof(CPUSH4State, end_reset_fields));
60
61 env->pc = 0xA0000000;
62 #if defined(CONFIG_USER_ONLY)
63 env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
64 set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
65 #else
66 env->sr = (1u << SR_MD) | (1u << SR_RB) | (1u << SR_BL) |
67 (1u << SR_I3) | (1u << SR_I2) | (1u << SR_I1) | (1u << SR_I0);
68 env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */
69 set_float_rounding_mode(float_round_to_zero, &env->fp_status);
70 set_flush_to_zero(1, &env->fp_status);
71 #endif
72 set_default_nan_mode(1, &env->fp_status);
73 }
74
75 static void superh_cpu_disas_set_info(CPUState *cpu, disassemble_info *info)
76 {
77 info->mach = bfd_mach_sh4;
78 info->print_insn = print_insn_sh;
79 }
80
81 static void superh_cpu_list_entry(gpointer data, gpointer user_data)
82 {
83 const char *typename = object_class_get_name(OBJECT_CLASS(data));
84 int len = strlen(typename) - strlen(SUPERH_CPU_TYPE_SUFFIX);
85
86 qemu_printf("%.*s\n", len, typename);
87 }
88
89 void sh4_cpu_list(void)
90 {
91 GSList *list;
92
93 list = object_class_get_list_sorted(TYPE_SUPERH_CPU, false);
94 g_slist_foreach(list, superh_cpu_list_entry, NULL);
95 g_slist_free(list);
96 }
97
98 static ObjectClass *superh_cpu_class_by_name(const char *cpu_model)
99 {
100 ObjectClass *oc;
101 char *s, *typename = NULL;
102
103 s = g_ascii_strdown(cpu_model, -1);
104 if (strcmp(s, "any") == 0) {
105 oc = object_class_by_name(TYPE_SH7750R_CPU);
106 goto out;
107 }
108
109 typename = g_strdup_printf(SUPERH_CPU_TYPE_NAME("%s"), s);
110 oc = object_class_by_name(typename);
111 if (oc != NULL && object_class_is_abstract(oc)) {
112 oc = NULL;
113 }
114
115 out:
116 g_free(s);
117 g_free(typename);
118 return oc;
119 }
120
121 static void sh7750r_cpu_initfn(Object *obj)
122 {
123 SuperHCPU *cpu = SUPERH_CPU(obj);
124 CPUSH4State *env = &cpu->env;
125
126 env->id = SH_CPU_SH7750R;
127 env->features = SH_FEATURE_BCR3_AND_BCR4;
128 }
129
130 static void sh7750r_class_init(ObjectClass *oc, void *data)
131 {
132 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
133
134 scc->pvr = 0x00050000;
135 scc->prr = 0x00000100;
136 scc->cvr = 0x00110000;
137 }
138
139 static void sh7751r_cpu_initfn(Object *obj)
140 {
141 SuperHCPU *cpu = SUPERH_CPU(obj);
142 CPUSH4State *env = &cpu->env;
143
144 env->id = SH_CPU_SH7751R;
145 env->features = SH_FEATURE_BCR3_AND_BCR4;
146 }
147
148 static void sh7751r_class_init(ObjectClass *oc, void *data)
149 {
150 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
151
152 scc->pvr = 0x04050005;
153 scc->prr = 0x00000113;
154 scc->cvr = 0x00110000; /* Neutered caches, should be 0x20480000 */
155 }
156
157 static void sh7785_cpu_initfn(Object *obj)
158 {
159 SuperHCPU *cpu = SUPERH_CPU(obj);
160 CPUSH4State *env = &cpu->env;
161
162 env->id = SH_CPU_SH7785;
163 env->features = SH_FEATURE_SH4A;
164 }
165
166 static void sh7785_class_init(ObjectClass *oc, void *data)
167 {
168 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
169
170 scc->pvr = 0x10300700;
171 scc->prr = 0x00000200;
172 scc->cvr = 0x71440211;
173 }
174
175 static void superh_cpu_realizefn(DeviceState *dev, Error **errp)
176 {
177 CPUState *cs = CPU(dev);
178 SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(dev);
179 Error *local_err = NULL;
180
181 cpu_exec_realizefn(cs, &local_err);
182 if (local_err != NULL) {
183 error_propagate(errp, local_err);
184 return;
185 }
186
187 cpu_reset(cs);
188 qemu_init_vcpu(cs);
189
190 scc->parent_realize(dev, errp);
191 }
192
193 static void superh_cpu_initfn(Object *obj)
194 {
195 SuperHCPU *cpu = SUPERH_CPU(obj);
196 CPUSH4State *env = &cpu->env;
197
198 cpu_set_cpustate_pointers(cpu);
199
200 env->movcal_backup_tail = &(env->movcal_backup);
201 }
202
203 static const VMStateDescription vmstate_sh_cpu = {
204 .name = "cpu",
205 .unmigratable = 1,
206 };
207
208 static void superh_cpu_class_init(ObjectClass *oc, void *data)
209 {
210 DeviceClass *dc = DEVICE_CLASS(oc);
211 CPUClass *cc = CPU_CLASS(oc);
212 SuperHCPUClass *scc = SUPERH_CPU_CLASS(oc);
213
214 device_class_set_parent_realize(dc, superh_cpu_realizefn,
215 &scc->parent_realize);
216
217 device_class_set_parent_reset(dc, superh_cpu_reset, &scc->parent_reset);
218
219 cc->class_by_name = superh_cpu_class_by_name;
220 cc->has_work = superh_cpu_has_work;
221 cc->do_interrupt = superh_cpu_do_interrupt;
222 cc->cpu_exec_interrupt = superh_cpu_exec_interrupt;
223 cc->dump_state = superh_cpu_dump_state;
224 cc->set_pc = superh_cpu_set_pc;
225 cc->synchronize_from_tb = superh_cpu_synchronize_from_tb;
226 cc->gdb_read_register = superh_cpu_gdb_read_register;
227 cc->gdb_write_register = superh_cpu_gdb_write_register;
228 cc->tlb_fill = superh_cpu_tlb_fill;
229 #ifndef CONFIG_USER_ONLY
230 cc->do_unaligned_access = superh_cpu_do_unaligned_access;
231 cc->get_phys_page_debug = superh_cpu_get_phys_page_debug;
232 #endif
233 cc->disas_set_info = superh_cpu_disas_set_info;
234 cc->tcg_initialize = sh4_translate_init;
235
236 cc->gdb_num_core_regs = 59;
237
238 dc->vmsd = &vmstate_sh_cpu;
239 }
240
241 #define DEFINE_SUPERH_CPU_TYPE(type_name, cinit, initfn) \
242 { \
243 .name = type_name, \
244 .parent = TYPE_SUPERH_CPU, \
245 .class_init = cinit, \
246 .instance_init = initfn, \
247 }
248 static const TypeInfo superh_cpu_type_infos[] = {
249 {
250 .name = TYPE_SUPERH_CPU,
251 .parent = TYPE_CPU,
252 .instance_size = sizeof(SuperHCPU),
253 .instance_init = superh_cpu_initfn,
254 .abstract = true,
255 .class_size = sizeof(SuperHCPUClass),
256 .class_init = superh_cpu_class_init,
257 },
258 DEFINE_SUPERH_CPU_TYPE(TYPE_SH7750R_CPU, sh7750r_class_init,
259 sh7750r_cpu_initfn),
260 DEFINE_SUPERH_CPU_TYPE(TYPE_SH7751R_CPU, sh7751r_class_init,
261 sh7751r_cpu_initfn),
262 DEFINE_SUPERH_CPU_TYPE(TYPE_SH7785_CPU, sh7785_class_init,
263 sh7785_cpu_initfn),
264
265 };
266
267 DEFINE_TYPES(superh_cpu_type_infos)