tests/acpi: add new unit test to test hotplug off/on feature on the root pci bus
[qemu.git] / target / tilegx / cpu.c
1 /*
2 * QEMU TILE-Gx CPU
3 *
4 * Copyright (c) 2015 Chen Gang
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2.1 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see
18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
19 */
20
21 #include "qemu/osdep.h"
22 #include "qapi/error.h"
23 #include "cpu.h"
24 #include "qemu/module.h"
25 #include "linux-user/syscall_defs.h"
26 #include "qemu/qemu-print.h"
27 #include "exec/exec-all.h"
28
29 static void tilegx_cpu_dump_state(CPUState *cs, FILE *f, int flags)
30 {
31 static const char * const reg_names[TILEGX_R_COUNT] = {
32 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
33 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
34 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
35 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
36 "r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
37 "r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
38 "r48", "r49", "r50", "r51", "bp", "tp", "sp", "lr"
39 };
40
41 TileGXCPU *cpu = TILEGX_CPU(cs);
42 CPUTLGState *env = &cpu->env;
43 int i;
44
45 for (i = 0; i < TILEGX_R_COUNT; i++) {
46 qemu_fprintf(f, "%-4s" TARGET_FMT_lx "%s",
47 reg_names[i], env->regs[i],
48 (i % 4) == 3 ? "\n" : " ");
49 }
50 qemu_fprintf(f, "PC " TARGET_FMT_lx " CEX " TARGET_FMT_lx "\n\n",
51 env->pc, env->spregs[TILEGX_SPR_CMPEXCH]);
52 }
53
54 static ObjectClass *tilegx_cpu_class_by_name(const char *cpu_model)
55 {
56 return object_class_by_name(TYPE_TILEGX_CPU);
57 }
58
59 static void tilegx_cpu_set_pc(CPUState *cs, vaddr value)
60 {
61 TileGXCPU *cpu = TILEGX_CPU(cs);
62
63 cpu->env.pc = value;
64 }
65
66 static bool tilegx_cpu_has_work(CPUState *cs)
67 {
68 return true;
69 }
70
71 static void tilegx_cpu_reset(DeviceState *dev)
72 {
73 CPUState *s = CPU(dev);
74 TileGXCPU *cpu = TILEGX_CPU(s);
75 TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(cpu);
76 CPUTLGState *env = &cpu->env;
77
78 tcc->parent_reset(dev);
79
80 memset(env, 0, offsetof(CPUTLGState, end_reset_fields));
81 }
82
83 static void tilegx_cpu_realizefn(DeviceState *dev, Error **errp)
84 {
85 CPUState *cs = CPU(dev);
86 TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(dev);
87 Error *local_err = NULL;
88
89 cpu_exec_realizefn(cs, &local_err);
90 if (local_err != NULL) {
91 error_propagate(errp, local_err);
92 return;
93 }
94
95 cpu_reset(cs);
96 qemu_init_vcpu(cs);
97
98 tcc->parent_realize(dev, errp);
99 }
100
101 static void tilegx_cpu_initfn(Object *obj)
102 {
103 TileGXCPU *cpu = TILEGX_CPU(obj);
104
105 cpu_set_cpustate_pointers(cpu);
106 }
107
108 static void tilegx_cpu_do_interrupt(CPUState *cs)
109 {
110 cs->exception_index = -1;
111 }
112
113 static bool tilegx_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
114 MMUAccessType access_type, int mmu_idx,
115 bool probe, uintptr_t retaddr)
116 {
117 TileGXCPU *cpu = TILEGX_CPU(cs);
118
119 /* The sigcode field will be filled in by do_signal in main.c. */
120 cs->exception_index = TILEGX_EXCP_SIGNAL;
121 cpu->env.excaddr = address;
122 cpu->env.signo = TARGET_SIGSEGV;
123 cpu->env.sigcode = 0;
124
125 cpu_loop_exit_restore(cs, retaddr);
126 }
127
128 static bool tilegx_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
129 {
130 if (interrupt_request & CPU_INTERRUPT_HARD) {
131 tilegx_cpu_do_interrupt(cs);
132 return true;
133 }
134 return false;
135 }
136
137 static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
138 {
139 DeviceClass *dc = DEVICE_CLASS(oc);
140 CPUClass *cc = CPU_CLASS(oc);
141 TileGXCPUClass *tcc = TILEGX_CPU_CLASS(oc);
142
143 device_class_set_parent_realize(dc, tilegx_cpu_realizefn,
144 &tcc->parent_realize);
145
146 device_class_set_parent_reset(dc, tilegx_cpu_reset, &tcc->parent_reset);
147
148 cc->class_by_name = tilegx_cpu_class_by_name;
149 cc->has_work = tilegx_cpu_has_work;
150 cc->do_interrupt = tilegx_cpu_do_interrupt;
151 cc->cpu_exec_interrupt = tilegx_cpu_exec_interrupt;
152 cc->dump_state = tilegx_cpu_dump_state;
153 cc->set_pc = tilegx_cpu_set_pc;
154 cc->tlb_fill = tilegx_cpu_tlb_fill;
155 cc->gdb_num_core_regs = 0;
156 cc->tcg_initialize = tilegx_tcg_init;
157 }
158
159 static const TypeInfo tilegx_cpu_type_info = {
160 .name = TYPE_TILEGX_CPU,
161 .parent = TYPE_CPU,
162 .instance_size = sizeof(TileGXCPU),
163 .instance_init = tilegx_cpu_initfn,
164 .class_size = sizeof(TileGXCPUClass),
165 .class_init = tilegx_cpu_class_init,
166 };
167
168 static void tilegx_cpu_register_types(void)
169 {
170 type_register_static(&tilegx_cpu_type_info);
171 }
172
173 type_init(tilegx_cpu_register_types)