tests: virtio-9p: rename PCI configuration test
[qemu.git] / target / tricore / csfr.def
1 /* A(ll) access permited
2    R(ead only) access
3    E(nd init protected) access
4
5    A|R|E(offset, register, feature introducing reg)
6
7    NOTE: PSW is handled as a special case in gen_mtcr/mfcr */
8
9 A(0xfe00, PCXI, TRICORE_FEATURE_13)
10 A(0xfe08, PC, TRICORE_FEATURE_13)
11 A(0xfe14, SYSCON, TRICORE_FEATURE_13)
12 R(0xfe18, CPU_ID, TRICORE_FEATURE_13)
13 E(0xfe20, BIV, TRICORE_FEATURE_13)
14 E(0xfe24, BTV, TRICORE_FEATURE_13)
15 E(0xfe28, ISP, TRICORE_FEATURE_13)
16 A(0xfe2c, ICR, TRICORE_FEATURE_13)
17 A(0xfe38, FCX, TRICORE_FEATURE_13)
18 A(0xfe3c, LCX, TRICORE_FEATURE_13)
19 E(0x9400, COMPAT, TRICORE_FEATURE_131)
20 /* memory protection register */
21 A(0xC000, DPR0_0L, TRICORE_FEATURE_13)
22 A(0xC004, DPR0_0U, TRICORE_FEATURE_13)
23 A(0xC008, DPR0_1L, TRICORE_FEATURE_13)
24 A(0xC00C, DPR0_1U, TRICORE_FEATURE_13)
25 A(0xC010, DPR0_2L, TRICORE_FEATURE_13)
26 A(0xC014, DPR0_2U, TRICORE_FEATURE_13)
27 A(0xC018, DPR0_3L, TRICORE_FEATURE_13)
28 A(0xC01C, DPR0_3U, TRICORE_FEATURE_13)
29 A(0xC400, DPR1_0L, TRICORE_FEATURE_13)
30 A(0xC404, DPR1_0U, TRICORE_FEATURE_13)
31 A(0xC408, DPR1_1L, TRICORE_FEATURE_13)
32 A(0xC40C, DPR1_1U, TRICORE_FEATURE_13)
33 A(0xC410, DPR1_2L, TRICORE_FEATURE_13)
34 A(0xC414, DPR1_2U, TRICORE_FEATURE_13)
35 A(0xC418, DPR1_3L, TRICORE_FEATURE_13)
36 A(0xC41C, DPR1_3U, TRICORE_FEATURE_13)
37 A(0xC800, DPR2_0L, TRICORE_FEATURE_13)
38 A(0xC804, DPR2_0U, TRICORE_FEATURE_13)
39 A(0xC808, DPR2_1L, TRICORE_FEATURE_13)
40 A(0xC80C, DPR2_1U, TRICORE_FEATURE_13)
41 A(0xC810, DPR2_2L, TRICORE_FEATURE_13)
42 A(0xC814, DPR2_2U, TRICORE_FEATURE_13)
43 A(0xC818, DPR2_3L, TRICORE_FEATURE_13)
44 A(0xC81C, DPR2_3U, TRICORE_FEATURE_13)
45 A(0xCC00, DPR3_0L, TRICORE_FEATURE_13)
46 A(0xCC04, DPR3_0U, TRICORE_FEATURE_13)
47 A(0xCC08, DPR3_1L, TRICORE_FEATURE_13)
48 A(0xCC0C, DPR3_1U, TRICORE_FEATURE_13)
49 A(0xCC10, DPR3_2L, TRICORE_FEATURE_13)
50 A(0xCC14, DPR3_2U, TRICORE_FEATURE_13)
51 A(0xCC18, DPR3_3L, TRICORE_FEATURE_13)
52 A(0xCC1C, DPR3_3U, TRICORE_FEATURE_13)
53 A(0xD000, CPR0_0L, TRICORE_FEATURE_13)
54 A(0xD004, CPR0_0U, TRICORE_FEATURE_13)
55 A(0xD008, CPR0_1L, TRICORE_FEATURE_13)
56 A(0xD00C, CPR0_1U, TRICORE_FEATURE_13)
57 A(0xD010, CPR0_2L, TRICORE_FEATURE_13)
58 A(0xD014, CPR0_2U, TRICORE_FEATURE_13)
59 A(0xD018, CPR0_3L, TRICORE_FEATURE_13)
60 A(0xD01C, CPR0_3U, TRICORE_FEATURE_13)
61 A(0xD400, CPR1_0L, TRICORE_FEATURE_13)
62 A(0xD404, CPR1_0U, TRICORE_FEATURE_13)
63 A(0xD408, CPR1_1L, TRICORE_FEATURE_13)
64 A(0xD40C, CPR1_1U, TRICORE_FEATURE_13)
65 A(0xD410, CPR1_2L, TRICORE_FEATURE_13)
66 A(0xD414, CPR1_2U, TRICORE_FEATURE_13)
67 A(0xD418, CPR1_3L, TRICORE_FEATURE_13)
68 A(0xD41C, CPR1_3U, TRICORE_FEATURE_13)
69 A(0xD800, CPR2_0L, TRICORE_FEATURE_13)
70 A(0xD804, CPR2_0U, TRICORE_FEATURE_13)
71 A(0xD808, CPR2_1L, TRICORE_FEATURE_13)
72 A(0xD80C, CPR2_1U, TRICORE_FEATURE_13)
73 A(0xD810, CPR2_2L, TRICORE_FEATURE_13)
74 A(0xD814, CPR2_2U, TRICORE_FEATURE_13)
75 A(0xD818, CPR2_3L, TRICORE_FEATURE_13)
76 A(0xD81C, CPR2_3U, TRICORE_FEATURE_13)
77 A(0xDC00, CPR3_0L, TRICORE_FEATURE_13)
78 A(0xDC04, CPR3_0U, TRICORE_FEATURE_13)
79 A(0xDC08, CPR3_1L, TRICORE_FEATURE_13)
80 A(0xDC0C, CPR3_1U, TRICORE_FEATURE_13)
81 A(0xDC10, CPR3_2L, TRICORE_FEATURE_13)
82 A(0xDC14, CPR3_2U, TRICORE_FEATURE_13)
83 A(0xDC18, CPR3_3L, TRICORE_FEATURE_13)
84 A(0xDC1C, CPR3_3U, TRICORE_FEATURE_13)
85 A(0xE000, DPM0, TRICORE_FEATURE_13)
86 A(0xE080, DPM1, TRICORE_FEATURE_13)
87 A(0xE100, DPM2, TRICORE_FEATURE_13)
88 A(0xE180, DPM3, TRICORE_FEATURE_13)
89 A(0xE200, CPM0, TRICORE_FEATURE_13)
90 A(0xE280, CPM1, TRICORE_FEATURE_13)
91 A(0xE300, CPM2, TRICORE_FEATURE_13)
92 A(0xE380, CPM3, TRICORE_FEATURE_13)
93 /* memory management registers */
94 A(0x8000, MMU_CON, TRICORE_FEATURE_13)
95 A(0x8004, MMU_ASI, TRICORE_FEATURE_13)
96 A(0x800C, MMU_TVA, TRICORE_FEATURE_13)
97 A(0x8010, MMU_TPA, TRICORE_FEATURE_13)
98 A(0x8014, MMU_TPX, TRICORE_FEATURE_13)
99 A(0x8018, MMU_TFA, TRICORE_FEATURE_13)
100 E(0x9004, BMACON, TRICORE_FEATURE_131)
101 E(0x900C, SMACON, TRICORE_FEATURE_131)
102 A(0x9020, DIEAR, TRICORE_FEATURE_131)
103 A(0x9024, DIETR, TRICORE_FEATURE_131)
104 A(0x9028, CCDIER, TRICORE_FEATURE_131)
105 E(0x9044, MIECON, TRICORE_FEATURE_131)
106 A(0x9210, PIEAR, TRICORE_FEATURE_131)
107 A(0x9214, PIETR, TRICORE_FEATURE_131)
108 A(0x9218, CCPIER, TRICORE_FEATURE_131)
109 /* debug registers */
110 A(0xFD00, DBGSR, TRICORE_FEATURE_13)
111 A(0xFD08, EXEVT, TRICORE_FEATURE_13)
112 A(0xFD0C, CREVT, TRICORE_FEATURE_13)
113 A(0xFD10, SWEVT, TRICORE_FEATURE_13)
114 A(0xFD20, TR0EVT, TRICORE_FEATURE_13)
115 A(0xFD24, TR1EVT, TRICORE_FEATURE_13)
116 A(0xFD40, DMS, TRICORE_FEATURE_13)
117 A(0xFD44, DCX, TRICORE_FEATURE_13)
118 A(0xFD48, DBGTCR, TRICORE_FEATURE_131)
119 A(0xFC00, CCTRL, TRICORE_FEATURE_131)
120 A(0xFC04, CCNT, TRICORE_FEATURE_131)
121 A(0xFC08, ICNT, TRICORE_FEATURE_131)
122 A(0xFC0C, M1CNT, TRICORE_FEATURE_131)
123 A(0xFC10, M2CNT, TRICORE_FEATURE_131)
124 A(0xFC14, M3CNT, TRICORE_FEATURE_131)