linux-user, scripts: add a script to update syscall.tbl
[qemu.git] / target / unicore32 / cpu.h
1 /*
2 * UniCore32 virtual CPU header
3 *
4 * Copyright (C) 2010-2012 Guan Xuetao
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation, or (at your option) any
9 * later version. See the COPYING file in the top-level directory.
10 */
11
12 #ifndef UNICORE32_CPU_H
13 #define UNICORE32_CPU_H
14
15 #include "cpu-qom.h"
16 #include "exec/cpu-defs.h"
17
18 typedef struct CPUUniCore32State {
19 /* Regs for current mode. */
20 uint32_t regs[32];
21 /* Frequently accessed ASR bits are stored separately for efficiently.
22 This contains all the other bits. Use asr_{read,write} to access
23 the whole ASR. */
24 uint32_t uncached_asr;
25 uint32_t bsr;
26
27 /* Banked registers. */
28 uint32_t banked_bsr[6];
29 uint32_t banked_r29[6];
30 uint32_t banked_r30[6];
31
32 /* asr flag cache for faster execution */
33 uint32_t CF; /* 0 or 1 */
34 uint32_t VF; /* V is the bit 31. All other bits are undefined */
35 uint32_t NF; /* N is bit 31. All other bits are undefined. */
36 uint32_t ZF; /* Z set if zero. */
37
38 /* System control coprocessor (cp0) */
39 struct {
40 uint32_t c0_cpuid;
41 uint32_t c0_cachetype;
42 uint32_t c1_sys; /* System control register. */
43 uint32_t c2_base; /* MMU translation table base. */
44 uint32_t c3_faultstatus; /* Fault status registers. */
45 uint32_t c4_faultaddr; /* Fault address registers. */
46 uint32_t c5_cacheop; /* Cache operation registers. */
47 uint32_t c6_tlbop; /* TLB operation registers. */
48 } cp0;
49
50 /* UniCore-F64 coprocessor state. */
51 struct {
52 float64 regs[16];
53 uint32_t xregs[32];
54 float_status fp_status;
55 } ucf64;
56
57 /* Internal CPU feature flags. */
58 uint32_t features;
59
60 } CPUUniCore32State;
61
62 /**
63 * UniCore32CPU:
64 * @env: #CPUUniCore32State
65 *
66 * A UniCore32 CPU.
67 */
68 struct UniCore32CPU {
69 /*< private >*/
70 CPUState parent_obj;
71 /*< public >*/
72
73 CPUNegativeOffsetState neg;
74 CPUUniCore32State env;
75 };
76
77
78 void uc32_cpu_do_interrupt(CPUState *cpu);
79 bool uc32_cpu_exec_interrupt(CPUState *cpu, int int_req);
80 void uc32_cpu_dump_state(CPUState *cpu, FILE *f, int flags);
81 hwaddr uc32_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
82
83 #define ASR_M (0x1f)
84 #define ASR_MODE_USER (0x10)
85 #define ASR_MODE_INTR (0x12)
86 #define ASR_MODE_PRIV (0x13)
87 #define ASR_MODE_TRAP (0x17)
88 #define ASR_MODE_EXTN (0x1b)
89 #define ASR_MODE_SUSR (0x1f)
90 #define ASR_I (1 << 7)
91 #define ASR_V (1 << 28)
92 #define ASR_C (1 << 29)
93 #define ASR_Z (1 << 30)
94 #define ASR_N (1 << 31)
95 #define ASR_NZCV (ASR_N | ASR_Z | ASR_C | ASR_V)
96 #define ASR_RESERVED (~(ASR_M | ASR_I | ASR_NZCV))
97
98 #define UC32_EXCP_PRIV (1)
99 #define UC32_EXCP_ITRAP (2)
100 #define UC32_EXCP_DTRAP (3)
101 #define UC32_EXCP_INTR (4)
102
103 /* Return the current ASR value. */
104 target_ulong cpu_asr_read(CPUUniCore32State *env1);
105 /* Set the ASR. Note that some bits of mask must be all-set or all-clear. */
106 void cpu_asr_write(CPUUniCore32State *env1, target_ulong val, target_ulong mask);
107
108 /* UniCore-F64 system registers. */
109 #define UC32_UCF64_FPSCR (31)
110 #define UCF64_FPSCR_MASK (0x27ffffff)
111 #define UCF64_FPSCR_RND_MASK (0x7)
112 #define UCF64_FPSCR_RND(r) (((r) >> 0) & UCF64_FPSCR_RND_MASK)
113 #define UCF64_FPSCR_TRAPEN_MASK (0x7f)
114 #define UCF64_FPSCR_TRAPEN(r) (((r) >> 10) & UCF64_FPSCR_TRAPEN_MASK)
115 #define UCF64_FPSCR_FLAG_MASK (0x3ff)
116 #define UCF64_FPSCR_FLAG(r) (((r) >> 17) & UCF64_FPSCR_FLAG_MASK)
117 #define UCF64_FPSCR_FLAG_ZERO (1 << 17)
118 #define UCF64_FPSCR_FLAG_INFINITY (1 << 18)
119 #define UCF64_FPSCR_FLAG_INVALID (1 << 19)
120 #define UCF64_FPSCR_FLAG_UNDERFLOW (1 << 20)
121 #define UCF64_FPSCR_FLAG_OVERFLOW (1 << 21)
122 #define UCF64_FPSCR_FLAG_INEXACT (1 << 22)
123 #define UCF64_FPSCR_FLAG_HUGEINT (1 << 23)
124 #define UCF64_FPSCR_FLAG_DENORMAL (1 << 24)
125 #define UCF64_FPSCR_FLAG_UNIMP (1 << 25)
126 #define UCF64_FPSCR_FLAG_DIVZERO (1 << 26)
127
128 #define UC32_HWCAP_CMOV 4 /* 1 << 2 */
129 #define UC32_HWCAP_UCF64 8 /* 1 << 3 */
130
131 #define cpu_signal_handler uc32_cpu_signal_handler
132
133 int uc32_cpu_signal_handler(int host_signum, void *pinfo, void *puc);
134
135 /* MMU modes definitions */
136 #define MMU_USER_IDX 1
137 static inline int cpu_mmu_index(CPUUniCore32State *env, bool ifetch)
138 {
139 return (env->uncached_asr & ASR_M) == ASR_MODE_USER ? 1 : 0;
140 }
141
142 typedef CPUUniCore32State CPUArchState;
143 typedef UniCore32CPU ArchCPU;
144
145 #include "exec/cpu-all.h"
146
147 #define UNICORE32_CPU_TYPE_SUFFIX "-" TYPE_UNICORE32_CPU
148 #define UNICORE32_CPU_TYPE_NAME(model) model UNICORE32_CPU_TYPE_SUFFIX
149 #define CPU_RESOLVING_TYPE TYPE_UNICORE32_CPU
150
151 static inline void cpu_get_tb_cpu_state(CPUUniCore32State *env, target_ulong *pc,
152 target_ulong *cs_base, uint32_t *flags)
153 {
154 *pc = env->regs[31];
155 *cs_base = 0;
156 *flags = 0;
157 if ((env->uncached_asr & ASR_M) != ASR_MODE_USER) {
158 *flags |= (1 << 6);
159 }
160 }
161
162 bool uc32_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
163 MMUAccessType access_type, int mmu_idx,
164 bool probe, uintptr_t retaddr);
165 void uc32_translate_init(void);
166 void switch_mode(CPUUniCore32State *, int);
167
168 #endif /* UNICORE32_CPU_H */