linux-user, scripts: add a script to update syscall.tbl
[qemu.git] / target / xtensa / cpu.c
1 /*
2 * QEMU Xtensa CPU
3 *
4 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
5 * Copyright (c) 2012 SUSE LINUX Products GmbH
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are met:
10 * * Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * * Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * * Neither the name of the Open Source and Linux Lab nor the
16 * names of its contributors may be used to endorse or promote products
17 * derived from this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
23 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
26 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31 #include "qemu/osdep.h"
32 #include "qapi/error.h"
33 #include "cpu.h"
34 #include "qemu/module.h"
35 #include "migration/vmstate.h"
36
37
38 static void xtensa_cpu_set_pc(CPUState *cs, vaddr value)
39 {
40 XtensaCPU *cpu = XTENSA_CPU(cs);
41
42 cpu->env.pc = value;
43 }
44
45 static bool xtensa_cpu_has_work(CPUState *cs)
46 {
47 #ifndef CONFIG_USER_ONLY
48 XtensaCPU *cpu = XTENSA_CPU(cs);
49
50 return !cpu->env.runstall && cpu->env.pending_irq_level;
51 #else
52 return true;
53 #endif
54 }
55
56 #ifdef CONFIG_USER_ONLY
57 static bool abi_call0;
58
59 void xtensa_set_abi_call0(void)
60 {
61 abi_call0 = true;
62 }
63
64 bool xtensa_abi_call0(void)
65 {
66 return abi_call0;
67 }
68 #endif
69
70 /* CPUClass::reset() */
71 static void xtensa_cpu_reset(CPUState *s)
72 {
73 XtensaCPU *cpu = XTENSA_CPU(s);
74 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(cpu);
75 CPUXtensaState *env = &cpu->env;
76
77 xcc->parent_reset(s);
78
79 env->exception_taken = 0;
80 env->pc = env->config->exception_vector[EXC_RESET0 + env->static_vectors];
81 env->sregs[LITBASE] &= ~1;
82 #ifndef CONFIG_USER_ONLY
83 env->sregs[PS] = xtensa_option_enabled(env->config,
84 XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10;
85 env->pending_irq_level = 0;
86 #else
87 env->sregs[PS] = PS_UM | (3 << PS_RING_SHIFT);
88 if (xtensa_option_enabled(env->config,
89 XTENSA_OPTION_WINDOWED_REGISTER) &&
90 !xtensa_abi_call0()) {
91 env->sregs[PS] |= PS_WOE;
92 }
93 #endif
94 env->sregs[VECBASE] = env->config->vecbase;
95 env->sregs[IBREAKENABLE] = 0;
96 env->sregs[MEMCTL] = MEMCTL_IL0EN & env->config->memctl_mask;
97 env->sregs[ATOMCTL] = xtensa_option_enabled(env->config,
98 XTENSA_OPTION_ATOMCTL) ? 0x28 : 0x15;
99 env->sregs[CONFIGID0] = env->config->configid[0];
100 env->sregs[CONFIGID1] = env->config->configid[1];
101 env->exclusive_addr = -1;
102
103 #ifndef CONFIG_USER_ONLY
104 reset_mmu(env);
105 s->halted = env->runstall;
106 #endif
107 }
108
109 static ObjectClass *xtensa_cpu_class_by_name(const char *cpu_model)
110 {
111 ObjectClass *oc;
112 char *typename;
113
114 typename = g_strdup_printf(XTENSA_CPU_TYPE_NAME("%s"), cpu_model);
115 oc = object_class_by_name(typename);
116 g_free(typename);
117 if (oc == NULL || !object_class_dynamic_cast(oc, TYPE_XTENSA_CPU) ||
118 object_class_is_abstract(oc)) {
119 return NULL;
120 }
121 return oc;
122 }
123
124 static void xtensa_cpu_disas_set_info(CPUState *cs, disassemble_info *info)
125 {
126 XtensaCPU *cpu = XTENSA_CPU(cs);
127
128 info->private_data = cpu->env.config->isa;
129 info->print_insn = print_insn_xtensa;
130 }
131
132 static void xtensa_cpu_realizefn(DeviceState *dev, Error **errp)
133 {
134 CPUState *cs = CPU(dev);
135 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(dev);
136 Error *local_err = NULL;
137
138 #ifndef CONFIG_USER_ONLY
139 xtensa_irq_init(&XTENSA_CPU(dev)->env);
140 #endif
141
142 cpu_exec_realizefn(cs, &local_err);
143 if (local_err != NULL) {
144 error_propagate(errp, local_err);
145 return;
146 }
147
148 cs->gdb_num_regs = xcc->config->gdb_regmap.num_regs;
149
150 qemu_init_vcpu(cs);
151
152 xcc->parent_realize(dev, errp);
153 }
154
155 static void xtensa_cpu_initfn(Object *obj)
156 {
157 XtensaCPU *cpu = XTENSA_CPU(obj);
158 XtensaCPUClass *xcc = XTENSA_CPU_GET_CLASS(obj);
159 CPUXtensaState *env = &cpu->env;
160
161 cpu_set_cpustate_pointers(cpu);
162 env->config = xcc->config;
163
164 #ifndef CONFIG_USER_ONLY
165 env->address_space_er = g_malloc(sizeof(*env->address_space_er));
166 env->system_er = g_malloc(sizeof(*env->system_er));
167 memory_region_init_io(env->system_er, obj, NULL, env, "er",
168 UINT64_C(0x100000000));
169 address_space_init(env->address_space_er, env->system_er, "ER");
170 #endif
171 }
172
173 static const VMStateDescription vmstate_xtensa_cpu = {
174 .name = "cpu",
175 .unmigratable = 1,
176 };
177
178 static void xtensa_cpu_class_init(ObjectClass *oc, void *data)
179 {
180 DeviceClass *dc = DEVICE_CLASS(oc);
181 CPUClass *cc = CPU_CLASS(oc);
182 XtensaCPUClass *xcc = XTENSA_CPU_CLASS(cc);
183
184 device_class_set_parent_realize(dc, xtensa_cpu_realizefn,
185 &xcc->parent_realize);
186
187 cpu_class_set_parent_reset(cc, xtensa_cpu_reset, &xcc->parent_reset);
188
189 cc->class_by_name = xtensa_cpu_class_by_name;
190 cc->has_work = xtensa_cpu_has_work;
191 cc->do_interrupt = xtensa_cpu_do_interrupt;
192 cc->cpu_exec_interrupt = xtensa_cpu_exec_interrupt;
193 cc->dump_state = xtensa_cpu_dump_state;
194 cc->set_pc = xtensa_cpu_set_pc;
195 cc->gdb_read_register = xtensa_cpu_gdb_read_register;
196 cc->gdb_write_register = xtensa_cpu_gdb_write_register;
197 cc->gdb_stop_before_watchpoint = true;
198 cc->tlb_fill = xtensa_cpu_tlb_fill;
199 #ifndef CONFIG_USER_ONLY
200 cc->do_unaligned_access = xtensa_cpu_do_unaligned_access;
201 cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug;
202 cc->do_transaction_failed = xtensa_cpu_do_transaction_failed;
203 #endif
204 cc->debug_excp_handler = xtensa_breakpoint_handler;
205 cc->disas_set_info = xtensa_cpu_disas_set_info;
206 cc->tcg_initialize = xtensa_translate_init;
207 dc->vmsd = &vmstate_xtensa_cpu;
208 }
209
210 static const TypeInfo xtensa_cpu_type_info = {
211 .name = TYPE_XTENSA_CPU,
212 .parent = TYPE_CPU,
213 .instance_size = sizeof(XtensaCPU),
214 .instance_init = xtensa_cpu_initfn,
215 .abstract = true,
216 .class_size = sizeof(XtensaCPUClass),
217 .class_init = xtensa_cpu_class_init,
218 };
219
220 static void xtensa_cpu_register_types(void)
221 {
222 type_register_static(&xtensa_cpu_type_info);
223 }
224
225 type_init(xtensa_cpu_register_types)