hw/arm/raspi: fix CPRMAN base address
[qemu.git] / tcg / aarch64 / tcg-target.h
1 /*
2 * Initial TCG Implementation for aarch64
3 *
4 * Copyright (c) 2013 Huawei Technologies Duesseldorf GmbH
5 * Written by Claudio Fontana
6 *
7 * This work is licensed under the terms of the GNU GPL, version 2 or
8 * (at your option) any later version.
9 *
10 * See the COPYING file in the top-level directory for details.
11 */
12
13 #ifndef AARCH64_TCG_TARGET_H
14 #define AARCH64_TCG_TARGET_H
15
16 #define TCG_TARGET_INSN_UNIT_SIZE 4
17 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 24
18 #undef TCG_TARGET_STACK_GROWSUP
19
20 typedef enum {
21 TCG_REG_X0, TCG_REG_X1, TCG_REG_X2, TCG_REG_X3,
22 TCG_REG_X4, TCG_REG_X5, TCG_REG_X6, TCG_REG_X7,
23 TCG_REG_X8, TCG_REG_X9, TCG_REG_X10, TCG_REG_X11,
24 TCG_REG_X12, TCG_REG_X13, TCG_REG_X14, TCG_REG_X15,
25 TCG_REG_X16, TCG_REG_X17, TCG_REG_X18, TCG_REG_X19,
26 TCG_REG_X20, TCG_REG_X21, TCG_REG_X22, TCG_REG_X23,
27 TCG_REG_X24, TCG_REG_X25, TCG_REG_X26, TCG_REG_X27,
28 TCG_REG_X28, TCG_REG_X29, TCG_REG_X30,
29
30 /* X31 is either the stack pointer or zero, depending on context. */
31 TCG_REG_SP = 31,
32 TCG_REG_XZR = 31,
33
34 TCG_REG_V0 = 32, TCG_REG_V1, TCG_REG_V2, TCG_REG_V3,
35 TCG_REG_V4, TCG_REG_V5, TCG_REG_V6, TCG_REG_V7,
36 TCG_REG_V8, TCG_REG_V9, TCG_REG_V10, TCG_REG_V11,
37 TCG_REG_V12, TCG_REG_V13, TCG_REG_V14, TCG_REG_V15,
38 TCG_REG_V16, TCG_REG_V17, TCG_REG_V18, TCG_REG_V19,
39 TCG_REG_V20, TCG_REG_V21, TCG_REG_V22, TCG_REG_V23,
40 TCG_REG_V24, TCG_REG_V25, TCG_REG_V26, TCG_REG_V27,
41 TCG_REG_V28, TCG_REG_V29, TCG_REG_V30, TCG_REG_V31,
42
43 /* Aliases. */
44 TCG_REG_FP = TCG_REG_X29,
45 TCG_REG_LR = TCG_REG_X30,
46 TCG_AREG0 = TCG_REG_X19,
47 } TCGReg;
48
49 #define TCG_TARGET_NB_REGS 64
50
51 /* used for function call generation */
52 #define TCG_REG_CALL_STACK TCG_REG_SP
53 #define TCG_TARGET_STACK_ALIGN 16
54 #define TCG_TARGET_CALL_ALIGN_ARGS 1
55 #define TCG_TARGET_CALL_STACK_OFFSET 0
56
57 /* optional instructions */
58 #define TCG_TARGET_HAS_div_i32 1
59 #define TCG_TARGET_HAS_rem_i32 1
60 #define TCG_TARGET_HAS_ext8s_i32 1
61 #define TCG_TARGET_HAS_ext16s_i32 1
62 #define TCG_TARGET_HAS_ext8u_i32 1
63 #define TCG_TARGET_HAS_ext16u_i32 1
64 #define TCG_TARGET_HAS_bswap16_i32 1
65 #define TCG_TARGET_HAS_bswap32_i32 1
66 #define TCG_TARGET_HAS_not_i32 1
67 #define TCG_TARGET_HAS_neg_i32 1
68 #define TCG_TARGET_HAS_rot_i32 1
69 #define TCG_TARGET_HAS_andc_i32 1
70 #define TCG_TARGET_HAS_orc_i32 1
71 #define TCG_TARGET_HAS_eqv_i32 1
72 #define TCG_TARGET_HAS_nand_i32 0
73 #define TCG_TARGET_HAS_nor_i32 0
74 #define TCG_TARGET_HAS_clz_i32 1
75 #define TCG_TARGET_HAS_ctz_i32 1
76 #define TCG_TARGET_HAS_ctpop_i32 0
77 #define TCG_TARGET_HAS_deposit_i32 1
78 #define TCG_TARGET_HAS_extract_i32 1
79 #define TCG_TARGET_HAS_sextract_i32 1
80 #define TCG_TARGET_HAS_extract2_i32 1
81 #define TCG_TARGET_HAS_movcond_i32 1
82 #define TCG_TARGET_HAS_add2_i32 1
83 #define TCG_TARGET_HAS_sub2_i32 1
84 #define TCG_TARGET_HAS_mulu2_i32 0
85 #define TCG_TARGET_HAS_muls2_i32 0
86 #define TCG_TARGET_HAS_muluh_i32 0
87 #define TCG_TARGET_HAS_mulsh_i32 0
88 #define TCG_TARGET_HAS_extrl_i64_i32 0
89 #define TCG_TARGET_HAS_extrh_i64_i32 0
90 #define TCG_TARGET_HAS_goto_ptr 1
91
92 #define TCG_TARGET_HAS_div_i64 1
93 #define TCG_TARGET_HAS_rem_i64 1
94 #define TCG_TARGET_HAS_ext8s_i64 1
95 #define TCG_TARGET_HAS_ext16s_i64 1
96 #define TCG_TARGET_HAS_ext32s_i64 1
97 #define TCG_TARGET_HAS_ext8u_i64 1
98 #define TCG_TARGET_HAS_ext16u_i64 1
99 #define TCG_TARGET_HAS_ext32u_i64 1
100 #define TCG_TARGET_HAS_bswap16_i64 1
101 #define TCG_TARGET_HAS_bswap32_i64 1
102 #define TCG_TARGET_HAS_bswap64_i64 1
103 #define TCG_TARGET_HAS_not_i64 1
104 #define TCG_TARGET_HAS_neg_i64 1
105 #define TCG_TARGET_HAS_rot_i64 1
106 #define TCG_TARGET_HAS_andc_i64 1
107 #define TCG_TARGET_HAS_orc_i64 1
108 #define TCG_TARGET_HAS_eqv_i64 1
109 #define TCG_TARGET_HAS_nand_i64 0
110 #define TCG_TARGET_HAS_nor_i64 0
111 #define TCG_TARGET_HAS_clz_i64 1
112 #define TCG_TARGET_HAS_ctz_i64 1
113 #define TCG_TARGET_HAS_ctpop_i64 0
114 #define TCG_TARGET_HAS_deposit_i64 1
115 #define TCG_TARGET_HAS_extract_i64 1
116 #define TCG_TARGET_HAS_sextract_i64 1
117 #define TCG_TARGET_HAS_extract2_i64 1
118 #define TCG_TARGET_HAS_movcond_i64 1
119 #define TCG_TARGET_HAS_add2_i64 1
120 #define TCG_TARGET_HAS_sub2_i64 1
121 #define TCG_TARGET_HAS_mulu2_i64 0
122 #define TCG_TARGET_HAS_muls2_i64 0
123 #define TCG_TARGET_HAS_muluh_i64 1
124 #define TCG_TARGET_HAS_mulsh_i64 1
125 #define TCG_TARGET_HAS_direct_jump 1
126
127 #define TCG_TARGET_HAS_v64 1
128 #define TCG_TARGET_HAS_v128 1
129 #define TCG_TARGET_HAS_v256 0
130
131 #define TCG_TARGET_HAS_andc_vec 1
132 #define TCG_TARGET_HAS_orc_vec 1
133 #define TCG_TARGET_HAS_not_vec 1
134 #define TCG_TARGET_HAS_neg_vec 1
135 #define TCG_TARGET_HAS_abs_vec 1
136 #define TCG_TARGET_HAS_roti_vec 0
137 #define TCG_TARGET_HAS_rots_vec 0
138 #define TCG_TARGET_HAS_rotv_vec 0
139 #define TCG_TARGET_HAS_shi_vec 1
140 #define TCG_TARGET_HAS_shs_vec 0
141 #define TCG_TARGET_HAS_shv_vec 1
142 #define TCG_TARGET_HAS_mul_vec 1
143 #define TCG_TARGET_HAS_sat_vec 1
144 #define TCG_TARGET_HAS_minmax_vec 1
145 #define TCG_TARGET_HAS_bitsel_vec 1
146 #define TCG_TARGET_HAS_cmpsel_vec 0
147
148 #define TCG_TARGET_DEFAULT_MO (0)
149 #define TCG_TARGET_HAS_MEMORY_BSWAP 1
150
151 static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
152 {
153 __builtin___clear_cache((char *)start, (char *)stop);
154 }
155
156 void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t);
157
158 #ifdef CONFIG_SOFTMMU
159 #define TCG_TARGET_NEED_LDST_LABELS
160 #endif
161 #define TCG_TARGET_NEED_POOL_LABELS
162
163 #endif /* AARCH64_TCG_TARGET_H */