migration: split migration hooks out of QEMUFileOps
[qemu.git] / tcg / arm / tcg-target.h
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 * Copyright (c) 2008 Andrzej Zaborowski
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 #ifndef TCG_TARGET_ARM
26 #define TCG_TARGET_ARM 1
27
28 #undef TCG_TARGET_STACK_GROWSUP
29 #define TCG_TARGET_INSN_UNIT_SIZE 4
30 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16
31
32 typedef enum {
33 TCG_REG_R0 = 0,
34 TCG_REG_R1,
35 TCG_REG_R2,
36 TCG_REG_R3,
37 TCG_REG_R4,
38 TCG_REG_R5,
39 TCG_REG_R6,
40 TCG_REG_R7,
41 TCG_REG_R8,
42 TCG_REG_R9,
43 TCG_REG_R10,
44 TCG_REG_R11,
45 TCG_REG_R12,
46 TCG_REG_R13,
47 TCG_REG_R14,
48 TCG_REG_PC,
49 } TCGReg;
50
51 #define TCG_TARGET_NB_REGS 16
52
53 #ifdef __ARM_ARCH_EXT_IDIV__
54 #define use_idiv_instructions 1
55 #else
56 extern bool use_idiv_instructions;
57 #endif
58
59
60 /* used for function call generation */
61 #define TCG_REG_CALL_STACK TCG_REG_R13
62 #define TCG_TARGET_STACK_ALIGN 8
63 #define TCG_TARGET_CALL_ALIGN_ARGS 1
64 #define TCG_TARGET_CALL_STACK_OFFSET 0
65
66 /* optional instructions */
67 #define TCG_TARGET_HAS_ext8s_i32 1
68 #define TCG_TARGET_HAS_ext16s_i32 1
69 #define TCG_TARGET_HAS_ext8u_i32 0 /* and r0, r1, #0xff */
70 #define TCG_TARGET_HAS_ext16u_i32 1
71 #define TCG_TARGET_HAS_bswap16_i32 1
72 #define TCG_TARGET_HAS_bswap32_i32 1
73 #define TCG_TARGET_HAS_not_i32 1
74 #define TCG_TARGET_HAS_neg_i32 1
75 #define TCG_TARGET_HAS_rot_i32 1
76 #define TCG_TARGET_HAS_andc_i32 1
77 #define TCG_TARGET_HAS_orc_i32 0
78 #define TCG_TARGET_HAS_eqv_i32 0
79 #define TCG_TARGET_HAS_nand_i32 0
80 #define TCG_TARGET_HAS_nor_i32 0
81 #define TCG_TARGET_HAS_deposit_i32 1
82 #define TCG_TARGET_HAS_movcond_i32 1
83 #define TCG_TARGET_HAS_mulu2_i32 1
84 #define TCG_TARGET_HAS_muls2_i32 1
85 #define TCG_TARGET_HAS_muluh_i32 0
86 #define TCG_TARGET_HAS_mulsh_i32 0
87 #define TCG_TARGET_HAS_div_i32 use_idiv_instructions
88 #define TCG_TARGET_HAS_rem_i32 0
89
90 extern bool tcg_target_deposit_valid(int ofs, int len);
91 #define TCG_TARGET_deposit_i32_valid tcg_target_deposit_valid
92
93 enum {
94 TCG_AREG0 = TCG_REG_R6,
95 };
96
97 static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
98 {
99 #if QEMU_GNUC_PREREQ(4, 1)
100 __builtin___clear_cache((char *) start, (char *) stop);
101 #else
102 register uintptr_t _beg __asm("a1") = start;
103 register uintptr_t _end __asm("a2") = stop;
104 register uintptr_t _flg __asm("a3") = 0;
105 __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
106 #endif
107 }
108
109 #endif