Merge remote-tracking branch 'remotes/jsnow-gitlab/tags/python-pull-request' into...
[qemu.git] / tcg / mips / tcg-target.h
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a copy
9 * of this software and associated documentation files (the "Software"), to deal
10 * in the Software without restriction, including without limitation the rights
11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
12 * copies of the Software, and to permit persons to whom the Software is
13 * furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice shall be included in
16 * all copies or substantial portions of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
24 * THE SOFTWARE.
25 */
26
27 #ifndef MIPS_TCG_TARGET_H
28 #define MIPS_TCG_TARGET_H
29
30 #if _MIPS_SIM == _ABIO32
31 # define TCG_TARGET_REG_BITS 32
32 #elif _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64
33 # define TCG_TARGET_REG_BITS 64
34 #else
35 # error "Unknown ABI"
36 #endif
37
38 #define TCG_TARGET_INSN_UNIT_SIZE 4
39 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16
40 #define TCG_TARGET_NB_REGS 32
41
42 #define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1)
43
44 typedef enum {
45 TCG_REG_ZERO = 0,
46 TCG_REG_AT,
47 TCG_REG_V0,
48 TCG_REG_V1,
49 TCG_REG_A0,
50 TCG_REG_A1,
51 TCG_REG_A2,
52 TCG_REG_A3,
53 TCG_REG_T0,
54 TCG_REG_T1,
55 TCG_REG_T2,
56 TCG_REG_T3,
57 TCG_REG_T4,
58 TCG_REG_T5,
59 TCG_REG_T6,
60 TCG_REG_T7,
61 TCG_REG_S0,
62 TCG_REG_S1,
63 TCG_REG_S2,
64 TCG_REG_S3,
65 TCG_REG_S4,
66 TCG_REG_S5,
67 TCG_REG_S6,
68 TCG_REG_S7,
69 TCG_REG_T8,
70 TCG_REG_T9,
71 TCG_REG_K0,
72 TCG_REG_K1,
73 TCG_REG_GP,
74 TCG_REG_SP,
75 TCG_REG_S8,
76 TCG_REG_RA,
77
78 TCG_REG_CALL_STACK = TCG_REG_SP,
79 TCG_AREG0 = TCG_REG_S0,
80 } TCGReg;
81
82 /* used for function call generation */
83 #define TCG_TARGET_STACK_ALIGN 16
84 #if _MIPS_SIM == _ABIO32
85 # define TCG_TARGET_CALL_STACK_OFFSET 16
86 #else
87 # define TCG_TARGET_CALL_STACK_OFFSET 0
88 #endif
89 #define TCG_TARGET_CALL_ALIGN_ARGS 1
90
91 /* MOVN/MOVZ instructions detection */
92 #if (defined(__mips_isa_rev) && (__mips_isa_rev >= 1)) || \
93 defined(_MIPS_ARCH_LOONGSON2E) || defined(_MIPS_ARCH_LOONGSON2F) || \
94 defined(_MIPS_ARCH_MIPS4)
95 #define use_movnz_instructions 1
96 #else
97 extern bool use_movnz_instructions;
98 #endif
99
100 /* MIPS32 instruction set detection */
101 #if defined(__mips_isa_rev) && (__mips_isa_rev >= 1)
102 #define use_mips32_instructions 1
103 #else
104 extern bool use_mips32_instructions;
105 #endif
106
107 /* MIPS32R2 instruction set detection */
108 #if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
109 #define use_mips32r2_instructions 1
110 #else
111 extern bool use_mips32r2_instructions;
112 #endif
113
114 /* MIPS32R6 instruction set detection */
115 #if defined(__mips_isa_rev) && (__mips_isa_rev >= 6)
116 #define use_mips32r6_instructions 1
117 #else
118 #define use_mips32r6_instructions 0
119 #endif
120
121 /* optional instructions */
122 #define TCG_TARGET_HAS_div_i32 1
123 #define TCG_TARGET_HAS_rem_i32 1
124 #define TCG_TARGET_HAS_not_i32 1
125 #define TCG_TARGET_HAS_nor_i32 1
126 #define TCG_TARGET_HAS_andc_i32 0
127 #define TCG_TARGET_HAS_orc_i32 0
128 #define TCG_TARGET_HAS_eqv_i32 0
129 #define TCG_TARGET_HAS_nand_i32 0
130 #define TCG_TARGET_HAS_mulu2_i32 (!use_mips32r6_instructions)
131 #define TCG_TARGET_HAS_muls2_i32 (!use_mips32r6_instructions)
132 #define TCG_TARGET_HAS_muluh_i32 1
133 #define TCG_TARGET_HAS_mulsh_i32 1
134 #define TCG_TARGET_HAS_bswap32_i32 1
135 #define TCG_TARGET_HAS_direct_jump 0
136
137 #if TCG_TARGET_REG_BITS == 64
138 #define TCG_TARGET_HAS_add2_i32 0
139 #define TCG_TARGET_HAS_sub2_i32 0
140 #define TCG_TARGET_HAS_extrl_i64_i32 1
141 #define TCG_TARGET_HAS_extrh_i64_i32 1
142 #define TCG_TARGET_HAS_div_i64 1
143 #define TCG_TARGET_HAS_rem_i64 1
144 #define TCG_TARGET_HAS_not_i64 1
145 #define TCG_TARGET_HAS_nor_i64 1
146 #define TCG_TARGET_HAS_andc_i64 0
147 #define TCG_TARGET_HAS_orc_i64 0
148 #define TCG_TARGET_HAS_eqv_i64 0
149 #define TCG_TARGET_HAS_nand_i64 0
150 #define TCG_TARGET_HAS_add2_i64 0
151 #define TCG_TARGET_HAS_sub2_i64 0
152 #define TCG_TARGET_HAS_mulu2_i64 (!use_mips32r6_instructions)
153 #define TCG_TARGET_HAS_muls2_i64 (!use_mips32r6_instructions)
154 #define TCG_TARGET_HAS_muluh_i64 1
155 #define TCG_TARGET_HAS_mulsh_i64 1
156 #define TCG_TARGET_HAS_ext32s_i64 1
157 #define TCG_TARGET_HAS_ext32u_i64 1
158 #endif
159
160 /* optional instructions detected at runtime */
161 #define TCG_TARGET_HAS_movcond_i32 use_movnz_instructions
162 #define TCG_TARGET_HAS_bswap16_i32 use_mips32r2_instructions
163 #define TCG_TARGET_HAS_deposit_i32 use_mips32r2_instructions
164 #define TCG_TARGET_HAS_extract_i32 use_mips32r2_instructions
165 #define TCG_TARGET_HAS_sextract_i32 0
166 #define TCG_TARGET_HAS_extract2_i32 0
167 #define TCG_TARGET_HAS_ext8s_i32 use_mips32r2_instructions
168 #define TCG_TARGET_HAS_ext16s_i32 use_mips32r2_instructions
169 #define TCG_TARGET_HAS_rot_i32 use_mips32r2_instructions
170 #define TCG_TARGET_HAS_clz_i32 use_mips32r2_instructions
171 #define TCG_TARGET_HAS_ctz_i32 0
172 #define TCG_TARGET_HAS_ctpop_i32 0
173 #define TCG_TARGET_HAS_qemu_st8_i32 0
174
175 #if TCG_TARGET_REG_BITS == 64
176 #define TCG_TARGET_HAS_movcond_i64 use_movnz_instructions
177 #define TCG_TARGET_HAS_bswap16_i64 use_mips32r2_instructions
178 #define TCG_TARGET_HAS_bswap32_i64 use_mips32r2_instructions
179 #define TCG_TARGET_HAS_bswap64_i64 use_mips32r2_instructions
180 #define TCG_TARGET_HAS_deposit_i64 use_mips32r2_instructions
181 #define TCG_TARGET_HAS_extract_i64 use_mips32r2_instructions
182 #define TCG_TARGET_HAS_sextract_i64 0
183 #define TCG_TARGET_HAS_extract2_i64 0
184 #define TCG_TARGET_HAS_ext8s_i64 use_mips32r2_instructions
185 #define TCG_TARGET_HAS_ext16s_i64 use_mips32r2_instructions
186 #define TCG_TARGET_HAS_rot_i64 use_mips32r2_instructions
187 #define TCG_TARGET_HAS_clz_i64 use_mips32r2_instructions
188 #define TCG_TARGET_HAS_ctz_i64 0
189 #define TCG_TARGET_HAS_ctpop_i64 0
190 #endif
191
192 /* optional instructions automatically implemented */
193 #define TCG_TARGET_HAS_neg_i32 0 /* sub rd, zero, rt */
194 #define TCG_TARGET_HAS_ext8u_i32 0 /* andi rt, rs, 0xff */
195 #define TCG_TARGET_HAS_ext16u_i32 0 /* andi rt, rs, 0xffff */
196
197 #if TCG_TARGET_REG_BITS == 64
198 #define TCG_TARGET_HAS_neg_i64 0 /* sub rd, zero, rt */
199 #define TCG_TARGET_HAS_ext8u_i64 0 /* andi rt, rs, 0xff */
200 #define TCG_TARGET_HAS_ext16u_i64 0 /* andi rt, rs, 0xffff */
201 #endif
202
203 #define TCG_TARGET_DEFAULT_MO (0)
204 #define TCG_TARGET_HAS_MEMORY_BSWAP 1
205
206 /* not defined -- call should be eliminated at compile time */
207 void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t)
208 QEMU_ERROR("code path is reachable");
209
210 #ifdef CONFIG_SOFTMMU
211 #define TCG_TARGET_NEED_LDST_LABELS
212 #endif
213
214 #endif