hw/arm/virt: parameter passing cleanups
[qemu.git] / tcg / ppc / tcg-target.h
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #ifndef PPC_TCG_TARGET_H
26 #define PPC_TCG_TARGET_H
27
28 #ifdef _ARCH_PPC64
29 # define TCG_TARGET_REG_BITS 64
30 #else
31 # define TCG_TARGET_REG_BITS 32
32 #endif
33
34 #define TCG_TARGET_NB_REGS 32
35 #define TCG_TARGET_INSN_UNIT_SIZE 4
36 #define TCG_TARGET_TLB_DISPLACEMENT_BITS 16
37
38 typedef enum {
39 TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3,
40 TCG_REG_R4, TCG_REG_R5, TCG_REG_R6, TCG_REG_R7,
41 TCG_REG_R8, TCG_REG_R9, TCG_REG_R10, TCG_REG_R11,
42 TCG_REG_R12, TCG_REG_R13, TCG_REG_R14, TCG_REG_R15,
43 TCG_REG_R16, TCG_REG_R17, TCG_REG_R18, TCG_REG_R19,
44 TCG_REG_R20, TCG_REG_R21, TCG_REG_R22, TCG_REG_R23,
45 TCG_REG_R24, TCG_REG_R25, TCG_REG_R26, TCG_REG_R27,
46 TCG_REG_R28, TCG_REG_R29, TCG_REG_R30, TCG_REG_R31,
47
48 TCG_REG_CALL_STACK = TCG_REG_R1,
49 TCG_AREG0 = TCG_REG_R27
50 } TCGReg;
51
52 /* optional instructions automatically implemented */
53 #define TCG_TARGET_HAS_ext8u_i32 0 /* andi */
54 #define TCG_TARGET_HAS_ext16u_i32 0
55
56 /* optional instructions */
57 #define TCG_TARGET_HAS_div_i32 1
58 #define TCG_TARGET_HAS_rem_i32 0
59 #define TCG_TARGET_HAS_rot_i32 1
60 #define TCG_TARGET_HAS_ext8s_i32 1
61 #define TCG_TARGET_HAS_ext16s_i32 1
62 #define TCG_TARGET_HAS_bswap16_i32 1
63 #define TCG_TARGET_HAS_bswap32_i32 1
64 #define TCG_TARGET_HAS_not_i32 1
65 #define TCG_TARGET_HAS_neg_i32 1
66 #define TCG_TARGET_HAS_andc_i32 1
67 #define TCG_TARGET_HAS_orc_i32 1
68 #define TCG_TARGET_HAS_eqv_i32 1
69 #define TCG_TARGET_HAS_nand_i32 1
70 #define TCG_TARGET_HAS_nor_i32 1
71 #define TCG_TARGET_HAS_deposit_i32 1
72 #define TCG_TARGET_HAS_movcond_i32 1
73 #define TCG_TARGET_HAS_mulu2_i32 0
74 #define TCG_TARGET_HAS_muls2_i32 0
75 #define TCG_TARGET_HAS_muluh_i32 1
76 #define TCG_TARGET_HAS_mulsh_i32 1
77
78 #if TCG_TARGET_REG_BITS == 64
79 #define TCG_TARGET_HAS_add2_i32 0
80 #define TCG_TARGET_HAS_sub2_i32 0
81 #define TCG_TARGET_HAS_extrl_i64_i32 0
82 #define TCG_TARGET_HAS_extrh_i64_i32 0
83 #define TCG_TARGET_HAS_div_i64 1
84 #define TCG_TARGET_HAS_rem_i64 0
85 #define TCG_TARGET_HAS_rot_i64 1
86 #define TCG_TARGET_HAS_ext8s_i64 1
87 #define TCG_TARGET_HAS_ext16s_i64 1
88 #define TCG_TARGET_HAS_ext32s_i64 1
89 #define TCG_TARGET_HAS_ext8u_i64 0
90 #define TCG_TARGET_HAS_ext16u_i64 0
91 #define TCG_TARGET_HAS_ext32u_i64 0
92 #define TCG_TARGET_HAS_bswap16_i64 1
93 #define TCG_TARGET_HAS_bswap32_i64 1
94 #define TCG_TARGET_HAS_bswap64_i64 1
95 #define TCG_TARGET_HAS_not_i64 1
96 #define TCG_TARGET_HAS_neg_i64 1
97 #define TCG_TARGET_HAS_andc_i64 1
98 #define TCG_TARGET_HAS_orc_i64 1
99 #define TCG_TARGET_HAS_eqv_i64 1
100 #define TCG_TARGET_HAS_nand_i64 1
101 #define TCG_TARGET_HAS_nor_i64 1
102 #define TCG_TARGET_HAS_deposit_i64 1
103 #define TCG_TARGET_HAS_movcond_i64 1
104 #define TCG_TARGET_HAS_add2_i64 1
105 #define TCG_TARGET_HAS_sub2_i64 1
106 #define TCG_TARGET_HAS_mulu2_i64 0
107 #define TCG_TARGET_HAS_muls2_i64 0
108 #define TCG_TARGET_HAS_muluh_i64 1
109 #define TCG_TARGET_HAS_mulsh_i64 1
110 #endif
111
112 void flush_icache_range(uintptr_t start, uintptr_t stop);
113
114 #endif