tcg-ppc64: Avoid some hard-codings of TCG_TYPE_I64
[qemu.git] / tcg / ppc64 / tcg-target.c
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "tcg-be-ldst.h"
26
27 /* Shorthand for size of a pointer. Avoid promotion to unsigned. */
28 #define SZP ((int)sizeof(void *))
29
30 #define TCG_CT_CONST_S16 0x100
31 #define TCG_CT_CONST_U16 0x200
32 #define TCG_CT_CONST_S32 0x400
33 #define TCG_CT_CONST_U32 0x800
34 #define TCG_CT_CONST_ZERO 0x1000
35 #define TCG_CT_CONST_MONE 0x2000
36
37 static tcg_insn_unit *tb_ret_addr;
38
39 #if TARGET_LONG_BITS == 32
40 #define LD_ADDR LWZ
41 #define CMP_L 0
42 #else
43 #define LD_ADDR LD
44 #define CMP_L (1<<21)
45 #endif
46
47 #ifndef GUEST_BASE
48 #define GUEST_BASE 0
49 #endif
50
51 #include "elf.h"
52 static bool have_isa_2_06;
53 #define HAVE_ISA_2_06 have_isa_2_06
54 #define HAVE_ISEL have_isa_2_06
55
56 #ifdef CONFIG_USE_GUEST_BASE
57 #define TCG_GUEST_BASE_REG 30
58 #else
59 #define TCG_GUEST_BASE_REG 0
60 #endif
61
62 #ifndef NDEBUG
63 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
64 "r0",
65 "r1",
66 "r2",
67 "r3",
68 "r4",
69 "r5",
70 "r6",
71 "r7",
72 "r8",
73 "r9",
74 "r10",
75 "r11",
76 "r12",
77 "r13",
78 "r14",
79 "r15",
80 "r16",
81 "r17",
82 "r18",
83 "r19",
84 "r20",
85 "r21",
86 "r22",
87 "r23",
88 "r24",
89 "r25",
90 "r26",
91 "r27",
92 "r28",
93 "r29",
94 "r30",
95 "r31"
96 };
97 #endif
98
99 static const int tcg_target_reg_alloc_order[] = {
100 TCG_REG_R14, /* call saved registers */
101 TCG_REG_R15,
102 TCG_REG_R16,
103 TCG_REG_R17,
104 TCG_REG_R18,
105 TCG_REG_R19,
106 TCG_REG_R20,
107 TCG_REG_R21,
108 TCG_REG_R22,
109 TCG_REG_R23,
110 TCG_REG_R24,
111 TCG_REG_R25,
112 TCG_REG_R26,
113 TCG_REG_R27,
114 TCG_REG_R28,
115 TCG_REG_R29,
116 TCG_REG_R30,
117 TCG_REG_R31,
118 TCG_REG_R12, /* call clobbered, non-arguments */
119 TCG_REG_R11,
120 TCG_REG_R10, /* call clobbered, arguments */
121 TCG_REG_R9,
122 TCG_REG_R8,
123 TCG_REG_R7,
124 TCG_REG_R6,
125 TCG_REG_R5,
126 TCG_REG_R4,
127 TCG_REG_R3,
128 };
129
130 static const int tcg_target_call_iarg_regs[] = {
131 TCG_REG_R3,
132 TCG_REG_R4,
133 TCG_REG_R5,
134 TCG_REG_R6,
135 TCG_REG_R7,
136 TCG_REG_R8,
137 TCG_REG_R9,
138 TCG_REG_R10
139 };
140
141 static const int tcg_target_call_oarg_regs[] = {
142 TCG_REG_R3
143 };
144
145 static const int tcg_target_callee_save_regs[] = {
146 #ifdef __APPLE__
147 TCG_REG_R11,
148 #endif
149 TCG_REG_R14,
150 TCG_REG_R15,
151 TCG_REG_R16,
152 TCG_REG_R17,
153 TCG_REG_R18,
154 TCG_REG_R19,
155 TCG_REG_R20,
156 TCG_REG_R21,
157 TCG_REG_R22,
158 TCG_REG_R23,
159 TCG_REG_R24,
160 TCG_REG_R25,
161 TCG_REG_R26,
162 TCG_REG_R27, /* currently used for the global env */
163 TCG_REG_R28,
164 TCG_REG_R29,
165 TCG_REG_R30,
166 TCG_REG_R31
167 };
168
169 static inline bool in_range_b(tcg_target_long target)
170 {
171 return target == sextract64(target, 0, 26);
172 }
173
174 static uint32_t reloc_pc24_val(tcg_insn_unit *pc, tcg_insn_unit *target)
175 {
176 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
177 assert(in_range_b(disp));
178 return disp & 0x3fffffc;
179 }
180
181 static void reloc_pc24(tcg_insn_unit *pc, tcg_insn_unit *target)
182 {
183 *pc = (*pc & ~0x3fffffc) | reloc_pc24_val(pc, target);
184 }
185
186 static uint16_t reloc_pc14_val(tcg_insn_unit *pc, tcg_insn_unit *target)
187 {
188 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
189 assert(disp == (int16_t) disp);
190 return disp & 0xfffc;
191 }
192
193 static void reloc_pc14(tcg_insn_unit *pc, tcg_insn_unit *target)
194 {
195 *pc = (*pc & ~0xfffc) | reloc_pc14_val(pc, target);
196 }
197
198 static inline void tcg_out_b_noaddr(TCGContext *s, int insn)
199 {
200 unsigned retrans = *s->code_ptr & 0x3fffffc;
201 tcg_out32(s, insn | retrans);
202 }
203
204 static inline void tcg_out_bc_noaddr(TCGContext *s, int insn)
205 {
206 unsigned retrans = *s->code_ptr & 0xfffc;
207 tcg_out32(s, insn | retrans);
208 }
209
210 static void patch_reloc(tcg_insn_unit *code_ptr, int type,
211 intptr_t value, intptr_t addend)
212 {
213 tcg_insn_unit *target = (tcg_insn_unit *)value;
214
215 assert(addend == 0);
216 switch (type) {
217 case R_PPC_REL14:
218 reloc_pc14(code_ptr, target);
219 break;
220 case R_PPC_REL24:
221 reloc_pc24(code_ptr, target);
222 break;
223 default:
224 tcg_abort();
225 }
226 }
227
228 /* parse target specific constraints */
229 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
230 {
231 const char *ct_str;
232
233 ct_str = *pct_str;
234 switch (ct_str[0]) {
235 case 'A': case 'B': case 'C': case 'D':
236 ct->ct |= TCG_CT_REG;
237 tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
238 break;
239 case 'r':
240 ct->ct |= TCG_CT_REG;
241 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
242 break;
243 case 'L': /* qemu_ld constraint */
244 ct->ct |= TCG_CT_REG;
245 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
246 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
247 #ifdef CONFIG_SOFTMMU
248 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
249 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
250 #endif
251 break;
252 case 'S': /* qemu_st constraint */
253 ct->ct |= TCG_CT_REG;
254 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
255 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
256 #ifdef CONFIG_SOFTMMU
257 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
258 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
259 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
260 #endif
261 break;
262 case 'I':
263 ct->ct |= TCG_CT_CONST_S16;
264 break;
265 case 'J':
266 ct->ct |= TCG_CT_CONST_U16;
267 break;
268 case 'M':
269 ct->ct |= TCG_CT_CONST_MONE;
270 break;
271 case 'T':
272 ct->ct |= TCG_CT_CONST_S32;
273 break;
274 case 'U':
275 ct->ct |= TCG_CT_CONST_U32;
276 break;
277 case 'Z':
278 ct->ct |= TCG_CT_CONST_ZERO;
279 break;
280 default:
281 return -1;
282 }
283 ct_str++;
284 *pct_str = ct_str;
285 return 0;
286 }
287
288 /* test if a constant matches the constraint */
289 static int tcg_target_const_match(tcg_target_long val, TCGType type,
290 const TCGArgConstraint *arg_ct)
291 {
292 int ct = arg_ct->ct;
293 if (ct & TCG_CT_CONST) {
294 return 1;
295 }
296
297 /* The only 32-bit constraint we use aside from
298 TCG_CT_CONST is TCG_CT_CONST_S16. */
299 if (type == TCG_TYPE_I32) {
300 val = (int32_t)val;
301 }
302
303 if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
304 return 1;
305 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
306 return 1;
307 } else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
308 return 1;
309 } else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
310 return 1;
311 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
312 return 1;
313 } else if ((ct & TCG_CT_CONST_MONE) && val == -1) {
314 return 1;
315 }
316 return 0;
317 }
318
319 #define OPCD(opc) ((opc)<<26)
320 #define XO19(opc) (OPCD(19)|((opc)<<1))
321 #define MD30(opc) (OPCD(30)|((opc)<<2))
322 #define MDS30(opc) (OPCD(30)|((opc)<<1))
323 #define XO31(opc) (OPCD(31)|((opc)<<1))
324 #define XO58(opc) (OPCD(58)|(opc))
325 #define XO62(opc) (OPCD(62)|(opc))
326
327 #define B OPCD( 18)
328 #define BC OPCD( 16)
329 #define LBZ OPCD( 34)
330 #define LHZ OPCD( 40)
331 #define LHA OPCD( 42)
332 #define LWZ OPCD( 32)
333 #define STB OPCD( 38)
334 #define STH OPCD( 44)
335 #define STW OPCD( 36)
336
337 #define STD XO62( 0)
338 #define STDU XO62( 1)
339 #define STDX XO31(149)
340
341 #define LD XO58( 0)
342 #define LDX XO31( 21)
343 #define LDU XO58( 1)
344 #define LWA XO58( 2)
345 #define LWAX XO31(341)
346
347 #define ADDIC OPCD( 12)
348 #define ADDI OPCD( 14)
349 #define ADDIS OPCD( 15)
350 #define ORI OPCD( 24)
351 #define ORIS OPCD( 25)
352 #define XORI OPCD( 26)
353 #define XORIS OPCD( 27)
354 #define ANDI OPCD( 28)
355 #define ANDIS OPCD( 29)
356 #define MULLI OPCD( 7)
357 #define CMPLI OPCD( 10)
358 #define CMPI OPCD( 11)
359 #define SUBFIC OPCD( 8)
360
361 #define LWZU OPCD( 33)
362 #define STWU OPCD( 37)
363
364 #define RLWIMI OPCD( 20)
365 #define RLWINM OPCD( 21)
366 #define RLWNM OPCD( 23)
367
368 #define RLDICL MD30( 0)
369 #define RLDICR MD30( 1)
370 #define RLDIMI MD30( 3)
371 #define RLDCL MDS30( 8)
372
373 #define BCLR XO19( 16)
374 #define BCCTR XO19(528)
375 #define CRAND XO19(257)
376 #define CRANDC XO19(129)
377 #define CRNAND XO19(225)
378 #define CROR XO19(449)
379 #define CRNOR XO19( 33)
380
381 #define EXTSB XO31(954)
382 #define EXTSH XO31(922)
383 #define EXTSW XO31(986)
384 #define ADD XO31(266)
385 #define ADDE XO31(138)
386 #define ADDME XO31(234)
387 #define ADDZE XO31(202)
388 #define ADDC XO31( 10)
389 #define AND XO31( 28)
390 #define SUBF XO31( 40)
391 #define SUBFC XO31( 8)
392 #define SUBFE XO31(136)
393 #define SUBFME XO31(232)
394 #define SUBFZE XO31(200)
395 #define OR XO31(444)
396 #define XOR XO31(316)
397 #define MULLW XO31(235)
398 #define MULHWU XO31( 11)
399 #define DIVW XO31(491)
400 #define DIVWU XO31(459)
401 #define CMP XO31( 0)
402 #define CMPL XO31( 32)
403 #define LHBRX XO31(790)
404 #define LWBRX XO31(534)
405 #define LDBRX XO31(532)
406 #define STHBRX XO31(918)
407 #define STWBRX XO31(662)
408 #define STDBRX XO31(660)
409 #define MFSPR XO31(339)
410 #define MTSPR XO31(467)
411 #define SRAWI XO31(824)
412 #define NEG XO31(104)
413 #define MFCR XO31( 19)
414 #define MFOCRF (MFCR | (1u << 20))
415 #define NOR XO31(124)
416 #define CNTLZW XO31( 26)
417 #define CNTLZD XO31( 58)
418 #define ANDC XO31( 60)
419 #define ORC XO31(412)
420 #define EQV XO31(284)
421 #define NAND XO31(476)
422 #define ISEL XO31( 15)
423
424 #define MULLD XO31(233)
425 #define MULHD XO31( 73)
426 #define MULHDU XO31( 9)
427 #define DIVD XO31(489)
428 #define DIVDU XO31(457)
429
430 #define LBZX XO31( 87)
431 #define LHZX XO31(279)
432 #define LHAX XO31(343)
433 #define LWZX XO31( 23)
434 #define STBX XO31(215)
435 #define STHX XO31(407)
436 #define STWX XO31(151)
437
438 #define SPR(a, b) ((((a)<<5)|(b))<<11)
439 #define LR SPR(8, 0)
440 #define CTR SPR(9, 0)
441
442 #define SLW XO31( 24)
443 #define SRW XO31(536)
444 #define SRAW XO31(792)
445
446 #define SLD XO31( 27)
447 #define SRD XO31(539)
448 #define SRAD XO31(794)
449 #define SRADI XO31(413<<1)
450
451 #define TW XO31( 4)
452 #define TRAP (TW | TO(31))
453
454 #define RT(r) ((r)<<21)
455 #define RS(r) ((r)<<21)
456 #define RA(r) ((r)<<16)
457 #define RB(r) ((r)<<11)
458 #define TO(t) ((t)<<21)
459 #define SH(s) ((s)<<11)
460 #define MB(b) ((b)<<6)
461 #define ME(e) ((e)<<1)
462 #define BO(o) ((o)<<21)
463 #define MB64(b) ((b)<<5)
464 #define FXM(b) (1 << (19 - (b)))
465
466 #define LK 1
467
468 #define TAB(t, a, b) (RT(t) | RA(a) | RB(b))
469 #define SAB(s, a, b) (RS(s) | RA(a) | RB(b))
470 #define TAI(s, a, i) (RT(s) | RA(a) | ((i) & 0xffff))
471 #define SAI(s, a, i) (RS(s) | RA(a) | ((i) & 0xffff))
472
473 #define BF(n) ((n)<<23)
474 #define BI(n, c) (((c)+((n)*4))<<16)
475 #define BT(n, c) (((c)+((n)*4))<<21)
476 #define BA(n, c) (((c)+((n)*4))<<16)
477 #define BB(n, c) (((c)+((n)*4))<<11)
478 #define BC_(n, c) (((c)+((n)*4))<<6)
479
480 #define BO_COND_TRUE BO(12)
481 #define BO_COND_FALSE BO( 4)
482 #define BO_ALWAYS BO(20)
483
484 enum {
485 CR_LT,
486 CR_GT,
487 CR_EQ,
488 CR_SO
489 };
490
491 static const uint32_t tcg_to_bc[] = {
492 [TCG_COND_EQ] = BC | BI(7, CR_EQ) | BO_COND_TRUE,
493 [TCG_COND_NE] = BC | BI(7, CR_EQ) | BO_COND_FALSE,
494 [TCG_COND_LT] = BC | BI(7, CR_LT) | BO_COND_TRUE,
495 [TCG_COND_GE] = BC | BI(7, CR_LT) | BO_COND_FALSE,
496 [TCG_COND_LE] = BC | BI(7, CR_GT) | BO_COND_FALSE,
497 [TCG_COND_GT] = BC | BI(7, CR_GT) | BO_COND_TRUE,
498 [TCG_COND_LTU] = BC | BI(7, CR_LT) | BO_COND_TRUE,
499 [TCG_COND_GEU] = BC | BI(7, CR_LT) | BO_COND_FALSE,
500 [TCG_COND_LEU] = BC | BI(7, CR_GT) | BO_COND_FALSE,
501 [TCG_COND_GTU] = BC | BI(7, CR_GT) | BO_COND_TRUE,
502 };
503
504 /* The low bit here is set if the RA and RB fields must be inverted. */
505 static const uint32_t tcg_to_isel[] = {
506 [TCG_COND_EQ] = ISEL | BC_(7, CR_EQ),
507 [TCG_COND_NE] = ISEL | BC_(7, CR_EQ) | 1,
508 [TCG_COND_LT] = ISEL | BC_(7, CR_LT),
509 [TCG_COND_GE] = ISEL | BC_(7, CR_LT) | 1,
510 [TCG_COND_LE] = ISEL | BC_(7, CR_GT) | 1,
511 [TCG_COND_GT] = ISEL | BC_(7, CR_GT),
512 [TCG_COND_LTU] = ISEL | BC_(7, CR_LT),
513 [TCG_COND_GEU] = ISEL | BC_(7, CR_LT) | 1,
514 [TCG_COND_LEU] = ISEL | BC_(7, CR_GT) | 1,
515 [TCG_COND_GTU] = ISEL | BC_(7, CR_GT),
516 };
517
518 static inline void tcg_out_mov(TCGContext *s, TCGType type,
519 TCGReg ret, TCGReg arg)
520 {
521 if (ret != arg) {
522 tcg_out32(s, OR | SAB(arg, ret, arg));
523 }
524 }
525
526 static inline void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs,
527 int sh, int mb)
528 {
529 sh = SH(sh & 0x1f) | (((sh >> 5) & 1) << 1);
530 mb = MB64((mb >> 5) | ((mb << 1) & 0x3f));
531 tcg_out32(s, op | RA(ra) | RS(rs) | sh | mb);
532 }
533
534 static inline void tcg_out_rlw(TCGContext *s, int op, TCGReg ra, TCGReg rs,
535 int sh, int mb, int me)
536 {
537 tcg_out32(s, op | RA(ra) | RS(rs) | SH(sh) | MB(mb) | ME(me));
538 }
539
540 static inline void tcg_out_ext32u(TCGContext *s, TCGReg dst, TCGReg src)
541 {
542 tcg_out_rld(s, RLDICL, dst, src, 0, 32);
543 }
544
545 static inline void tcg_out_shli64(TCGContext *s, TCGReg dst, TCGReg src, int c)
546 {
547 tcg_out_rld(s, RLDICR, dst, src, c, 63 - c);
548 }
549
550 static inline void tcg_out_shri64(TCGContext *s, TCGReg dst, TCGReg src, int c)
551 {
552 tcg_out_rld(s, RLDICL, dst, src, 64 - c, c);
553 }
554
555 static void tcg_out_movi32(TCGContext *s, TCGReg ret, int32_t arg)
556 {
557 if (arg == (int16_t) arg) {
558 tcg_out32(s, ADDI | TAI(ret, 0, arg));
559 } else {
560 tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16));
561 if (arg & 0xffff) {
562 tcg_out32(s, ORI | SAI(ret, ret, arg));
563 }
564 }
565 }
566
567 static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret,
568 tcg_target_long arg)
569 {
570 if (type == TCG_TYPE_I32 || arg == (int32_t)arg) {
571 tcg_out_movi32(s, ret, arg);
572 } else if (arg == (uint32_t)arg && !(arg & 0x8000)) {
573 tcg_out32(s, ADDI | TAI(ret, 0, arg));
574 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
575 } else {
576 int32_t high = arg >> 32;
577 tcg_out_movi32(s, ret, high);
578 if (high) {
579 tcg_out_shli64(s, ret, ret, 32);
580 }
581 if (arg & 0xffff0000) {
582 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
583 }
584 if (arg & 0xffff) {
585 tcg_out32(s, ORI | SAI(ret, ret, arg));
586 }
587 }
588 }
589
590 static bool mask_operand(uint32_t c, int *mb, int *me)
591 {
592 uint32_t lsb, test;
593
594 /* Accept a bit pattern like:
595 0....01....1
596 1....10....0
597 0..01..10..0
598 Keep track of the transitions. */
599 if (c == 0 || c == -1) {
600 return false;
601 }
602 test = c;
603 lsb = test & -test;
604 test += lsb;
605 if (test & (test - 1)) {
606 return false;
607 }
608
609 *me = clz32(lsb);
610 *mb = test ? clz32(test & -test) + 1 : 0;
611 return true;
612 }
613
614 static bool mask64_operand(uint64_t c, int *mb, int *me)
615 {
616 uint64_t lsb;
617
618 if (c == 0) {
619 return false;
620 }
621
622 lsb = c & -c;
623 /* Accept 1..10..0. */
624 if (c == -lsb) {
625 *mb = 0;
626 *me = clz64(lsb);
627 return true;
628 }
629 /* Accept 0..01..1. */
630 if (lsb == 1 && (c & (c + 1)) == 0) {
631 *mb = clz64(c + 1) + 1;
632 *me = 63;
633 return true;
634 }
635 return false;
636 }
637
638 static void tcg_out_andi32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
639 {
640 int mb, me;
641
642 if ((c & 0xffff) == c) {
643 tcg_out32(s, ANDI | SAI(src, dst, c));
644 return;
645 } else if ((c & 0xffff0000) == c) {
646 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
647 return;
648 } else if (mask_operand(c, &mb, &me)) {
649 tcg_out_rlw(s, RLWINM, dst, src, 0, mb, me);
650 } else {
651 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R0, c);
652 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
653 }
654 }
655
656 static void tcg_out_andi64(TCGContext *s, TCGReg dst, TCGReg src, uint64_t c)
657 {
658 int mb, me;
659
660 if ((c & 0xffff) == c) {
661 tcg_out32(s, ANDI | SAI(src, dst, c));
662 return;
663 } else if ((c & 0xffff0000) == c) {
664 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
665 return;
666 } else if (mask64_operand(c, &mb, &me)) {
667 if (mb == 0) {
668 tcg_out_rld(s, RLDICR, dst, src, 0, me);
669 } else {
670 tcg_out_rld(s, RLDICL, dst, src, 0, mb);
671 }
672 } else {
673 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, c);
674 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
675 }
676 }
677
678 static void tcg_out_zori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c,
679 int op_lo, int op_hi)
680 {
681 if (c >> 16) {
682 tcg_out32(s, op_hi | SAI(src, dst, c >> 16));
683 src = dst;
684 }
685 if (c & 0xffff) {
686 tcg_out32(s, op_lo | SAI(src, dst, c));
687 src = dst;
688 }
689 }
690
691 static void tcg_out_ori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
692 {
693 tcg_out_zori32(s, dst, src, c, ORI, ORIS);
694 }
695
696 static void tcg_out_xori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
697 {
698 tcg_out_zori32(s, dst, src, c, XORI, XORIS);
699 }
700
701 static void tcg_out_b(TCGContext *s, int mask, tcg_insn_unit *target)
702 {
703 ptrdiff_t disp = tcg_pcrel_diff(s, target);
704 if (in_range_b(disp)) {
705 tcg_out32(s, B | (disp & 0x3fffffc) | mask);
706 } else {
707 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, (uintptr_t)target);
708 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | CTR);
709 tcg_out32(s, BCCTR | BO_ALWAYS | mask);
710 }
711 }
712
713 static void tcg_out_call(TCGContext *s, tcg_insn_unit *target)
714 {
715 #ifdef __APPLE__
716 tcg_out_b(s, LK, target);
717 #else
718 /* Look through the descriptor. If the branch is in range, and we
719 don't have to spend too much effort on building the toc. */
720 void *tgt = ((void **)target)[0];
721 uintptr_t toc = ((uintptr_t *)target)[1];
722 intptr_t diff = tcg_pcrel_diff(s, tgt);
723
724 if (in_range_b(diff) && toc == (uint32_t)toc) {
725 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, toc);
726 tcg_out_b(s, LK, tgt);
727 } else {
728 /* Fold the low bits of the constant into the addresses below. */
729 intptr_t arg = (intptr_t)target;
730 int ofs = (int16_t)arg;
731
732 if (ofs + 8 < 0x8000) {
733 arg -= ofs;
734 } else {
735 ofs = 0;
736 }
737 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg);
738 tcg_out32(s, LD | TAI(TCG_REG_R0, TCG_REG_R2, ofs));
739 tcg_out32(s, MTSPR | RA(TCG_REG_R0) | CTR);
740 tcg_out32(s, LD | TAI(TCG_REG_R2, TCG_REG_R2, ofs + 8));
741 tcg_out32(s, BCCTR | BO_ALWAYS | LK);
742 }
743 #endif
744 }
745
746 static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
747 TCGReg base, tcg_target_long offset)
748 {
749 tcg_target_long orig = offset, l0, l1, extra = 0, align = 0;
750 TCGReg rs = TCG_REG_R2;
751
752 assert(rt != TCG_REG_R2 && base != TCG_REG_R2);
753
754 switch (opi) {
755 case LD: case LWA:
756 align = 3;
757 /* FALLTHRU */
758 default:
759 if (rt != TCG_REG_R0) {
760 rs = rt;
761 }
762 break;
763 case STD:
764 align = 3;
765 break;
766 case STB: case STH: case STW:
767 break;
768 }
769
770 /* For unaligned, or very large offsets, use the indexed form. */
771 if (offset & align || offset != (int32_t)offset) {
772 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, orig);
773 tcg_out32(s, opx | TAB(rt, base, TCG_REG_R2));
774 return;
775 }
776
777 l0 = (int16_t)offset;
778 offset = (offset - l0) >> 16;
779 l1 = (int16_t)offset;
780
781 if (l1 < 0 && orig >= 0) {
782 extra = 0x4000;
783 l1 = (int16_t)(offset - 0x4000);
784 }
785 if (l1) {
786 tcg_out32(s, ADDIS | TAI(rs, base, l1));
787 base = rs;
788 }
789 if (extra) {
790 tcg_out32(s, ADDIS | TAI(rs, base, extra));
791 base = rs;
792 }
793 if (opi != ADDI || base != rt || l0 != 0) {
794 tcg_out32(s, opi | TAI(rt, base, l0));
795 }
796 }
797
798 static const uint32_t qemu_ldx_opc[16] = {
799 [MO_UB] = LBZX,
800 [MO_UW] = LHZX,
801 [MO_UL] = LWZX,
802 [MO_Q] = LDX,
803 [MO_SW] = LHAX,
804 [MO_SL] = LWAX,
805 [MO_BSWAP | MO_UB] = LBZX,
806 [MO_BSWAP | MO_UW] = LHBRX,
807 [MO_BSWAP | MO_UL] = LWBRX,
808 [MO_BSWAP | MO_Q] = LDBRX,
809 };
810
811 static const uint32_t qemu_stx_opc[16] = {
812 [MO_UB] = STBX,
813 [MO_UW] = STHX,
814 [MO_UL] = STWX,
815 [MO_Q] = STDX,
816 [MO_BSWAP | MO_UB] = STBX,
817 [MO_BSWAP | MO_UW] = STHBRX,
818 [MO_BSWAP | MO_UL] = STWBRX,
819 [MO_BSWAP | MO_Q] = STDBRX,
820 };
821
822 static const uint32_t qemu_exts_opc[4] = {
823 EXTSB, EXTSH, EXTSW, 0
824 };
825
826 #if defined (CONFIG_SOFTMMU)
827 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
828 * int mmu_idx, uintptr_t ra)
829 */
830 static void * const qemu_ld_helpers[16] = {
831 [MO_UB] = helper_ret_ldub_mmu,
832 [MO_LEUW] = helper_le_lduw_mmu,
833 [MO_LEUL] = helper_le_ldul_mmu,
834 [MO_LEQ] = helper_le_ldq_mmu,
835 [MO_BEUW] = helper_be_lduw_mmu,
836 [MO_BEUL] = helper_be_ldul_mmu,
837 [MO_BEQ] = helper_be_ldq_mmu,
838 };
839
840 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
841 * uintxx_t val, int mmu_idx, uintptr_t ra)
842 */
843 static void * const qemu_st_helpers[16] = {
844 [MO_UB] = helper_ret_stb_mmu,
845 [MO_LEUW] = helper_le_stw_mmu,
846 [MO_LEUL] = helper_le_stl_mmu,
847 [MO_LEQ] = helper_le_stq_mmu,
848 [MO_BEUW] = helper_be_stw_mmu,
849 [MO_BEUL] = helper_be_stl_mmu,
850 [MO_BEQ] = helper_be_stq_mmu,
851 };
852
853 /* Perform the TLB load and compare. Places the result of the comparison
854 in CR7, loads the addend of the TLB into R3, and returns the register
855 containing the guest address (zero-extended into R4). Clobbers R0 and R2. */
856
857 static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp s_bits, TCGReg addr_reg,
858 int mem_index, bool is_read)
859 {
860 int cmp_off
861 = (is_read
862 ? offsetof(CPUArchState, tlb_table[mem_index][0].addr_read)
863 : offsetof(CPUArchState, tlb_table[mem_index][0].addr_write));
864 int add_off = offsetof(CPUArchState, tlb_table[mem_index][0].addend);
865 TCGReg base = TCG_AREG0;
866
867 /* Extract the page index, shifted into place for tlb index. */
868 if (TARGET_LONG_BITS == 32) {
869 /* Zero-extend the address into a place helpful for further use. */
870 tcg_out_ext32u(s, TCG_REG_R4, addr_reg);
871 addr_reg = TCG_REG_R4;
872 } else {
873 tcg_out_rld(s, RLDICL, TCG_REG_R3, addr_reg,
874 64 - TARGET_PAGE_BITS, 64 - CPU_TLB_BITS);
875 }
876
877 /* Compensate for very large offsets. */
878 if (add_off >= 0x8000) {
879 /* Most target env are smaller than 32k; none are larger than 64k.
880 Simplify the logic here merely to offset by 0x7ff0, giving us a
881 range just shy of 64k. Check this assumption. */
882 QEMU_BUILD_BUG_ON(offsetof(CPUArchState,
883 tlb_table[NB_MMU_MODES - 1][1])
884 > 0x7ff0 + 0x7fff);
885 tcg_out32(s, ADDI | TAI(TCG_REG_R2, base, 0x7ff0));
886 base = TCG_REG_R2;
887 cmp_off -= 0x7ff0;
888 add_off -= 0x7ff0;
889 }
890
891 /* Extraction and shifting, part 2. */
892 if (TARGET_LONG_BITS == 32) {
893 tcg_out_rlw(s, RLWINM, TCG_REG_R3, addr_reg,
894 32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
895 32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS),
896 31 - CPU_TLB_ENTRY_BITS);
897 } else {
898 tcg_out_shli64(s, TCG_REG_R3, TCG_REG_R3, CPU_TLB_ENTRY_BITS);
899 }
900
901 tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, base));
902
903 /* Load the tlb comparator. */
904 tcg_out32(s, LD_ADDR | TAI(TCG_REG_R2, TCG_REG_R3, cmp_off));
905
906 /* Load the TLB addend for use on the fast path. Do this asap
907 to minimize any load use delay. */
908 tcg_out32(s, LD | TAI(TCG_REG_R3, TCG_REG_R3, add_off));
909
910 /* Clear the non-page, non-alignment bits from the address. */
911 if (TARGET_LONG_BITS == 32) {
912 tcg_out_rlw(s, RLWINM, TCG_REG_R0, addr_reg, 0,
913 (32 - s_bits) & 31, 31 - TARGET_PAGE_BITS);
914 } else if (!s_bits) {
915 tcg_out_rld(s, RLDICR, TCG_REG_R0, addr_reg, 0, 63 - TARGET_PAGE_BITS);
916 } else {
917 tcg_out_rld(s, RLDICL, TCG_REG_R0, addr_reg,
918 64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - s_bits);
919 tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BITS, 0);
920 }
921
922 tcg_out32(s, CMP | BF(7) | RA(TCG_REG_R0) | RB(TCG_REG_R2) | CMP_L);
923
924 return addr_reg;
925 }
926
927 /* Record the context of a call to the out of line helper code for the slow
928 path for a load or store, so that we can later generate the correct
929 helper code. */
930 static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOp opc,
931 int data_reg, int addr_reg, int mem_index,
932 tcg_insn_unit *raddr, tcg_insn_unit *label_ptr)
933 {
934 TCGLabelQemuLdst *label = new_ldst_label(s);
935
936 label->is_ld = is_ld;
937 label->opc = opc;
938 label->datalo_reg = data_reg;
939 label->addrlo_reg = addr_reg;
940 label->mem_index = mem_index;
941 label->raddr = raddr;
942 label->label_ptr[0] = label_ptr;
943 }
944
945 static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
946 {
947 TCGMemOp opc = lb->opc;
948
949 reloc_pc14(lb->label_ptr[0], s->code_ptr);
950
951 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_AREG0);
952
953 /* If the address needed to be zero-extended, we'll have already
954 placed it in R4. The only remaining case is 64-bit guest. */
955 tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R4, lb->addrlo_reg);
956
957 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R5, lb->mem_index);
958 tcg_out32(s, MFSPR | RT(TCG_REG_R6) | LR);
959
960 tcg_out_call(s, qemu_ld_helpers[opc & ~MO_SIGN]);
961
962 if (opc & MO_SIGN) {
963 uint32_t insn = qemu_exts_opc[opc & MO_SIZE];
964 tcg_out32(s, insn | RA(lb->datalo_reg) | RS(TCG_REG_R3));
965 } else {
966 tcg_out_mov(s, TCG_TYPE_I64, lb->datalo_reg, TCG_REG_R3);
967 }
968
969 tcg_out_b(s, 0, lb->raddr);
970 }
971
972 static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
973 {
974 TCGMemOp opc = lb->opc;
975 TCGMemOp s_bits = opc & MO_SIZE;
976
977 reloc_pc14(lb->label_ptr[0], s->code_ptr);
978
979 tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R3, TCG_AREG0);
980
981 /* If the address needed to be zero-extended, we'll have already
982 placed it in R4. The only remaining case is 64-bit guest. */
983 tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R4, lb->addrlo_reg);
984
985 tcg_out_rld(s, RLDICL, TCG_REG_R5, lb->datalo_reg,
986 0, 64 - (1 << (3 + s_bits)));
987 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R6, lb->mem_index);
988 tcg_out32(s, MFSPR | RT(TCG_REG_R7) | LR);
989
990 tcg_out_call(s, qemu_st_helpers[opc]);
991
992 tcg_out_b(s, 0, lb->raddr);
993 }
994 #endif /* SOFTMMU */
995
996 static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
997 TCGMemOp opc, int mem_index)
998 {
999 TCGReg rbase;
1000 uint32_t insn;
1001 TCGMemOp s_bits = opc & MO_SIZE;
1002 #ifdef CONFIG_SOFTMMU
1003 tcg_insn_unit *label_ptr;
1004 #endif
1005
1006 #ifdef CONFIG_SOFTMMU
1007 addr_reg = tcg_out_tlb_read(s, s_bits, addr_reg, mem_index, true);
1008
1009 /* Load a pointer into the current opcode w/conditional branch-link. */
1010 label_ptr = s->code_ptr;
1011 tcg_out_bc_noaddr(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
1012
1013 rbase = TCG_REG_R3;
1014 #else /* !CONFIG_SOFTMMU */
1015 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
1016 if (TARGET_LONG_BITS == 32) {
1017 tcg_out_ext32u(s, TCG_REG_R2, addr_reg);
1018 addr_reg = TCG_REG_R2;
1019 }
1020 #endif
1021
1022 insn = qemu_ldx_opc[opc];
1023 if (!HAVE_ISA_2_06 && insn == LDBRX) {
1024 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addr_reg, 4));
1025 tcg_out32(s, LWBRX | TAB(data_reg, rbase, addr_reg));
1026 tcg_out32(s, LWBRX | TAB(TCG_REG_R0, rbase, TCG_REG_R0));
1027 tcg_out_rld(s, RLDIMI, data_reg, TCG_REG_R0, 32, 0);
1028 } else if (insn) {
1029 tcg_out32(s, insn | TAB(data_reg, rbase, addr_reg));
1030 } else {
1031 insn = qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)];
1032 tcg_out32(s, insn | TAB(data_reg, rbase, addr_reg));
1033 insn = qemu_exts_opc[s_bits];
1034 tcg_out32(s, insn | RA(data_reg) | RS(data_reg));
1035 }
1036
1037 #ifdef CONFIG_SOFTMMU
1038 add_qemu_ldst_label(s, true, opc, data_reg, addr_reg, mem_index,
1039 s->code_ptr, label_ptr);
1040 #endif
1041 }
1042
1043 static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
1044 TCGMemOp opc, int mem_index)
1045 {
1046 TCGReg rbase;
1047 uint32_t insn;
1048 #ifdef CONFIG_SOFTMMU
1049 tcg_insn_unit *label_ptr;
1050 #endif
1051
1052 #ifdef CONFIG_SOFTMMU
1053 addr_reg = tcg_out_tlb_read(s, opc & MO_SIZE, addr_reg, mem_index, false);
1054
1055 /* Load a pointer into the current opcode w/conditional branch-link. */
1056 label_ptr = s->code_ptr;
1057 tcg_out_bc_noaddr(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
1058
1059 rbase = TCG_REG_R3;
1060 #else /* !CONFIG_SOFTMMU */
1061 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
1062 if (TARGET_LONG_BITS == 32) {
1063 tcg_out_ext32u(s, TCG_REG_R2, addr_reg);
1064 addr_reg = TCG_REG_R2;
1065 }
1066 #endif
1067
1068 insn = qemu_stx_opc[opc];
1069 if (!HAVE_ISA_2_06 && insn == STDBRX) {
1070 tcg_out32(s, STWBRX | SAB(data_reg, rbase, addr_reg));
1071 tcg_out32(s, ADDI | TAI(TCG_REG_R2, addr_reg, 4));
1072 tcg_out_shri64(s, TCG_REG_R0, data_reg, 32);
1073 tcg_out32(s, STWBRX | SAB(TCG_REG_R0, rbase, TCG_REG_R2));
1074 } else {
1075 tcg_out32(s, insn | SAB(data_reg, rbase, addr_reg));
1076 }
1077
1078 #ifdef CONFIG_SOFTMMU
1079 add_qemu_ldst_label(s, false, opc, data_reg, addr_reg, mem_index,
1080 s->code_ptr, label_ptr);
1081 #endif
1082 }
1083
1084 #define FRAME_SIZE ((int) \
1085 ((8 /* back chain */ \
1086 + 8 /* CR */ \
1087 + 8 /* LR */ \
1088 + 8 /* compiler doubleword */ \
1089 + 8 /* link editor doubleword */ \
1090 + 8 /* TOC save area */ \
1091 + TCG_STATIC_CALL_ARGS_SIZE \
1092 + CPU_TEMP_BUF_NLONGS * sizeof(long) \
1093 + ARRAY_SIZE(tcg_target_callee_save_regs) * 8 \
1094 + 15) & ~15))
1095
1096 #define REG_SAVE_BOT (FRAME_SIZE - ARRAY_SIZE(tcg_target_callee_save_regs) * 8)
1097
1098 static void tcg_target_qemu_prologue(TCGContext *s)
1099 {
1100 int i;
1101
1102 tcg_set_frame(s, TCG_REG_CALL_STACK,
1103 REG_SAVE_BOT - CPU_TEMP_BUF_NLONGS * sizeof(long),
1104 CPU_TEMP_BUF_NLONGS * sizeof(long));
1105
1106 #ifndef __APPLE__
1107 /* First emit adhoc function descriptor */
1108 tcg_out64(s, (uint64_t)s->code_ptr + 24); /* entry point */
1109 tcg_out64(s, 0); /* toc */
1110 tcg_out64(s, 0); /* environment pointer */
1111 #endif
1112
1113 /* Prologue */
1114 tcg_out32(s, MFSPR | RT(TCG_REG_R0) | LR);
1115 tcg_out32(s, STDU | SAI(TCG_REG_R1, TCG_REG_R1, -FRAME_SIZE));
1116 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
1117 tcg_out32(s, STD | SAI(tcg_target_callee_save_regs[i], 1,
1118 REG_SAVE_BOT + i * 8));
1119 }
1120 tcg_out32(s, STD | SAI(TCG_REG_R0, TCG_REG_R1, FRAME_SIZE + 16));
1121
1122 #ifdef CONFIG_USE_GUEST_BASE
1123 if (GUEST_BASE) {
1124 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, GUEST_BASE);
1125 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
1126 }
1127 #endif
1128
1129 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
1130 tcg_out32(s, MTSPR | RS(tcg_target_call_iarg_regs[1]) | CTR);
1131 tcg_out32(s, BCCTR | BO_ALWAYS);
1132
1133 /* Epilogue */
1134 tb_ret_addr = s->code_ptr;
1135
1136 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
1137 tcg_out32(s, LD | TAI(tcg_target_callee_save_regs[i], TCG_REG_R1,
1138 REG_SAVE_BOT + i * 8));
1139 }
1140 tcg_out32(s, LD | TAI(TCG_REG_R0, TCG_REG_R1, FRAME_SIZE + 16));
1141 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | LR);
1142 tcg_out32(s, ADDI | TAI(TCG_REG_R1, TCG_REG_R1, FRAME_SIZE));
1143 tcg_out32(s, BCLR | BO_ALWAYS);
1144 }
1145
1146 static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
1147 TCGReg arg1, intptr_t arg2)
1148 {
1149 int opi, opx;
1150
1151 if (type == TCG_TYPE_I32) {
1152 opi = LWZ, opx = LWZX;
1153 } else {
1154 opi = LD, opx = LDX;
1155 }
1156 tcg_out_mem_long(s, opi, opx, ret, arg1, arg2);
1157 }
1158
1159 static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
1160 TCGReg arg1, intptr_t arg2)
1161 {
1162 int opi, opx;
1163
1164 if (type == TCG_TYPE_I32) {
1165 opi = STW, opx = STWX;
1166 } else {
1167 opi = STD, opx = STDX;
1168 }
1169 tcg_out_mem_long(s, opi, opx, arg, arg1, arg2);
1170 }
1171
1172 static void tcg_out_cmp(TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
1173 int const_arg2, int cr, TCGType type)
1174 {
1175 int imm;
1176 uint32_t op;
1177
1178 /* Simplify the comparisons below wrt CMPI. */
1179 if (type == TCG_TYPE_I32) {
1180 arg2 = (int32_t)arg2;
1181 }
1182
1183 switch (cond) {
1184 case TCG_COND_EQ:
1185 case TCG_COND_NE:
1186 if (const_arg2) {
1187 if ((int16_t) arg2 == arg2) {
1188 op = CMPI;
1189 imm = 1;
1190 break;
1191 } else if ((uint16_t) arg2 == arg2) {
1192 op = CMPLI;
1193 imm = 1;
1194 break;
1195 }
1196 }
1197 op = CMPL;
1198 imm = 0;
1199 break;
1200
1201 case TCG_COND_LT:
1202 case TCG_COND_GE:
1203 case TCG_COND_LE:
1204 case TCG_COND_GT:
1205 if (const_arg2) {
1206 if ((int16_t) arg2 == arg2) {
1207 op = CMPI;
1208 imm = 1;
1209 break;
1210 }
1211 }
1212 op = CMP;
1213 imm = 0;
1214 break;
1215
1216 case TCG_COND_LTU:
1217 case TCG_COND_GEU:
1218 case TCG_COND_LEU:
1219 case TCG_COND_GTU:
1220 if (const_arg2) {
1221 if ((uint16_t) arg2 == arg2) {
1222 op = CMPLI;
1223 imm = 1;
1224 break;
1225 }
1226 }
1227 op = CMPL;
1228 imm = 0;
1229 break;
1230
1231 default:
1232 tcg_abort();
1233 }
1234 op |= BF(cr) | ((type == TCG_TYPE_I64) << 21);
1235
1236 if (imm) {
1237 tcg_out32(s, op | RA(arg1) | (arg2 & 0xffff));
1238 } else {
1239 if (const_arg2) {
1240 tcg_out_movi(s, type, TCG_REG_R0, arg2);
1241 arg2 = TCG_REG_R0;
1242 }
1243 tcg_out32(s, op | RA(arg1) | RB(arg2));
1244 }
1245 }
1246
1247 static void tcg_out_setcond_eq0(TCGContext *s, TCGType type,
1248 TCGReg dst, TCGReg src)
1249 {
1250 tcg_out32(s, (type == TCG_TYPE_I64 ? CNTLZD : CNTLZW) | RS(src) | RA(dst));
1251 tcg_out_shri64(s, dst, dst, type == TCG_TYPE_I64 ? 6 : 5);
1252 }
1253
1254 static void tcg_out_setcond_ne0(TCGContext *s, TCGReg dst, TCGReg src)
1255 {
1256 /* X != 0 implies X + -1 generates a carry. Extra addition
1257 trickery means: R = X-1 + ~X + C = X-1 + (-X+1) + C = C. */
1258 if (dst != src) {
1259 tcg_out32(s, ADDIC | TAI(dst, src, -1));
1260 tcg_out32(s, SUBFE | TAB(dst, dst, src));
1261 } else {
1262 tcg_out32(s, ADDIC | TAI(TCG_REG_R0, src, -1));
1263 tcg_out32(s, SUBFE | TAB(dst, TCG_REG_R0, src));
1264 }
1265 }
1266
1267 static TCGReg tcg_gen_setcond_xor(TCGContext *s, TCGReg arg1, TCGArg arg2,
1268 bool const_arg2)
1269 {
1270 if (const_arg2) {
1271 if ((uint32_t)arg2 == arg2) {
1272 tcg_out_xori32(s, TCG_REG_R0, arg1, arg2);
1273 } else {
1274 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, arg2);
1275 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, TCG_REG_R0));
1276 }
1277 } else {
1278 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, arg2));
1279 }
1280 return TCG_REG_R0;
1281 }
1282
1283 static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond,
1284 TCGArg arg0, TCGArg arg1, TCGArg arg2,
1285 int const_arg2)
1286 {
1287 int crop, sh;
1288
1289 /* Ignore high bits of a potential constant arg2. */
1290 if (type == TCG_TYPE_I32) {
1291 arg2 = (uint32_t)arg2;
1292 }
1293
1294 /* Handle common and trivial cases before handling anything else. */
1295 if (arg2 == 0) {
1296 switch (cond) {
1297 case TCG_COND_EQ:
1298 tcg_out_setcond_eq0(s, type, arg0, arg1);
1299 return;
1300 case TCG_COND_NE:
1301 if (type == TCG_TYPE_I32) {
1302 tcg_out_ext32u(s, TCG_REG_R0, arg1);
1303 arg1 = TCG_REG_R0;
1304 }
1305 tcg_out_setcond_ne0(s, arg0, arg1);
1306 return;
1307 case TCG_COND_GE:
1308 tcg_out32(s, NOR | SAB(arg1, arg0, arg1));
1309 arg1 = arg0;
1310 /* FALLTHRU */
1311 case TCG_COND_LT:
1312 /* Extract the sign bit. */
1313 tcg_out_rld(s, RLDICL, arg0, arg1,
1314 type == TCG_TYPE_I64 ? 1 : 33, 63);
1315 return;
1316 default:
1317 break;
1318 }
1319 }
1320
1321 /* If we have ISEL, we can implement everything with 3 or 4 insns.
1322 All other cases below are also at least 3 insns, so speed up the
1323 code generator by not considering them and always using ISEL. */
1324 if (HAVE_ISEL) {
1325 int isel, tab;
1326
1327 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1328
1329 isel = tcg_to_isel[cond];
1330
1331 tcg_out_movi(s, type, arg0, 1);
1332 if (isel & 1) {
1333 /* arg0 = (bc ? 0 : 1) */
1334 tab = TAB(arg0, 0, arg0);
1335 isel &= ~1;
1336 } else {
1337 /* arg0 = (bc ? 1 : 0) */
1338 tcg_out_movi(s, type, TCG_REG_R0, 0);
1339 tab = TAB(arg0, arg0, TCG_REG_R0);
1340 }
1341 tcg_out32(s, isel | tab);
1342 return;
1343 }
1344
1345 switch (cond) {
1346 case TCG_COND_EQ:
1347 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
1348 tcg_out_setcond_eq0(s, type, arg0, arg1);
1349 return;
1350
1351 case TCG_COND_NE:
1352 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
1353 /* Discard the high bits only once, rather than both inputs. */
1354 if (type == TCG_TYPE_I32) {
1355 tcg_out_ext32u(s, TCG_REG_R0, arg1);
1356 arg1 = TCG_REG_R0;
1357 }
1358 tcg_out_setcond_ne0(s, arg0, arg1);
1359 return;
1360
1361 case TCG_COND_GT:
1362 case TCG_COND_GTU:
1363 sh = 30;
1364 crop = 0;
1365 goto crtest;
1366
1367 case TCG_COND_LT:
1368 case TCG_COND_LTU:
1369 sh = 29;
1370 crop = 0;
1371 goto crtest;
1372
1373 case TCG_COND_GE:
1374 case TCG_COND_GEU:
1375 sh = 31;
1376 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_LT) | BB(7, CR_LT);
1377 goto crtest;
1378
1379 case TCG_COND_LE:
1380 case TCG_COND_LEU:
1381 sh = 31;
1382 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_GT) | BB(7, CR_GT);
1383 crtest:
1384 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1385 if (crop) {
1386 tcg_out32(s, crop);
1387 }
1388 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7));
1389 tcg_out_rlw(s, RLWINM, arg0, TCG_REG_R0, sh, 31, 31);
1390 break;
1391
1392 default:
1393 tcg_abort();
1394 }
1395 }
1396
1397 static void tcg_out_bc(TCGContext *s, int bc, int label_index)
1398 {
1399 TCGLabel *l = &s->labels[label_index];
1400
1401 if (l->has_value) {
1402 tcg_out32(s, bc | reloc_pc14_val(s->code_ptr, l->u.value_ptr));
1403 } else {
1404 tcg_out_reloc(s, s->code_ptr, R_PPC_REL14, label_index, 0);
1405 tcg_out_bc_noaddr(s, bc);
1406 }
1407 }
1408
1409 static void tcg_out_brcond(TCGContext *s, TCGCond cond,
1410 TCGArg arg1, TCGArg arg2, int const_arg2,
1411 int label_index, TCGType type)
1412 {
1413 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1414 tcg_out_bc(s, tcg_to_bc[cond], label_index);
1415 }
1416
1417 static void tcg_out_movcond(TCGContext *s, TCGType type, TCGCond cond,
1418 TCGArg dest, TCGArg c1, TCGArg c2, TCGArg v1,
1419 TCGArg v2, bool const_c2)
1420 {
1421 /* If for some reason both inputs are zero, don't produce bad code. */
1422 if (v1 == 0 && v2 == 0) {
1423 tcg_out_movi(s, type, dest, 0);
1424 return;
1425 }
1426
1427 tcg_out_cmp(s, cond, c1, c2, const_c2, 7, type);
1428
1429 if (HAVE_ISEL) {
1430 int isel = tcg_to_isel[cond];
1431
1432 /* Swap the V operands if the operation indicates inversion. */
1433 if (isel & 1) {
1434 int t = v1;
1435 v1 = v2;
1436 v2 = t;
1437 isel &= ~1;
1438 }
1439 /* V1 == 0 is handled by isel; V2 == 0 must be handled by hand. */
1440 if (v2 == 0) {
1441 tcg_out_movi(s, type, TCG_REG_R0, 0);
1442 }
1443 tcg_out32(s, isel | TAB(dest, v1, v2));
1444 } else {
1445 if (dest == v2) {
1446 cond = tcg_invert_cond(cond);
1447 v2 = v1;
1448 } else if (dest != v1) {
1449 if (v1 == 0) {
1450 tcg_out_movi(s, type, dest, 0);
1451 } else {
1452 tcg_out_mov(s, type, dest, v1);
1453 }
1454 }
1455 /* Branch forward over one insn */
1456 tcg_out32(s, tcg_to_bc[cond] | 8);
1457 if (v2 == 0) {
1458 tcg_out_movi(s, type, dest, 0);
1459 } else {
1460 tcg_out_mov(s, type, dest, v2);
1461 }
1462 }
1463 }
1464
1465 void ppc_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr)
1466 {
1467 TCGContext s;
1468
1469 s.code_buf = s.code_ptr = (tcg_insn_unit *)jmp_addr;
1470 tcg_out_b(&s, 0, (tcg_insn_unit *)addr);
1471 flush_icache_range(jmp_addr, jmp_addr + tcg_current_code_size(&s));
1472 }
1473
1474 static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
1475 const int *const_args)
1476 {
1477 TCGArg a0, a1, a2;
1478 int c;
1479
1480 switch (opc) {
1481 case INDEX_op_exit_tb:
1482 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, args[0]);
1483 tcg_out_b(s, 0, tb_ret_addr);
1484 break;
1485 case INDEX_op_goto_tb:
1486 if (s->tb_jmp_offset) {
1487 /* Direct jump method. */
1488 s->tb_jmp_offset[args[0]] = tcg_current_code_size(s);
1489 s->code_ptr += 7;
1490 } else {
1491 /* Indirect jump method. */
1492 tcg_abort();
1493 }
1494 s->tb_next_offset[args[0]] = tcg_current_code_size(s);
1495 break;
1496 case INDEX_op_br:
1497 {
1498 TCGLabel *l = &s->labels[args[0]];
1499
1500 if (l->has_value) {
1501 tcg_out_b(s, 0, l->u.value_ptr);
1502 } else {
1503 tcg_out_reloc(s, s->code_ptr, R_PPC_REL24, args[0], 0);
1504 tcg_out_b_noaddr(s, B);
1505 }
1506 }
1507 break;
1508 case INDEX_op_ld8u_i32:
1509 case INDEX_op_ld8u_i64:
1510 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
1511 break;
1512 case INDEX_op_ld8s_i32:
1513 case INDEX_op_ld8s_i64:
1514 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
1515 tcg_out32(s, EXTSB | RS(args[0]) | RA(args[0]));
1516 break;
1517 case INDEX_op_ld16u_i32:
1518 case INDEX_op_ld16u_i64:
1519 tcg_out_mem_long(s, LHZ, LHZX, args[0], args[1], args[2]);
1520 break;
1521 case INDEX_op_ld16s_i32:
1522 case INDEX_op_ld16s_i64:
1523 tcg_out_mem_long(s, LHA, LHAX, args[0], args[1], args[2]);
1524 break;
1525 case INDEX_op_ld_i32:
1526 case INDEX_op_ld32u_i64:
1527 tcg_out_mem_long(s, LWZ, LWZX, args[0], args[1], args[2]);
1528 break;
1529 case INDEX_op_ld32s_i64:
1530 tcg_out_mem_long(s, LWA, LWAX, args[0], args[1], args[2]);
1531 break;
1532 case INDEX_op_ld_i64:
1533 tcg_out_mem_long(s, LD, LDX, args[0], args[1], args[2]);
1534 break;
1535 case INDEX_op_st8_i32:
1536 case INDEX_op_st8_i64:
1537 tcg_out_mem_long(s, STB, STBX, args[0], args[1], args[2]);
1538 break;
1539 case INDEX_op_st16_i32:
1540 case INDEX_op_st16_i64:
1541 tcg_out_mem_long(s, STH, STHX, args[0], args[1], args[2]);
1542 break;
1543 case INDEX_op_st_i32:
1544 case INDEX_op_st32_i64:
1545 tcg_out_mem_long(s, STW, STWX, args[0], args[1], args[2]);
1546 break;
1547 case INDEX_op_st_i64:
1548 tcg_out_mem_long(s, STD, STDX, args[0], args[1], args[2]);
1549 break;
1550
1551 case INDEX_op_add_i32:
1552 a0 = args[0], a1 = args[1], a2 = args[2];
1553 if (const_args[2]) {
1554 do_addi_32:
1555 tcg_out_mem_long(s, ADDI, ADD, a0, a1, (int32_t)a2);
1556 } else {
1557 tcg_out32(s, ADD | TAB(a0, a1, a2));
1558 }
1559 break;
1560 case INDEX_op_sub_i32:
1561 a0 = args[0], a1 = args[1], a2 = args[2];
1562 if (const_args[1]) {
1563 if (const_args[2]) {
1564 tcg_out_movi(s, TCG_TYPE_I32, a0, a1 - a2);
1565 } else {
1566 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
1567 }
1568 } else if (const_args[2]) {
1569 a2 = -a2;
1570 goto do_addi_32;
1571 } else {
1572 tcg_out32(s, SUBF | TAB(a0, a2, a1));
1573 }
1574 break;
1575
1576 case INDEX_op_and_i32:
1577 a0 = args[0], a1 = args[1], a2 = args[2];
1578 if (const_args[2]) {
1579 tcg_out_andi32(s, a0, a1, a2);
1580 } else {
1581 tcg_out32(s, AND | SAB(a1, a0, a2));
1582 }
1583 break;
1584 case INDEX_op_and_i64:
1585 a0 = args[0], a1 = args[1], a2 = args[2];
1586 if (const_args[2]) {
1587 tcg_out_andi64(s, a0, a1, a2);
1588 } else {
1589 tcg_out32(s, AND | SAB(a1, a0, a2));
1590 }
1591 break;
1592 case INDEX_op_or_i64:
1593 case INDEX_op_or_i32:
1594 a0 = args[0], a1 = args[1], a2 = args[2];
1595 if (const_args[2]) {
1596 tcg_out_ori32(s, a0, a1, a2);
1597 } else {
1598 tcg_out32(s, OR | SAB(a1, a0, a2));
1599 }
1600 break;
1601 case INDEX_op_xor_i64:
1602 case INDEX_op_xor_i32:
1603 a0 = args[0], a1 = args[1], a2 = args[2];
1604 if (const_args[2]) {
1605 tcg_out_xori32(s, a0, a1, a2);
1606 } else {
1607 tcg_out32(s, XOR | SAB(a1, a0, a2));
1608 }
1609 break;
1610 case INDEX_op_andc_i32:
1611 a0 = args[0], a1 = args[1], a2 = args[2];
1612 if (const_args[2]) {
1613 tcg_out_andi32(s, a0, a1, ~a2);
1614 } else {
1615 tcg_out32(s, ANDC | SAB(a1, a0, a2));
1616 }
1617 break;
1618 case INDEX_op_andc_i64:
1619 a0 = args[0], a1 = args[1], a2 = args[2];
1620 if (const_args[2]) {
1621 tcg_out_andi64(s, a0, a1, ~a2);
1622 } else {
1623 tcg_out32(s, ANDC | SAB(a1, a0, a2));
1624 }
1625 break;
1626 case INDEX_op_orc_i32:
1627 if (const_args[2]) {
1628 tcg_out_ori32(s, args[0], args[1], ~args[2]);
1629 break;
1630 }
1631 /* FALLTHRU */
1632 case INDEX_op_orc_i64:
1633 tcg_out32(s, ORC | SAB(args[1], args[0], args[2]));
1634 break;
1635 case INDEX_op_eqv_i32:
1636 if (const_args[2]) {
1637 tcg_out_xori32(s, args[0], args[1], ~args[2]);
1638 break;
1639 }
1640 /* FALLTHRU */
1641 case INDEX_op_eqv_i64:
1642 tcg_out32(s, EQV | SAB(args[1], args[0], args[2]));
1643 break;
1644 case INDEX_op_nand_i32:
1645 case INDEX_op_nand_i64:
1646 tcg_out32(s, NAND | SAB(args[1], args[0], args[2]));
1647 break;
1648 case INDEX_op_nor_i32:
1649 case INDEX_op_nor_i64:
1650 tcg_out32(s, NOR | SAB(args[1], args[0], args[2]));
1651 break;
1652
1653 case INDEX_op_mul_i32:
1654 a0 = args[0], a1 = args[1], a2 = args[2];
1655 if (const_args[2]) {
1656 tcg_out32(s, MULLI | TAI(a0, a1, a2));
1657 } else {
1658 tcg_out32(s, MULLW | TAB(a0, a1, a2));
1659 }
1660 break;
1661
1662 case INDEX_op_div_i32:
1663 tcg_out32(s, DIVW | TAB(args[0], args[1], args[2]));
1664 break;
1665
1666 case INDEX_op_divu_i32:
1667 tcg_out32(s, DIVWU | TAB(args[0], args[1], args[2]));
1668 break;
1669
1670 case INDEX_op_shl_i32:
1671 if (const_args[2]) {
1672 tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31 - args[2]);
1673 } else {
1674 tcg_out32(s, SLW | SAB(args[1], args[0], args[2]));
1675 }
1676 break;
1677 case INDEX_op_shr_i32:
1678 if (const_args[2]) {
1679 tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], args[2], 31);
1680 } else {
1681 tcg_out32(s, SRW | SAB(args[1], args[0], args[2]));
1682 }
1683 break;
1684 case INDEX_op_sar_i32:
1685 if (const_args[2]) {
1686 tcg_out32(s, SRAWI | RS(args[1]) | RA(args[0]) | SH(args[2]));
1687 } else {
1688 tcg_out32(s, SRAW | SAB(args[1], args[0], args[2]));
1689 }
1690 break;
1691 case INDEX_op_rotl_i32:
1692 if (const_args[2]) {
1693 tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31);
1694 } else {
1695 tcg_out32(s, RLWNM | SAB(args[1], args[0], args[2])
1696 | MB(0) | ME(31));
1697 }
1698 break;
1699 case INDEX_op_rotr_i32:
1700 if (const_args[2]) {
1701 tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], 0, 31);
1702 } else {
1703 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 32));
1704 tcg_out32(s, RLWNM | SAB(args[1], args[0], TCG_REG_R0)
1705 | MB(0) | ME(31));
1706 }
1707 break;
1708
1709 case INDEX_op_brcond_i32:
1710 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1711 args[3], TCG_TYPE_I32);
1712 break;
1713
1714 case INDEX_op_brcond_i64:
1715 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1716 args[3], TCG_TYPE_I64);
1717 break;
1718
1719 case INDEX_op_neg_i32:
1720 case INDEX_op_neg_i64:
1721 tcg_out32(s, NEG | RT(args[0]) | RA(args[1]));
1722 break;
1723
1724 case INDEX_op_not_i32:
1725 case INDEX_op_not_i64:
1726 tcg_out32(s, NOR | SAB(args[1], args[0], args[1]));
1727 break;
1728
1729 case INDEX_op_add_i64:
1730 a0 = args[0], a1 = args[1], a2 = args[2];
1731 if (const_args[2]) {
1732 do_addi_64:
1733 tcg_out_mem_long(s, ADDI, ADD, a0, a1, a2);
1734 } else {
1735 tcg_out32(s, ADD | TAB(a0, a1, a2));
1736 }
1737 break;
1738 case INDEX_op_sub_i64:
1739 a0 = args[0], a1 = args[1], a2 = args[2];
1740 if (const_args[1]) {
1741 if (const_args[2]) {
1742 tcg_out_movi(s, TCG_TYPE_I64, a0, a1 - a2);
1743 } else {
1744 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
1745 }
1746 } else if (const_args[2]) {
1747 a2 = -a2;
1748 goto do_addi_64;
1749 } else {
1750 tcg_out32(s, SUBF | TAB(a0, a2, a1));
1751 }
1752 break;
1753
1754 case INDEX_op_shl_i64:
1755 if (const_args[2]) {
1756 tcg_out_shli64(s, args[0], args[1], args[2]);
1757 } else {
1758 tcg_out32(s, SLD | SAB(args[1], args[0], args[2]));
1759 }
1760 break;
1761 case INDEX_op_shr_i64:
1762 if (const_args[2]) {
1763 tcg_out_shri64(s, args[0], args[1], args[2]);
1764 } else {
1765 tcg_out32(s, SRD | SAB(args[1], args[0], args[2]));
1766 }
1767 break;
1768 case INDEX_op_sar_i64:
1769 if (const_args[2]) {
1770 int sh = SH(args[2] & 0x1f) | (((args[2] >> 5) & 1) << 1);
1771 tcg_out32(s, SRADI | RA(args[0]) | RS(args[1]) | sh);
1772 } else {
1773 tcg_out32(s, SRAD | SAB(args[1], args[0], args[2]));
1774 }
1775 break;
1776 case INDEX_op_rotl_i64:
1777 if (const_args[2]) {
1778 tcg_out_rld(s, RLDICL, args[0], args[1], args[2], 0);
1779 } else {
1780 tcg_out32(s, RLDCL | SAB(args[1], args[0], args[2]) | MB64(0));
1781 }
1782 break;
1783 case INDEX_op_rotr_i64:
1784 if (const_args[2]) {
1785 tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 0);
1786 } else {
1787 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 64));
1788 tcg_out32(s, RLDCL | SAB(args[1], args[0], TCG_REG_R0) | MB64(0));
1789 }
1790 break;
1791
1792 case INDEX_op_mul_i64:
1793 a0 = args[0], a1 = args[1], a2 = args[2];
1794 if (const_args[2]) {
1795 tcg_out32(s, MULLI | TAI(a0, a1, a2));
1796 } else {
1797 tcg_out32(s, MULLD | TAB(a0, a1, a2));
1798 }
1799 break;
1800 case INDEX_op_div_i64:
1801 tcg_out32(s, DIVD | TAB(args[0], args[1], args[2]));
1802 break;
1803 case INDEX_op_divu_i64:
1804 tcg_out32(s, DIVDU | TAB(args[0], args[1], args[2]));
1805 break;
1806
1807 case INDEX_op_qemu_ld_i32:
1808 case INDEX_op_qemu_ld_i64:
1809 tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3]);
1810 break;
1811 case INDEX_op_qemu_st_i32:
1812 case INDEX_op_qemu_st_i64:
1813 tcg_out_qemu_st(s, args[0], args[1], args[2], args[3]);
1814 break;
1815
1816 case INDEX_op_ext8s_i32:
1817 case INDEX_op_ext8s_i64:
1818 c = EXTSB;
1819 goto gen_ext;
1820 case INDEX_op_ext16s_i32:
1821 case INDEX_op_ext16s_i64:
1822 c = EXTSH;
1823 goto gen_ext;
1824 case INDEX_op_ext32s_i64:
1825 c = EXTSW;
1826 goto gen_ext;
1827 gen_ext:
1828 tcg_out32(s, c | RS(args[1]) | RA(args[0]));
1829 break;
1830
1831 case INDEX_op_setcond_i32:
1832 tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2],
1833 const_args[2]);
1834 break;
1835 case INDEX_op_setcond_i64:
1836 tcg_out_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], args[2],
1837 const_args[2]);
1838 break;
1839
1840 case INDEX_op_bswap16_i32:
1841 case INDEX_op_bswap16_i64:
1842 a0 = args[0], a1 = args[1];
1843 /* a1 = abcd */
1844 if (a0 != a1) {
1845 /* a0 = (a1 r<< 24) & 0xff # 000c */
1846 tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
1847 /* a0 = (a0 & ~0xff00) | (a1 r<< 8) & 0xff00 # 00dc */
1848 tcg_out_rlw(s, RLWIMI, a0, a1, 8, 16, 23);
1849 } else {
1850 /* r0 = (a1 r<< 8) & 0xff00 # 00d0 */
1851 tcg_out_rlw(s, RLWINM, TCG_REG_R0, a1, 8, 16, 23);
1852 /* a0 = (a1 r<< 24) & 0xff # 000c */
1853 tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
1854 /* a0 = a0 | r0 # 00dc */
1855 tcg_out32(s, OR | SAB(TCG_REG_R0, a0, a0));
1856 }
1857 break;
1858
1859 case INDEX_op_bswap32_i32:
1860 case INDEX_op_bswap32_i64:
1861 /* Stolen from gcc's builtin_bswap32 */
1862 a1 = args[1];
1863 a0 = args[0] == a1 ? TCG_REG_R0 : args[0];
1864
1865 /* a1 = args[1] # abcd */
1866 /* a0 = rotate_left (a1, 8) # bcda */
1867 tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
1868 /* a0 = (a0 & ~0xff000000) | ((a1 r<< 24) & 0xff000000) # dcda */
1869 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
1870 /* a0 = (a0 & ~0x0000ff00) | ((a1 r<< 24) & 0x0000ff00) # dcba */
1871 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
1872
1873 if (a0 == TCG_REG_R0) {
1874 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
1875 }
1876 break;
1877
1878 case INDEX_op_bswap64_i64:
1879 a0 = args[0], a1 = args[1], a2 = TCG_REG_R0;
1880 if (a0 == a1) {
1881 a0 = TCG_REG_R0;
1882 a2 = a1;
1883 }
1884
1885 /* a1 = # abcd efgh */
1886 /* a0 = rl32(a1, 8) # 0000 fghe */
1887 tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
1888 /* a0 = dep(a0, rl32(a1, 24), 0xff000000) # 0000 hghe */
1889 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
1890 /* a0 = dep(a0, rl32(a1, 24), 0x0000ff00) # 0000 hgfe */
1891 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
1892
1893 /* a0 = rl64(a0, 32) # hgfe 0000 */
1894 /* a2 = rl64(a1, 32) # efgh abcd */
1895 tcg_out_rld(s, RLDICL, a0, a0, 32, 0);
1896 tcg_out_rld(s, RLDICL, a2, a1, 32, 0);
1897
1898 /* a0 = dep(a0, rl32(a2, 8), 0xffffffff) # hgfe bcda */
1899 tcg_out_rlw(s, RLWIMI, a0, a2, 8, 0, 31);
1900 /* a0 = dep(a0, rl32(a2, 24), 0xff000000) # hgfe dcda */
1901 tcg_out_rlw(s, RLWIMI, a0, a2, 24, 0, 7);
1902 /* a0 = dep(a0, rl32(a2, 24), 0x0000ff00) # hgfe dcba */
1903 tcg_out_rlw(s, RLWIMI, a0, a2, 24, 16, 23);
1904
1905 if (a0 == 0) {
1906 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
1907 }
1908 break;
1909
1910 case INDEX_op_deposit_i32:
1911 if (const_args[2]) {
1912 uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3];
1913 tcg_out_andi32(s, args[0], args[0], ~mask);
1914 } else {
1915 tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3],
1916 32 - args[3] - args[4], 31 - args[3]);
1917 }
1918 break;
1919 case INDEX_op_deposit_i64:
1920 if (const_args[2]) {
1921 uint64_t mask = ((2ull << (args[4] - 1)) - 1) << args[3];
1922 tcg_out_andi64(s, args[0], args[0], ~mask);
1923 } else {
1924 tcg_out_rld(s, RLDIMI, args[0], args[2], args[3],
1925 64 - args[3] - args[4]);
1926 }
1927 break;
1928
1929 case INDEX_op_movcond_i32:
1930 tcg_out_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], args[2],
1931 args[3], args[4], const_args[2]);
1932 break;
1933 case INDEX_op_movcond_i64:
1934 tcg_out_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], args[2],
1935 args[3], args[4], const_args[2]);
1936 break;
1937
1938 case INDEX_op_add2_i64:
1939 /* Note that the CA bit is defined based on the word size of the
1940 environment. So in 64-bit mode it's always carry-out of bit 63.
1941 The fallback code using deposit works just as well for 32-bit. */
1942 a0 = args[0], a1 = args[1];
1943 if (a0 == args[3] || (!const_args[5] && a0 == args[5])) {
1944 a0 = TCG_REG_R0;
1945 }
1946 if (const_args[4]) {
1947 tcg_out32(s, ADDIC | TAI(a0, args[2], args[4]));
1948 } else {
1949 tcg_out32(s, ADDC | TAB(a0, args[2], args[4]));
1950 }
1951 if (const_args[5]) {
1952 tcg_out32(s, (args[5] ? ADDME : ADDZE) | RT(a1) | RA(args[3]));
1953 } else {
1954 tcg_out32(s, ADDE | TAB(a1, args[3], args[5]));
1955 }
1956 if (a0 != args[0]) {
1957 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
1958 }
1959 break;
1960
1961 case INDEX_op_sub2_i64:
1962 a0 = args[0], a1 = args[1];
1963 if (a0 == args[5] || (!const_args[4] && a0 == args[4])) {
1964 a0 = TCG_REG_R0;
1965 }
1966 if (const_args[2]) {
1967 tcg_out32(s, SUBFIC | TAI(a0, args[3], args[2]));
1968 } else {
1969 tcg_out32(s, SUBFC | TAB(a0, args[3], args[2]));
1970 }
1971 if (const_args[4]) {
1972 tcg_out32(s, (args[4] ? SUBFME : SUBFZE) | RT(a1) | RA(args[5]));
1973 } else {
1974 tcg_out32(s, SUBFE | TAB(a1, args[5], args[4]));
1975 }
1976 if (a0 != args[0]) {
1977 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
1978 }
1979 break;
1980
1981 case INDEX_op_muluh_i64:
1982 tcg_out32(s, MULHDU | TAB(args[0], args[1], args[2]));
1983 break;
1984 case INDEX_op_mulsh_i64:
1985 tcg_out32(s, MULHD | TAB(args[0], args[1], args[2]));
1986 break;
1987
1988 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
1989 case INDEX_op_mov_i64:
1990 case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
1991 case INDEX_op_movi_i64:
1992 case INDEX_op_call: /* Always emitted via tcg_out_call. */
1993 default:
1994 tcg_abort();
1995 }
1996 }
1997
1998 static const TCGTargetOpDef ppc_op_defs[] = {
1999 { INDEX_op_exit_tb, { } },
2000 { INDEX_op_goto_tb, { } },
2001 { INDEX_op_br, { } },
2002
2003 { INDEX_op_ld8u_i32, { "r", "r" } },
2004 { INDEX_op_ld8s_i32, { "r", "r" } },
2005 { INDEX_op_ld16u_i32, { "r", "r" } },
2006 { INDEX_op_ld16s_i32, { "r", "r" } },
2007 { INDEX_op_ld_i32, { "r", "r" } },
2008 { INDEX_op_ld_i64, { "r", "r" } },
2009 { INDEX_op_st8_i32, { "r", "r" } },
2010 { INDEX_op_st8_i64, { "r", "r" } },
2011 { INDEX_op_st16_i32, { "r", "r" } },
2012 { INDEX_op_st16_i64, { "r", "r" } },
2013 { INDEX_op_st_i32, { "r", "r" } },
2014 { INDEX_op_st_i64, { "r", "r" } },
2015 { INDEX_op_st32_i64, { "r", "r" } },
2016
2017 { INDEX_op_ld8u_i64, { "r", "r" } },
2018 { INDEX_op_ld8s_i64, { "r", "r" } },
2019 { INDEX_op_ld16u_i64, { "r", "r" } },
2020 { INDEX_op_ld16s_i64, { "r", "r" } },
2021 { INDEX_op_ld32u_i64, { "r", "r" } },
2022 { INDEX_op_ld32s_i64, { "r", "r" } },
2023
2024 { INDEX_op_add_i32, { "r", "r", "ri" } },
2025 { INDEX_op_mul_i32, { "r", "r", "rI" } },
2026 { INDEX_op_div_i32, { "r", "r", "r" } },
2027 { INDEX_op_divu_i32, { "r", "r", "r" } },
2028 { INDEX_op_sub_i32, { "r", "rI", "ri" } },
2029 { INDEX_op_and_i32, { "r", "r", "ri" } },
2030 { INDEX_op_or_i32, { "r", "r", "ri" } },
2031 { INDEX_op_xor_i32, { "r", "r", "ri" } },
2032 { INDEX_op_andc_i32, { "r", "r", "ri" } },
2033 { INDEX_op_orc_i32, { "r", "r", "ri" } },
2034 { INDEX_op_eqv_i32, { "r", "r", "ri" } },
2035 { INDEX_op_nand_i32, { "r", "r", "r" } },
2036 { INDEX_op_nor_i32, { "r", "r", "r" } },
2037
2038 { INDEX_op_shl_i32, { "r", "r", "ri" } },
2039 { INDEX_op_shr_i32, { "r", "r", "ri" } },
2040 { INDEX_op_sar_i32, { "r", "r", "ri" } },
2041 { INDEX_op_rotl_i32, { "r", "r", "ri" } },
2042 { INDEX_op_rotr_i32, { "r", "r", "ri" } },
2043
2044 { INDEX_op_brcond_i32, { "r", "ri" } },
2045 { INDEX_op_brcond_i64, { "r", "ri" } },
2046
2047 { INDEX_op_neg_i32, { "r", "r" } },
2048 { INDEX_op_not_i32, { "r", "r" } },
2049
2050 { INDEX_op_add_i64, { "r", "r", "rT" } },
2051 { INDEX_op_sub_i64, { "r", "rI", "rT" } },
2052 { INDEX_op_and_i64, { "r", "r", "ri" } },
2053 { INDEX_op_or_i64, { "r", "r", "rU" } },
2054 { INDEX_op_xor_i64, { "r", "r", "rU" } },
2055 { INDEX_op_andc_i64, { "r", "r", "ri" } },
2056 { INDEX_op_orc_i64, { "r", "r", "r" } },
2057 { INDEX_op_eqv_i64, { "r", "r", "r" } },
2058 { INDEX_op_nand_i64, { "r", "r", "r" } },
2059 { INDEX_op_nor_i64, { "r", "r", "r" } },
2060
2061 { INDEX_op_shl_i64, { "r", "r", "ri" } },
2062 { INDEX_op_shr_i64, { "r", "r", "ri" } },
2063 { INDEX_op_sar_i64, { "r", "r", "ri" } },
2064 { INDEX_op_rotl_i64, { "r", "r", "ri" } },
2065 { INDEX_op_rotr_i64, { "r", "r", "ri" } },
2066
2067 { INDEX_op_mul_i64, { "r", "r", "rI" } },
2068 { INDEX_op_div_i64, { "r", "r", "r" } },
2069 { INDEX_op_divu_i64, { "r", "r", "r" } },
2070
2071 { INDEX_op_neg_i64, { "r", "r" } },
2072 { INDEX_op_not_i64, { "r", "r" } },
2073
2074 { INDEX_op_qemu_ld_i32, { "r", "L" } },
2075 { INDEX_op_qemu_ld_i64, { "r", "L" } },
2076 { INDEX_op_qemu_st_i32, { "S", "S" } },
2077 { INDEX_op_qemu_st_i64, { "S", "S" } },
2078
2079 { INDEX_op_ext8s_i32, { "r", "r" } },
2080 { INDEX_op_ext16s_i32, { "r", "r" } },
2081 { INDEX_op_ext8s_i64, { "r", "r" } },
2082 { INDEX_op_ext16s_i64, { "r", "r" } },
2083 { INDEX_op_ext32s_i64, { "r", "r" } },
2084
2085 { INDEX_op_setcond_i32, { "r", "r", "ri" } },
2086 { INDEX_op_setcond_i64, { "r", "r", "ri" } },
2087 { INDEX_op_movcond_i32, { "r", "r", "ri", "rZ", "rZ" } },
2088 { INDEX_op_movcond_i64, { "r", "r", "ri", "rZ", "rZ" } },
2089
2090 { INDEX_op_bswap16_i32, { "r", "r" } },
2091 { INDEX_op_bswap16_i64, { "r", "r" } },
2092 { INDEX_op_bswap32_i32, { "r", "r" } },
2093 { INDEX_op_bswap32_i64, { "r", "r" } },
2094 { INDEX_op_bswap64_i64, { "r", "r" } },
2095
2096 { INDEX_op_deposit_i32, { "r", "0", "rZ" } },
2097 { INDEX_op_deposit_i64, { "r", "0", "rZ" } },
2098
2099 { INDEX_op_add2_i64, { "r", "r", "r", "r", "rI", "rZM" } },
2100 { INDEX_op_sub2_i64, { "r", "r", "rI", "r", "rZM", "r" } },
2101 { INDEX_op_mulsh_i64, { "r", "r", "r" } },
2102 { INDEX_op_muluh_i64, { "r", "r", "r" } },
2103
2104 { -1 },
2105 };
2106
2107 static void tcg_target_init(TCGContext *s)
2108 {
2109 unsigned long hwcap = qemu_getauxval(AT_HWCAP);
2110 if (hwcap & PPC_FEATURE_ARCH_2_06) {
2111 have_isa_2_06 = true;
2112 }
2113
2114 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
2115 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
2116 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
2117 (1 << TCG_REG_R0) |
2118 (1 << TCG_REG_R2) |
2119 (1 << TCG_REG_R3) |
2120 (1 << TCG_REG_R4) |
2121 (1 << TCG_REG_R5) |
2122 (1 << TCG_REG_R6) |
2123 (1 << TCG_REG_R7) |
2124 (1 << TCG_REG_R8) |
2125 (1 << TCG_REG_R9) |
2126 (1 << TCG_REG_R10) |
2127 (1 << TCG_REG_R11) |
2128 (1 << TCG_REG_R12));
2129
2130 tcg_regset_clear(s->reserved_regs);
2131 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */
2132 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */
2133 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* mem temp */
2134 #ifdef __APPLE__
2135 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R11); /* ??? */
2136 #endif
2137 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */
2138
2139 tcg_add_target_add_op_defs(ppc_op_defs);
2140 }
2141
2142 typedef struct {
2143 DebugFrameCIE cie;
2144 DebugFrameFDEHeader fde;
2145 uint8_t fde_def_cfa[4];
2146 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2 + 3];
2147 } DebugFrame;
2148
2149 /* We're expecting a 2 byte uleb128 encoded value. */
2150 QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
2151
2152 #define ELF_HOST_MACHINE EM_PPC64
2153
2154 static DebugFrame debug_frame = {
2155 .cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
2156 .cie.id = -1,
2157 .cie.version = 1,
2158 .cie.code_align = 1,
2159 .cie.data_align = 0x78, /* sleb128 -8 */
2160 .cie.return_column = 65,
2161
2162 /* Total FDE size does not include the "len" member. */
2163 .fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, fde.cie_offset),
2164
2165 .fde_def_cfa = {
2166 12, 1, /* DW_CFA_def_cfa r1, ... */
2167 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2168 (FRAME_SIZE >> 7)
2169 },
2170 .fde_reg_ofs = {
2171 0x11, 65, 0x7e, /* DW_CFA_offset_extended_sf, lr, 16 */
2172 }
2173 };
2174
2175 void tcg_register_jit(void *buf, size_t buf_size)
2176 {
2177 uint8_t *p = &debug_frame.fde_reg_ofs[3];
2178 int i;
2179
2180 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i, p += 2) {
2181 p[0] = 0x80 + tcg_target_callee_save_regs[i];
2182 p[1] = (FRAME_SIZE - (REG_SAVE_BOT + i * 8)) / 8;
2183 }
2184
2185 debug_frame.fde.func_start = (tcg_target_long) buf;
2186 debug_frame.fde.func_len = buf_size;
2187
2188 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
2189 }