tcg-ppc64: Adjust tcg_out_call for ELFv2
[qemu.git] / tcg / ppc64 / tcg-target.c
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "tcg-be-ldst.h"
26
27 /* Shorthand for size of a pointer. Avoid promotion to unsigned. */
28 #define SZP ((int)sizeof(void *))
29
30 /* Shorthand for size of a register. */
31 #define SZR (TCG_TARGET_REG_BITS / 8)
32
33 #define TCG_CT_CONST_S16 0x100
34 #define TCG_CT_CONST_U16 0x200
35 #define TCG_CT_CONST_S32 0x400
36 #define TCG_CT_CONST_U32 0x800
37 #define TCG_CT_CONST_ZERO 0x1000
38 #define TCG_CT_CONST_MONE 0x2000
39
40 static tcg_insn_unit *tb_ret_addr;
41
42 #ifndef GUEST_BASE
43 #define GUEST_BASE 0
44 #endif
45
46 #include "elf.h"
47 static bool have_isa_2_06;
48 #define HAVE_ISA_2_06 have_isa_2_06
49 #define HAVE_ISEL have_isa_2_06
50
51 #ifdef CONFIG_USE_GUEST_BASE
52 #define TCG_GUEST_BASE_REG 30
53 #else
54 #define TCG_GUEST_BASE_REG 0
55 #endif
56
57 #ifndef NDEBUG
58 static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
59 "r0",
60 "r1",
61 "r2",
62 "r3",
63 "r4",
64 "r5",
65 "r6",
66 "r7",
67 "r8",
68 "r9",
69 "r10",
70 "r11",
71 "r12",
72 "r13",
73 "r14",
74 "r15",
75 "r16",
76 "r17",
77 "r18",
78 "r19",
79 "r20",
80 "r21",
81 "r22",
82 "r23",
83 "r24",
84 "r25",
85 "r26",
86 "r27",
87 "r28",
88 "r29",
89 "r30",
90 "r31"
91 };
92 #endif
93
94 static const int tcg_target_reg_alloc_order[] = {
95 TCG_REG_R14, /* call saved registers */
96 TCG_REG_R15,
97 TCG_REG_R16,
98 TCG_REG_R17,
99 TCG_REG_R18,
100 TCG_REG_R19,
101 TCG_REG_R20,
102 TCG_REG_R21,
103 TCG_REG_R22,
104 TCG_REG_R23,
105 TCG_REG_R24,
106 TCG_REG_R25,
107 TCG_REG_R26,
108 TCG_REG_R27,
109 TCG_REG_R28,
110 TCG_REG_R29,
111 TCG_REG_R30,
112 TCG_REG_R31,
113 TCG_REG_R12, /* call clobbered, non-arguments */
114 TCG_REG_R11,
115 TCG_REG_R10, /* call clobbered, arguments */
116 TCG_REG_R9,
117 TCG_REG_R8,
118 TCG_REG_R7,
119 TCG_REG_R6,
120 TCG_REG_R5,
121 TCG_REG_R4,
122 TCG_REG_R3,
123 };
124
125 static const int tcg_target_call_iarg_regs[] = {
126 TCG_REG_R3,
127 TCG_REG_R4,
128 TCG_REG_R5,
129 TCG_REG_R6,
130 TCG_REG_R7,
131 TCG_REG_R8,
132 TCG_REG_R9,
133 TCG_REG_R10
134 };
135
136 static const int tcg_target_call_oarg_regs[] = {
137 TCG_REG_R3
138 };
139
140 static const int tcg_target_callee_save_regs[] = {
141 #ifdef __APPLE__
142 TCG_REG_R11,
143 #endif
144 TCG_REG_R14,
145 TCG_REG_R15,
146 TCG_REG_R16,
147 TCG_REG_R17,
148 TCG_REG_R18,
149 TCG_REG_R19,
150 TCG_REG_R20,
151 TCG_REG_R21,
152 TCG_REG_R22,
153 TCG_REG_R23,
154 TCG_REG_R24,
155 TCG_REG_R25,
156 TCG_REG_R26,
157 TCG_REG_R27, /* currently used for the global env */
158 TCG_REG_R28,
159 TCG_REG_R29,
160 TCG_REG_R30,
161 TCG_REG_R31
162 };
163
164 static inline bool in_range_b(tcg_target_long target)
165 {
166 return target == sextract64(target, 0, 26);
167 }
168
169 static uint32_t reloc_pc24_val(tcg_insn_unit *pc, tcg_insn_unit *target)
170 {
171 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
172 assert(in_range_b(disp));
173 return disp & 0x3fffffc;
174 }
175
176 static void reloc_pc24(tcg_insn_unit *pc, tcg_insn_unit *target)
177 {
178 *pc = (*pc & ~0x3fffffc) | reloc_pc24_val(pc, target);
179 }
180
181 static uint16_t reloc_pc14_val(tcg_insn_unit *pc, tcg_insn_unit *target)
182 {
183 ptrdiff_t disp = tcg_ptr_byte_diff(target, pc);
184 assert(disp == (int16_t) disp);
185 return disp & 0xfffc;
186 }
187
188 static void reloc_pc14(tcg_insn_unit *pc, tcg_insn_unit *target)
189 {
190 *pc = (*pc & ~0xfffc) | reloc_pc14_val(pc, target);
191 }
192
193 static inline void tcg_out_b_noaddr(TCGContext *s, int insn)
194 {
195 unsigned retrans = *s->code_ptr & 0x3fffffc;
196 tcg_out32(s, insn | retrans);
197 }
198
199 static inline void tcg_out_bc_noaddr(TCGContext *s, int insn)
200 {
201 unsigned retrans = *s->code_ptr & 0xfffc;
202 tcg_out32(s, insn | retrans);
203 }
204
205 static void patch_reloc(tcg_insn_unit *code_ptr, int type,
206 intptr_t value, intptr_t addend)
207 {
208 tcg_insn_unit *target = (tcg_insn_unit *)value;
209
210 assert(addend == 0);
211 switch (type) {
212 case R_PPC_REL14:
213 reloc_pc14(code_ptr, target);
214 break;
215 case R_PPC_REL24:
216 reloc_pc24(code_ptr, target);
217 break;
218 default:
219 tcg_abort();
220 }
221 }
222
223 /* parse target specific constraints */
224 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
225 {
226 const char *ct_str;
227
228 ct_str = *pct_str;
229 switch (ct_str[0]) {
230 case 'A': case 'B': case 'C': case 'D':
231 ct->ct |= TCG_CT_REG;
232 tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A');
233 break;
234 case 'r':
235 ct->ct |= TCG_CT_REG;
236 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
237 break;
238 case 'L': /* qemu_ld constraint */
239 ct->ct |= TCG_CT_REG;
240 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
241 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
242 #ifdef CONFIG_SOFTMMU
243 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
244 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
245 #endif
246 break;
247 case 'S': /* qemu_st constraint */
248 ct->ct |= TCG_CT_REG;
249 tcg_regset_set32(ct->u.regs, 0, 0xffffffff);
250 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3);
251 #ifdef CONFIG_SOFTMMU
252 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4);
253 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5);
254 tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6);
255 #endif
256 break;
257 case 'I':
258 ct->ct |= TCG_CT_CONST_S16;
259 break;
260 case 'J':
261 ct->ct |= TCG_CT_CONST_U16;
262 break;
263 case 'M':
264 ct->ct |= TCG_CT_CONST_MONE;
265 break;
266 case 'T':
267 ct->ct |= TCG_CT_CONST_S32;
268 break;
269 case 'U':
270 ct->ct |= TCG_CT_CONST_U32;
271 break;
272 case 'Z':
273 ct->ct |= TCG_CT_CONST_ZERO;
274 break;
275 default:
276 return -1;
277 }
278 ct_str++;
279 *pct_str = ct_str;
280 return 0;
281 }
282
283 /* test if a constant matches the constraint */
284 static int tcg_target_const_match(tcg_target_long val, TCGType type,
285 const TCGArgConstraint *arg_ct)
286 {
287 int ct = arg_ct->ct;
288 if (ct & TCG_CT_CONST) {
289 return 1;
290 }
291
292 /* The only 32-bit constraint we use aside from
293 TCG_CT_CONST is TCG_CT_CONST_S16. */
294 if (type == TCG_TYPE_I32) {
295 val = (int32_t)val;
296 }
297
298 if ((ct & TCG_CT_CONST_S16) && val == (int16_t)val) {
299 return 1;
300 } else if ((ct & TCG_CT_CONST_U16) && val == (uint16_t)val) {
301 return 1;
302 } else if ((ct & TCG_CT_CONST_S32) && val == (int32_t)val) {
303 return 1;
304 } else if ((ct & TCG_CT_CONST_U32) && val == (uint32_t)val) {
305 return 1;
306 } else if ((ct & TCG_CT_CONST_ZERO) && val == 0) {
307 return 1;
308 } else if ((ct & TCG_CT_CONST_MONE) && val == -1) {
309 return 1;
310 }
311 return 0;
312 }
313
314 #define OPCD(opc) ((opc)<<26)
315 #define XO19(opc) (OPCD(19)|((opc)<<1))
316 #define MD30(opc) (OPCD(30)|((opc)<<2))
317 #define MDS30(opc) (OPCD(30)|((opc)<<1))
318 #define XO31(opc) (OPCD(31)|((opc)<<1))
319 #define XO58(opc) (OPCD(58)|(opc))
320 #define XO62(opc) (OPCD(62)|(opc))
321
322 #define B OPCD( 18)
323 #define BC OPCD( 16)
324 #define LBZ OPCD( 34)
325 #define LHZ OPCD( 40)
326 #define LHA OPCD( 42)
327 #define LWZ OPCD( 32)
328 #define STB OPCD( 38)
329 #define STH OPCD( 44)
330 #define STW OPCD( 36)
331
332 #define STD XO62( 0)
333 #define STDU XO62( 1)
334 #define STDX XO31(149)
335
336 #define LD XO58( 0)
337 #define LDX XO31( 21)
338 #define LDU XO58( 1)
339 #define LWA XO58( 2)
340 #define LWAX XO31(341)
341
342 #define ADDIC OPCD( 12)
343 #define ADDI OPCD( 14)
344 #define ADDIS OPCD( 15)
345 #define ORI OPCD( 24)
346 #define ORIS OPCD( 25)
347 #define XORI OPCD( 26)
348 #define XORIS OPCD( 27)
349 #define ANDI OPCD( 28)
350 #define ANDIS OPCD( 29)
351 #define MULLI OPCD( 7)
352 #define CMPLI OPCD( 10)
353 #define CMPI OPCD( 11)
354 #define SUBFIC OPCD( 8)
355
356 #define LWZU OPCD( 33)
357 #define STWU OPCD( 37)
358
359 #define RLWIMI OPCD( 20)
360 #define RLWINM OPCD( 21)
361 #define RLWNM OPCD( 23)
362
363 #define RLDICL MD30( 0)
364 #define RLDICR MD30( 1)
365 #define RLDIMI MD30( 3)
366 #define RLDCL MDS30( 8)
367
368 #define BCLR XO19( 16)
369 #define BCCTR XO19(528)
370 #define CRAND XO19(257)
371 #define CRANDC XO19(129)
372 #define CRNAND XO19(225)
373 #define CROR XO19(449)
374 #define CRNOR XO19( 33)
375
376 #define EXTSB XO31(954)
377 #define EXTSH XO31(922)
378 #define EXTSW XO31(986)
379 #define ADD XO31(266)
380 #define ADDE XO31(138)
381 #define ADDME XO31(234)
382 #define ADDZE XO31(202)
383 #define ADDC XO31( 10)
384 #define AND XO31( 28)
385 #define SUBF XO31( 40)
386 #define SUBFC XO31( 8)
387 #define SUBFE XO31(136)
388 #define SUBFME XO31(232)
389 #define SUBFZE XO31(200)
390 #define OR XO31(444)
391 #define XOR XO31(316)
392 #define MULLW XO31(235)
393 #define MULHWU XO31( 11)
394 #define DIVW XO31(491)
395 #define DIVWU XO31(459)
396 #define CMP XO31( 0)
397 #define CMPL XO31( 32)
398 #define LHBRX XO31(790)
399 #define LWBRX XO31(534)
400 #define LDBRX XO31(532)
401 #define STHBRX XO31(918)
402 #define STWBRX XO31(662)
403 #define STDBRX XO31(660)
404 #define MFSPR XO31(339)
405 #define MTSPR XO31(467)
406 #define SRAWI XO31(824)
407 #define NEG XO31(104)
408 #define MFCR XO31( 19)
409 #define MFOCRF (MFCR | (1u << 20))
410 #define NOR XO31(124)
411 #define CNTLZW XO31( 26)
412 #define CNTLZD XO31( 58)
413 #define ANDC XO31( 60)
414 #define ORC XO31(412)
415 #define EQV XO31(284)
416 #define NAND XO31(476)
417 #define ISEL XO31( 15)
418
419 #define MULLD XO31(233)
420 #define MULHD XO31( 73)
421 #define MULHDU XO31( 9)
422 #define DIVD XO31(489)
423 #define DIVDU XO31(457)
424
425 #define LBZX XO31( 87)
426 #define LHZX XO31(279)
427 #define LHAX XO31(343)
428 #define LWZX XO31( 23)
429 #define STBX XO31(215)
430 #define STHX XO31(407)
431 #define STWX XO31(151)
432
433 #define SPR(a, b) ((((a)<<5)|(b))<<11)
434 #define LR SPR(8, 0)
435 #define CTR SPR(9, 0)
436
437 #define SLW XO31( 24)
438 #define SRW XO31(536)
439 #define SRAW XO31(792)
440
441 #define SLD XO31( 27)
442 #define SRD XO31(539)
443 #define SRAD XO31(794)
444 #define SRADI XO31(413<<1)
445
446 #define TW XO31( 4)
447 #define TRAP (TW | TO(31))
448
449 #define RT(r) ((r)<<21)
450 #define RS(r) ((r)<<21)
451 #define RA(r) ((r)<<16)
452 #define RB(r) ((r)<<11)
453 #define TO(t) ((t)<<21)
454 #define SH(s) ((s)<<11)
455 #define MB(b) ((b)<<6)
456 #define ME(e) ((e)<<1)
457 #define BO(o) ((o)<<21)
458 #define MB64(b) ((b)<<5)
459 #define FXM(b) (1 << (19 - (b)))
460
461 #define LK 1
462
463 #define TAB(t, a, b) (RT(t) | RA(a) | RB(b))
464 #define SAB(s, a, b) (RS(s) | RA(a) | RB(b))
465 #define TAI(s, a, i) (RT(s) | RA(a) | ((i) & 0xffff))
466 #define SAI(s, a, i) (RS(s) | RA(a) | ((i) & 0xffff))
467
468 #define BF(n) ((n)<<23)
469 #define BI(n, c) (((c)+((n)*4))<<16)
470 #define BT(n, c) (((c)+((n)*4))<<21)
471 #define BA(n, c) (((c)+((n)*4))<<16)
472 #define BB(n, c) (((c)+((n)*4))<<11)
473 #define BC_(n, c) (((c)+((n)*4))<<6)
474
475 #define BO_COND_TRUE BO(12)
476 #define BO_COND_FALSE BO( 4)
477 #define BO_ALWAYS BO(20)
478
479 enum {
480 CR_LT,
481 CR_GT,
482 CR_EQ,
483 CR_SO
484 };
485
486 static const uint32_t tcg_to_bc[] = {
487 [TCG_COND_EQ] = BC | BI(7, CR_EQ) | BO_COND_TRUE,
488 [TCG_COND_NE] = BC | BI(7, CR_EQ) | BO_COND_FALSE,
489 [TCG_COND_LT] = BC | BI(7, CR_LT) | BO_COND_TRUE,
490 [TCG_COND_GE] = BC | BI(7, CR_LT) | BO_COND_FALSE,
491 [TCG_COND_LE] = BC | BI(7, CR_GT) | BO_COND_FALSE,
492 [TCG_COND_GT] = BC | BI(7, CR_GT) | BO_COND_TRUE,
493 [TCG_COND_LTU] = BC | BI(7, CR_LT) | BO_COND_TRUE,
494 [TCG_COND_GEU] = BC | BI(7, CR_LT) | BO_COND_FALSE,
495 [TCG_COND_LEU] = BC | BI(7, CR_GT) | BO_COND_FALSE,
496 [TCG_COND_GTU] = BC | BI(7, CR_GT) | BO_COND_TRUE,
497 };
498
499 /* The low bit here is set if the RA and RB fields must be inverted. */
500 static const uint32_t tcg_to_isel[] = {
501 [TCG_COND_EQ] = ISEL | BC_(7, CR_EQ),
502 [TCG_COND_NE] = ISEL | BC_(7, CR_EQ) | 1,
503 [TCG_COND_LT] = ISEL | BC_(7, CR_LT),
504 [TCG_COND_GE] = ISEL | BC_(7, CR_LT) | 1,
505 [TCG_COND_LE] = ISEL | BC_(7, CR_GT) | 1,
506 [TCG_COND_GT] = ISEL | BC_(7, CR_GT),
507 [TCG_COND_LTU] = ISEL | BC_(7, CR_LT),
508 [TCG_COND_GEU] = ISEL | BC_(7, CR_LT) | 1,
509 [TCG_COND_LEU] = ISEL | BC_(7, CR_GT) | 1,
510 [TCG_COND_GTU] = ISEL | BC_(7, CR_GT),
511 };
512
513 static inline void tcg_out_mov(TCGContext *s, TCGType type,
514 TCGReg ret, TCGReg arg)
515 {
516 if (ret != arg) {
517 tcg_out32(s, OR | SAB(arg, ret, arg));
518 }
519 }
520
521 static inline void tcg_out_rld(TCGContext *s, int op, TCGReg ra, TCGReg rs,
522 int sh, int mb)
523 {
524 sh = SH(sh & 0x1f) | (((sh >> 5) & 1) << 1);
525 mb = MB64((mb >> 5) | ((mb << 1) & 0x3f));
526 tcg_out32(s, op | RA(ra) | RS(rs) | sh | mb);
527 }
528
529 static inline void tcg_out_rlw(TCGContext *s, int op, TCGReg ra, TCGReg rs,
530 int sh, int mb, int me)
531 {
532 tcg_out32(s, op | RA(ra) | RS(rs) | SH(sh) | MB(mb) | ME(me));
533 }
534
535 static inline void tcg_out_ext32u(TCGContext *s, TCGReg dst, TCGReg src)
536 {
537 tcg_out_rld(s, RLDICL, dst, src, 0, 32);
538 }
539
540 static inline void tcg_out_shli64(TCGContext *s, TCGReg dst, TCGReg src, int c)
541 {
542 tcg_out_rld(s, RLDICR, dst, src, c, 63 - c);
543 }
544
545 static inline void tcg_out_shri64(TCGContext *s, TCGReg dst, TCGReg src, int c)
546 {
547 tcg_out_rld(s, RLDICL, dst, src, 64 - c, c);
548 }
549
550 static void tcg_out_movi32(TCGContext *s, TCGReg ret, int32_t arg)
551 {
552 if (arg == (int16_t) arg) {
553 tcg_out32(s, ADDI | TAI(ret, 0, arg));
554 } else {
555 tcg_out32(s, ADDIS | TAI(ret, 0, arg >> 16));
556 if (arg & 0xffff) {
557 tcg_out32(s, ORI | SAI(ret, ret, arg));
558 }
559 }
560 }
561
562 static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg ret,
563 tcg_target_long arg)
564 {
565 if (type == TCG_TYPE_I32 || arg == (int32_t)arg) {
566 tcg_out_movi32(s, ret, arg);
567 } else if (arg == (uint32_t)arg && !(arg & 0x8000)) {
568 tcg_out32(s, ADDI | TAI(ret, 0, arg));
569 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
570 } else {
571 int32_t high = arg >> 32;
572 tcg_out_movi32(s, ret, high);
573 if (high) {
574 tcg_out_shli64(s, ret, ret, 32);
575 }
576 if (arg & 0xffff0000) {
577 tcg_out32(s, ORIS | SAI(ret, ret, arg >> 16));
578 }
579 if (arg & 0xffff) {
580 tcg_out32(s, ORI | SAI(ret, ret, arg));
581 }
582 }
583 }
584
585 static bool mask_operand(uint32_t c, int *mb, int *me)
586 {
587 uint32_t lsb, test;
588
589 /* Accept a bit pattern like:
590 0....01....1
591 1....10....0
592 0..01..10..0
593 Keep track of the transitions. */
594 if (c == 0 || c == -1) {
595 return false;
596 }
597 test = c;
598 lsb = test & -test;
599 test += lsb;
600 if (test & (test - 1)) {
601 return false;
602 }
603
604 *me = clz32(lsb);
605 *mb = test ? clz32(test & -test) + 1 : 0;
606 return true;
607 }
608
609 static bool mask64_operand(uint64_t c, int *mb, int *me)
610 {
611 uint64_t lsb;
612
613 if (c == 0) {
614 return false;
615 }
616
617 lsb = c & -c;
618 /* Accept 1..10..0. */
619 if (c == -lsb) {
620 *mb = 0;
621 *me = clz64(lsb);
622 return true;
623 }
624 /* Accept 0..01..1. */
625 if (lsb == 1 && (c & (c + 1)) == 0) {
626 *mb = clz64(c + 1) + 1;
627 *me = 63;
628 return true;
629 }
630 return false;
631 }
632
633 static void tcg_out_andi32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
634 {
635 int mb, me;
636
637 if ((c & 0xffff) == c) {
638 tcg_out32(s, ANDI | SAI(src, dst, c));
639 return;
640 } else if ((c & 0xffff0000) == c) {
641 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
642 return;
643 } else if (mask_operand(c, &mb, &me)) {
644 tcg_out_rlw(s, RLWINM, dst, src, 0, mb, me);
645 } else {
646 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R0, c);
647 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
648 }
649 }
650
651 static void tcg_out_andi64(TCGContext *s, TCGReg dst, TCGReg src, uint64_t c)
652 {
653 int mb, me;
654
655 if ((c & 0xffff) == c) {
656 tcg_out32(s, ANDI | SAI(src, dst, c));
657 return;
658 } else if ((c & 0xffff0000) == c) {
659 tcg_out32(s, ANDIS | SAI(src, dst, c >> 16));
660 return;
661 } else if (mask64_operand(c, &mb, &me)) {
662 if (mb == 0) {
663 tcg_out_rld(s, RLDICR, dst, src, 0, me);
664 } else {
665 tcg_out_rld(s, RLDICL, dst, src, 0, mb);
666 }
667 } else {
668 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, c);
669 tcg_out32(s, AND | SAB(src, dst, TCG_REG_R0));
670 }
671 }
672
673 static void tcg_out_zori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c,
674 int op_lo, int op_hi)
675 {
676 if (c >> 16) {
677 tcg_out32(s, op_hi | SAI(src, dst, c >> 16));
678 src = dst;
679 }
680 if (c & 0xffff) {
681 tcg_out32(s, op_lo | SAI(src, dst, c));
682 src = dst;
683 }
684 }
685
686 static void tcg_out_ori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
687 {
688 tcg_out_zori32(s, dst, src, c, ORI, ORIS);
689 }
690
691 static void tcg_out_xori32(TCGContext *s, TCGReg dst, TCGReg src, uint32_t c)
692 {
693 tcg_out_zori32(s, dst, src, c, XORI, XORIS);
694 }
695
696 static void tcg_out_b(TCGContext *s, int mask, tcg_insn_unit *target)
697 {
698 ptrdiff_t disp = tcg_pcrel_diff(s, target);
699 if (in_range_b(disp)) {
700 tcg_out32(s, B | (disp & 0x3fffffc) | mask);
701 } else {
702 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R0, (uintptr_t)target);
703 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | CTR);
704 tcg_out32(s, BCCTR | BO_ALWAYS | mask);
705 }
706 }
707
708 static void tcg_out_mem_long(TCGContext *s, int opi, int opx, TCGReg rt,
709 TCGReg base, tcg_target_long offset)
710 {
711 tcg_target_long orig = offset, l0, l1, extra = 0, align = 0;
712 bool is_store = false;
713 TCGReg rs = TCG_REG_R2;
714
715 switch (opi) {
716 case LD: case LWA:
717 align = 3;
718 /* FALLTHRU */
719 default:
720 if (rt != TCG_REG_R0) {
721 rs = rt;
722 break;
723 }
724 break;
725 case STD:
726 align = 3;
727 /* FALLTHRU */
728 case STB: case STH: case STW:
729 is_store = true;
730 break;
731 }
732
733 /* For unaligned, or very large offsets, use the indexed form. */
734 if (offset & align || offset != (int32_t)offset) {
735 tcg_debug_assert(rs != base && (!is_store || rs != rt));
736 tcg_out_movi(s, TCG_TYPE_PTR, rs, orig);
737 tcg_out32(s, opx | TAB(rt, base, rs));
738 return;
739 }
740
741 l0 = (int16_t)offset;
742 offset = (offset - l0) >> 16;
743 l1 = (int16_t)offset;
744
745 if (l1 < 0 && orig >= 0) {
746 extra = 0x4000;
747 l1 = (int16_t)(offset - 0x4000);
748 }
749 if (l1) {
750 tcg_out32(s, ADDIS | TAI(rs, base, l1));
751 base = rs;
752 }
753 if (extra) {
754 tcg_out32(s, ADDIS | TAI(rs, base, extra));
755 base = rs;
756 }
757 if (opi != ADDI || base != rt || l0 != 0) {
758 tcg_out32(s, opi | TAI(rt, base, l0));
759 }
760 }
761
762 static inline void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret,
763 TCGReg arg1, intptr_t arg2)
764 {
765 int opi, opx;
766
767 if (type == TCG_TYPE_I32) {
768 opi = LWZ, opx = LWZX;
769 } else {
770 opi = LD, opx = LDX;
771 }
772 tcg_out_mem_long(s, opi, opx, ret, arg1, arg2);
773 }
774
775 static inline void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg,
776 TCGReg arg1, intptr_t arg2)
777 {
778 int opi, opx;
779
780 if (type == TCG_TYPE_I32) {
781 opi = STW, opx = STWX;
782 } else {
783 opi = STD, opx = STDX;
784 }
785 tcg_out_mem_long(s, opi, opx, arg, arg1, arg2);
786 }
787
788 static void tcg_out_cmp(TCGContext *s, int cond, TCGArg arg1, TCGArg arg2,
789 int const_arg2, int cr, TCGType type)
790 {
791 int imm;
792 uint32_t op;
793
794 /* Simplify the comparisons below wrt CMPI. */
795 if (type == TCG_TYPE_I32) {
796 arg2 = (int32_t)arg2;
797 }
798
799 switch (cond) {
800 case TCG_COND_EQ:
801 case TCG_COND_NE:
802 if (const_arg2) {
803 if ((int16_t) arg2 == arg2) {
804 op = CMPI;
805 imm = 1;
806 break;
807 } else if ((uint16_t) arg2 == arg2) {
808 op = CMPLI;
809 imm = 1;
810 break;
811 }
812 }
813 op = CMPL;
814 imm = 0;
815 break;
816
817 case TCG_COND_LT:
818 case TCG_COND_GE:
819 case TCG_COND_LE:
820 case TCG_COND_GT:
821 if (const_arg2) {
822 if ((int16_t) arg2 == arg2) {
823 op = CMPI;
824 imm = 1;
825 break;
826 }
827 }
828 op = CMP;
829 imm = 0;
830 break;
831
832 case TCG_COND_LTU:
833 case TCG_COND_GEU:
834 case TCG_COND_LEU:
835 case TCG_COND_GTU:
836 if (const_arg2) {
837 if ((uint16_t) arg2 == arg2) {
838 op = CMPLI;
839 imm = 1;
840 break;
841 }
842 }
843 op = CMPL;
844 imm = 0;
845 break;
846
847 default:
848 tcg_abort();
849 }
850 op |= BF(cr) | ((type == TCG_TYPE_I64) << 21);
851
852 if (imm) {
853 tcg_out32(s, op | RA(arg1) | (arg2 & 0xffff));
854 } else {
855 if (const_arg2) {
856 tcg_out_movi(s, type, TCG_REG_R0, arg2);
857 arg2 = TCG_REG_R0;
858 }
859 tcg_out32(s, op | RA(arg1) | RB(arg2));
860 }
861 }
862
863 static void tcg_out_setcond_eq0(TCGContext *s, TCGType type,
864 TCGReg dst, TCGReg src)
865 {
866 tcg_out32(s, (type == TCG_TYPE_I64 ? CNTLZD : CNTLZW) | RS(src) | RA(dst));
867 tcg_out_shri64(s, dst, dst, type == TCG_TYPE_I64 ? 6 : 5);
868 }
869
870 static void tcg_out_setcond_ne0(TCGContext *s, TCGReg dst, TCGReg src)
871 {
872 /* X != 0 implies X + -1 generates a carry. Extra addition
873 trickery means: R = X-1 + ~X + C = X-1 + (-X+1) + C = C. */
874 if (dst != src) {
875 tcg_out32(s, ADDIC | TAI(dst, src, -1));
876 tcg_out32(s, SUBFE | TAB(dst, dst, src));
877 } else {
878 tcg_out32(s, ADDIC | TAI(TCG_REG_R0, src, -1));
879 tcg_out32(s, SUBFE | TAB(dst, TCG_REG_R0, src));
880 }
881 }
882
883 static TCGReg tcg_gen_setcond_xor(TCGContext *s, TCGReg arg1, TCGArg arg2,
884 bool const_arg2)
885 {
886 if (const_arg2) {
887 if ((uint32_t)arg2 == arg2) {
888 tcg_out_xori32(s, TCG_REG_R0, arg1, arg2);
889 } else {
890 tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_R0, arg2);
891 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, TCG_REG_R0));
892 }
893 } else {
894 tcg_out32(s, XOR | SAB(arg1, TCG_REG_R0, arg2));
895 }
896 return TCG_REG_R0;
897 }
898
899 static void tcg_out_setcond(TCGContext *s, TCGType type, TCGCond cond,
900 TCGArg arg0, TCGArg arg1, TCGArg arg2,
901 int const_arg2)
902 {
903 int crop, sh;
904
905 /* Ignore high bits of a potential constant arg2. */
906 if (type == TCG_TYPE_I32) {
907 arg2 = (uint32_t)arg2;
908 }
909
910 /* Handle common and trivial cases before handling anything else. */
911 if (arg2 == 0) {
912 switch (cond) {
913 case TCG_COND_EQ:
914 tcg_out_setcond_eq0(s, type, arg0, arg1);
915 return;
916 case TCG_COND_NE:
917 if (type == TCG_TYPE_I32) {
918 tcg_out_ext32u(s, TCG_REG_R0, arg1);
919 arg1 = TCG_REG_R0;
920 }
921 tcg_out_setcond_ne0(s, arg0, arg1);
922 return;
923 case TCG_COND_GE:
924 tcg_out32(s, NOR | SAB(arg1, arg0, arg1));
925 arg1 = arg0;
926 /* FALLTHRU */
927 case TCG_COND_LT:
928 /* Extract the sign bit. */
929 tcg_out_rld(s, RLDICL, arg0, arg1,
930 type == TCG_TYPE_I64 ? 1 : 33, 63);
931 return;
932 default:
933 break;
934 }
935 }
936
937 /* If we have ISEL, we can implement everything with 3 or 4 insns.
938 All other cases below are also at least 3 insns, so speed up the
939 code generator by not considering them and always using ISEL. */
940 if (HAVE_ISEL) {
941 int isel, tab;
942
943 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
944
945 isel = tcg_to_isel[cond];
946
947 tcg_out_movi(s, type, arg0, 1);
948 if (isel & 1) {
949 /* arg0 = (bc ? 0 : 1) */
950 tab = TAB(arg0, 0, arg0);
951 isel &= ~1;
952 } else {
953 /* arg0 = (bc ? 1 : 0) */
954 tcg_out_movi(s, type, TCG_REG_R0, 0);
955 tab = TAB(arg0, arg0, TCG_REG_R0);
956 }
957 tcg_out32(s, isel | tab);
958 return;
959 }
960
961 switch (cond) {
962 case TCG_COND_EQ:
963 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
964 tcg_out_setcond_eq0(s, type, arg0, arg1);
965 return;
966
967 case TCG_COND_NE:
968 arg1 = tcg_gen_setcond_xor(s, arg1, arg2, const_arg2);
969 /* Discard the high bits only once, rather than both inputs. */
970 if (type == TCG_TYPE_I32) {
971 tcg_out_ext32u(s, TCG_REG_R0, arg1);
972 arg1 = TCG_REG_R0;
973 }
974 tcg_out_setcond_ne0(s, arg0, arg1);
975 return;
976
977 case TCG_COND_GT:
978 case TCG_COND_GTU:
979 sh = 30;
980 crop = 0;
981 goto crtest;
982
983 case TCG_COND_LT:
984 case TCG_COND_LTU:
985 sh = 29;
986 crop = 0;
987 goto crtest;
988
989 case TCG_COND_GE:
990 case TCG_COND_GEU:
991 sh = 31;
992 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_LT) | BB(7, CR_LT);
993 goto crtest;
994
995 case TCG_COND_LE:
996 case TCG_COND_LEU:
997 sh = 31;
998 crop = CRNOR | BT(7, CR_EQ) | BA(7, CR_GT) | BB(7, CR_GT);
999 crtest:
1000 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1001 if (crop) {
1002 tcg_out32(s, crop);
1003 }
1004 tcg_out32(s, MFOCRF | RT(TCG_REG_R0) | FXM(7));
1005 tcg_out_rlw(s, RLWINM, arg0, TCG_REG_R0, sh, 31, 31);
1006 break;
1007
1008 default:
1009 tcg_abort();
1010 }
1011 }
1012
1013 static void tcg_out_bc(TCGContext *s, int bc, int label_index)
1014 {
1015 TCGLabel *l = &s->labels[label_index];
1016
1017 if (l->has_value) {
1018 tcg_out32(s, bc | reloc_pc14_val(s->code_ptr, l->u.value_ptr));
1019 } else {
1020 tcg_out_reloc(s, s->code_ptr, R_PPC_REL14, label_index, 0);
1021 tcg_out_bc_noaddr(s, bc);
1022 }
1023 }
1024
1025 static void tcg_out_brcond(TCGContext *s, TCGCond cond,
1026 TCGArg arg1, TCGArg arg2, int const_arg2,
1027 int label_index, TCGType type)
1028 {
1029 tcg_out_cmp(s, cond, arg1, arg2, const_arg2, 7, type);
1030 tcg_out_bc(s, tcg_to_bc[cond], label_index);
1031 }
1032
1033 static void tcg_out_movcond(TCGContext *s, TCGType type, TCGCond cond,
1034 TCGArg dest, TCGArg c1, TCGArg c2, TCGArg v1,
1035 TCGArg v2, bool const_c2)
1036 {
1037 /* If for some reason both inputs are zero, don't produce bad code. */
1038 if (v1 == 0 && v2 == 0) {
1039 tcg_out_movi(s, type, dest, 0);
1040 return;
1041 }
1042
1043 tcg_out_cmp(s, cond, c1, c2, const_c2, 7, type);
1044
1045 if (HAVE_ISEL) {
1046 int isel = tcg_to_isel[cond];
1047
1048 /* Swap the V operands if the operation indicates inversion. */
1049 if (isel & 1) {
1050 int t = v1;
1051 v1 = v2;
1052 v2 = t;
1053 isel &= ~1;
1054 }
1055 /* V1 == 0 is handled by isel; V2 == 0 must be handled by hand. */
1056 if (v2 == 0) {
1057 tcg_out_movi(s, type, TCG_REG_R0, 0);
1058 }
1059 tcg_out32(s, isel | TAB(dest, v1, v2));
1060 } else {
1061 if (dest == v2) {
1062 cond = tcg_invert_cond(cond);
1063 v2 = v1;
1064 } else if (dest != v1) {
1065 if (v1 == 0) {
1066 tcg_out_movi(s, type, dest, 0);
1067 } else {
1068 tcg_out_mov(s, type, dest, v1);
1069 }
1070 }
1071 /* Branch forward over one insn */
1072 tcg_out32(s, tcg_to_bc[cond] | 8);
1073 if (v2 == 0) {
1074 tcg_out_movi(s, type, dest, 0);
1075 } else {
1076 tcg_out_mov(s, type, dest, v2);
1077 }
1078 }
1079 }
1080
1081 void ppc_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr)
1082 {
1083 TCGContext s;
1084
1085 s.code_buf = s.code_ptr = (tcg_insn_unit *)jmp_addr;
1086 tcg_out_b(&s, 0, (tcg_insn_unit *)addr);
1087 flush_icache_range(jmp_addr, jmp_addr + tcg_current_code_size(&s));
1088 }
1089
1090 static void tcg_out_call(TCGContext *s, tcg_insn_unit *target)
1091 {
1092 #ifdef _CALL_AIX
1093 /* Look through the descriptor. If the branch is in range, and we
1094 don't have to spend too much effort on building the toc. */
1095 void *tgt = ((void **)target)[0];
1096 uintptr_t toc = ((uintptr_t *)target)[1];
1097 intptr_t diff = tcg_pcrel_diff(s, tgt);
1098
1099 if (in_range_b(diff) && toc == (uint32_t)toc) {
1100 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, toc);
1101 tcg_out_b(s, LK, tgt);
1102 } else {
1103 /* Fold the low bits of the constant into the addresses below. */
1104 intptr_t arg = (intptr_t)target;
1105 int ofs = (int16_t)arg;
1106
1107 if (ofs + 8 < 0x8000) {
1108 arg -= ofs;
1109 } else {
1110 ofs = 0;
1111 }
1112 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R2, arg);
1113 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R2, ofs);
1114 tcg_out32(s, MTSPR | RA(TCG_REG_R0) | CTR);
1115 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R2, TCG_REG_R2, ofs + SZP);
1116 tcg_out32(s, BCCTR | BO_ALWAYS | LK);
1117 }
1118 #elif defined(_CALL_ELF) && _CALL_ELF == 2
1119 intptr_t diff;
1120
1121 /* In the ELFv2 ABI, we have to set up r12 to contain the destination
1122 address, which the callee uses to compute its TOC address. */
1123 /* FIXME: when the branch is in range, we could avoid r12 load if we
1124 knew that the destination uses the same TOC, and what its local
1125 entry point offset is. */
1126 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R12, (intptr_t)target);
1127
1128 diff = tcg_pcrel_diff(s, target);
1129 if (in_range_b(diff)) {
1130 tcg_out_b(s, LK, target);
1131 } else {
1132 tcg_out32(s, MTSPR | RS(TCG_REG_R12) | CTR);
1133 tcg_out32(s, BCCTR | BO_ALWAYS | LK);
1134 }
1135 #else
1136 tcg_out_b(s, LK, target);
1137 #endif
1138 }
1139
1140 static const uint32_t qemu_ldx_opc[16] = {
1141 [MO_UB] = LBZX,
1142 [MO_UW] = LHZX,
1143 [MO_UL] = LWZX,
1144 [MO_Q] = LDX,
1145 [MO_SW] = LHAX,
1146 [MO_SL] = LWAX,
1147 [MO_BSWAP | MO_UB] = LBZX,
1148 [MO_BSWAP | MO_UW] = LHBRX,
1149 [MO_BSWAP | MO_UL] = LWBRX,
1150 [MO_BSWAP | MO_Q] = LDBRX,
1151 };
1152
1153 static const uint32_t qemu_stx_opc[16] = {
1154 [MO_UB] = STBX,
1155 [MO_UW] = STHX,
1156 [MO_UL] = STWX,
1157 [MO_Q] = STDX,
1158 [MO_BSWAP | MO_UB] = STBX,
1159 [MO_BSWAP | MO_UW] = STHBRX,
1160 [MO_BSWAP | MO_UL] = STWBRX,
1161 [MO_BSWAP | MO_Q] = STDBRX,
1162 };
1163
1164 static const uint32_t qemu_exts_opc[4] = {
1165 EXTSB, EXTSH, EXTSW, 0
1166 };
1167
1168 #if defined (CONFIG_SOFTMMU)
1169 /* helper signature: helper_ld_mmu(CPUState *env, target_ulong addr,
1170 * int mmu_idx, uintptr_t ra)
1171 */
1172 static void * const qemu_ld_helpers[16] = {
1173 [MO_UB] = helper_ret_ldub_mmu,
1174 [MO_LEUW] = helper_le_lduw_mmu,
1175 [MO_LEUL] = helper_le_ldul_mmu,
1176 [MO_LEQ] = helper_le_ldq_mmu,
1177 [MO_BEUW] = helper_be_lduw_mmu,
1178 [MO_BEUL] = helper_be_ldul_mmu,
1179 [MO_BEQ] = helper_be_ldq_mmu,
1180 };
1181
1182 /* helper signature: helper_st_mmu(CPUState *env, target_ulong addr,
1183 * uintxx_t val, int mmu_idx, uintptr_t ra)
1184 */
1185 static void * const qemu_st_helpers[16] = {
1186 [MO_UB] = helper_ret_stb_mmu,
1187 [MO_LEUW] = helper_le_stw_mmu,
1188 [MO_LEUL] = helper_le_stl_mmu,
1189 [MO_LEQ] = helper_le_stq_mmu,
1190 [MO_BEUW] = helper_be_stw_mmu,
1191 [MO_BEUL] = helper_be_stl_mmu,
1192 [MO_BEQ] = helper_be_stq_mmu,
1193 };
1194
1195 /* Perform the TLB load and compare. Places the result of the comparison
1196 in CR7, loads the addend of the TLB into R3, and returns the register
1197 containing the guest address (zero-extended into R4). Clobbers R0 and R2. */
1198
1199 static TCGReg tcg_out_tlb_read(TCGContext *s, TCGMemOp s_bits, TCGReg addr_reg,
1200 int mem_index, bool is_read)
1201 {
1202 int cmp_off
1203 = (is_read
1204 ? offsetof(CPUArchState, tlb_table[mem_index][0].addr_read)
1205 : offsetof(CPUArchState, tlb_table[mem_index][0].addr_write));
1206 int add_off = offsetof(CPUArchState, tlb_table[mem_index][0].addend);
1207 TCGReg base = TCG_AREG0;
1208
1209 /* Extract the page index, shifted into place for tlb index. */
1210 if (TARGET_LONG_BITS == 32) {
1211 /* Zero-extend the address into a place helpful for further use. */
1212 tcg_out_ext32u(s, TCG_REG_R4, addr_reg);
1213 addr_reg = TCG_REG_R4;
1214 } else {
1215 tcg_out_rld(s, RLDICL, TCG_REG_R3, addr_reg,
1216 64 - TARGET_PAGE_BITS, 64 - CPU_TLB_BITS);
1217 }
1218
1219 /* Compensate for very large offsets. */
1220 if (add_off >= 0x8000) {
1221 /* Most target env are smaller than 32k; none are larger than 64k.
1222 Simplify the logic here merely to offset by 0x7ff0, giving us a
1223 range just shy of 64k. Check this assumption. */
1224 QEMU_BUILD_BUG_ON(offsetof(CPUArchState,
1225 tlb_table[NB_MMU_MODES - 1][1])
1226 > 0x7ff0 + 0x7fff);
1227 tcg_out32(s, ADDI | TAI(TCG_REG_R2, base, 0x7ff0));
1228 base = TCG_REG_R2;
1229 cmp_off -= 0x7ff0;
1230 add_off -= 0x7ff0;
1231 }
1232
1233 /* Extraction and shifting, part 2. */
1234 if (TARGET_LONG_BITS == 32) {
1235 tcg_out_rlw(s, RLWINM, TCG_REG_R3, addr_reg,
1236 32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS),
1237 32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS),
1238 31 - CPU_TLB_ENTRY_BITS);
1239 } else {
1240 tcg_out_shli64(s, TCG_REG_R3, TCG_REG_R3, CPU_TLB_ENTRY_BITS);
1241 }
1242
1243 tcg_out32(s, ADD | TAB(TCG_REG_R3, TCG_REG_R3, base));
1244
1245 /* Load the tlb comparator. */
1246 tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_R2, TCG_REG_R3, cmp_off);
1247
1248 /* Load the TLB addend for use on the fast path. Do this asap
1249 to minimize any load use delay. */
1250 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_REG_R3, add_off);
1251
1252 /* Clear the non-page, non-alignment bits from the address. */
1253 if (TARGET_LONG_BITS == 32) {
1254 tcg_out_rlw(s, RLWINM, TCG_REG_R0, addr_reg, 0,
1255 (32 - s_bits) & 31, 31 - TARGET_PAGE_BITS);
1256 } else if (!s_bits) {
1257 tcg_out_rld(s, RLDICR, TCG_REG_R0, addr_reg, 0, 63 - TARGET_PAGE_BITS);
1258 } else {
1259 tcg_out_rld(s, RLDICL, TCG_REG_R0, addr_reg,
1260 64 - TARGET_PAGE_BITS, TARGET_PAGE_BITS - s_bits);
1261 tcg_out_rld(s, RLDICL, TCG_REG_R0, TCG_REG_R0, TARGET_PAGE_BITS, 0);
1262 }
1263
1264 tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_R2, 0, 7, TCG_TYPE_TL);
1265
1266 return addr_reg;
1267 }
1268
1269 /* Record the context of a call to the out of line helper code for the slow
1270 path for a load or store, so that we can later generate the correct
1271 helper code. */
1272 static void add_qemu_ldst_label(TCGContext *s, bool is_ld, TCGMemOp opc,
1273 int data_reg, int addr_reg, int mem_index,
1274 tcg_insn_unit *raddr, tcg_insn_unit *label_ptr)
1275 {
1276 TCGLabelQemuLdst *label = new_ldst_label(s);
1277
1278 label->is_ld = is_ld;
1279 label->opc = opc;
1280 label->datalo_reg = data_reg;
1281 label->addrlo_reg = addr_reg;
1282 label->mem_index = mem_index;
1283 label->raddr = raddr;
1284 label->label_ptr[0] = label_ptr;
1285 }
1286
1287 static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
1288 {
1289 TCGMemOp opc = lb->opc;
1290
1291 reloc_pc14(lb->label_ptr[0], s->code_ptr);
1292
1293 tcg_out_mov(s, TCG_TYPE_PTR, TCG_REG_R3, TCG_AREG0);
1294
1295 /* If the address needed to be zero-extended, we'll have already
1296 placed it in R4. The only remaining case is 64-bit guest. */
1297 tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R4, lb->addrlo_reg);
1298
1299 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R5, lb->mem_index);
1300 tcg_out32(s, MFSPR | RT(TCG_REG_R6) | LR);
1301
1302 tcg_out_call(s, qemu_ld_helpers[opc & ~MO_SIGN]);
1303
1304 if (opc & MO_SIGN) {
1305 uint32_t insn = qemu_exts_opc[opc & MO_SIZE];
1306 tcg_out32(s, insn | RA(lb->datalo_reg) | RS(TCG_REG_R3));
1307 } else {
1308 tcg_out_mov(s, TCG_TYPE_I64, lb->datalo_reg, TCG_REG_R3);
1309 }
1310
1311 tcg_out_b(s, 0, lb->raddr);
1312 }
1313
1314 static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb)
1315 {
1316 TCGMemOp opc = lb->opc;
1317 TCGMemOp s_bits = opc & MO_SIZE;
1318
1319 reloc_pc14(lb->label_ptr[0], s->code_ptr);
1320
1321 tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R3, TCG_AREG0);
1322
1323 /* If the address needed to be zero-extended, we'll have already
1324 placed it in R4. The only remaining case is 64-bit guest. */
1325 tcg_out_mov(s, TCG_TYPE_I64, TCG_REG_R4, lb->addrlo_reg);
1326
1327 tcg_out_rld(s, RLDICL, TCG_REG_R5, lb->datalo_reg,
1328 0, 64 - (1 << (3 + s_bits)));
1329 tcg_out_movi(s, TCG_TYPE_I32, TCG_REG_R6, lb->mem_index);
1330 tcg_out32(s, MFSPR | RT(TCG_REG_R7) | LR);
1331
1332 tcg_out_call(s, qemu_st_helpers[opc]);
1333
1334 tcg_out_b(s, 0, lb->raddr);
1335 }
1336 #endif /* SOFTMMU */
1337
1338 static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
1339 TCGMemOp opc, int mem_index)
1340 {
1341 TCGReg rbase;
1342 uint32_t insn;
1343 TCGMemOp s_bits = opc & MO_SIZE;
1344 #ifdef CONFIG_SOFTMMU
1345 tcg_insn_unit *label_ptr;
1346 #endif
1347
1348 #ifdef CONFIG_SOFTMMU
1349 addr_reg = tcg_out_tlb_read(s, s_bits, addr_reg, mem_index, true);
1350
1351 /* Load a pointer into the current opcode w/conditional branch-link. */
1352 label_ptr = s->code_ptr;
1353 tcg_out_bc_noaddr(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
1354
1355 rbase = TCG_REG_R3;
1356 #else /* !CONFIG_SOFTMMU */
1357 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
1358 if (TARGET_LONG_BITS == 32) {
1359 tcg_out_ext32u(s, TCG_REG_R2, addr_reg);
1360 addr_reg = TCG_REG_R2;
1361 }
1362 #endif
1363
1364 insn = qemu_ldx_opc[opc];
1365 if (!HAVE_ISA_2_06 && insn == LDBRX) {
1366 tcg_out32(s, ADDI | TAI(TCG_REG_R0, addr_reg, 4));
1367 tcg_out32(s, LWBRX | TAB(data_reg, rbase, addr_reg));
1368 tcg_out32(s, LWBRX | TAB(TCG_REG_R0, rbase, TCG_REG_R0));
1369 tcg_out_rld(s, RLDIMI, data_reg, TCG_REG_R0, 32, 0);
1370 } else if (insn) {
1371 tcg_out32(s, insn | TAB(data_reg, rbase, addr_reg));
1372 } else {
1373 insn = qemu_ldx_opc[opc & (MO_SIZE | MO_BSWAP)];
1374 tcg_out32(s, insn | TAB(data_reg, rbase, addr_reg));
1375 insn = qemu_exts_opc[s_bits];
1376 tcg_out32(s, insn | RA(data_reg) | RS(data_reg));
1377 }
1378
1379 #ifdef CONFIG_SOFTMMU
1380 add_qemu_ldst_label(s, true, opc, data_reg, addr_reg, mem_index,
1381 s->code_ptr, label_ptr);
1382 #endif
1383 }
1384
1385 static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
1386 TCGMemOp opc, int mem_index)
1387 {
1388 TCGReg rbase;
1389 uint32_t insn;
1390 #ifdef CONFIG_SOFTMMU
1391 tcg_insn_unit *label_ptr;
1392 #endif
1393
1394 #ifdef CONFIG_SOFTMMU
1395 addr_reg = tcg_out_tlb_read(s, opc & MO_SIZE, addr_reg, mem_index, false);
1396
1397 /* Load a pointer into the current opcode w/conditional branch-link. */
1398 label_ptr = s->code_ptr;
1399 tcg_out_bc_noaddr(s, BC | BI(7, CR_EQ) | BO_COND_FALSE | LK);
1400
1401 rbase = TCG_REG_R3;
1402 #else /* !CONFIG_SOFTMMU */
1403 rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
1404 if (TARGET_LONG_BITS == 32) {
1405 tcg_out_ext32u(s, TCG_REG_R2, addr_reg);
1406 addr_reg = TCG_REG_R2;
1407 }
1408 #endif
1409
1410 insn = qemu_stx_opc[opc];
1411 if (!HAVE_ISA_2_06 && insn == STDBRX) {
1412 tcg_out32(s, STWBRX | SAB(data_reg, rbase, addr_reg));
1413 tcg_out32(s, ADDI | TAI(TCG_REG_R2, addr_reg, 4));
1414 tcg_out_shri64(s, TCG_REG_R0, data_reg, 32);
1415 tcg_out32(s, STWBRX | SAB(TCG_REG_R0, rbase, TCG_REG_R2));
1416 } else {
1417 tcg_out32(s, insn | SAB(data_reg, rbase, addr_reg));
1418 }
1419
1420 #ifdef CONFIG_SOFTMMU
1421 add_qemu_ldst_label(s, false, opc, data_reg, addr_reg, mem_index,
1422 s->code_ptr, label_ptr);
1423 #endif
1424 }
1425
1426 /* Parameters for function call generation, used in tcg.c. */
1427 #define TCG_TARGET_STACK_ALIGN 16
1428 #define TCG_TARGET_EXTEND_ARGS 1
1429
1430 #ifdef _CALL_AIX
1431 # define LINK_AREA_SIZE (6 * SZR)
1432 # define LR_OFFSET (1 * SZR)
1433 # define TCG_TARGET_CALL_STACK_OFFSET (LINK_AREA_SIZE + 8 * SZR)
1434 #elif defined(_CALL_ELF) && _CALL_ELF == 2
1435 # define LINK_AREA_SIZE (4 * SZR)
1436 # define LR_OFFSET (1 * SZR)
1437 # define TCG_TARGET_CALL_STACK_OFFSET LINK_AREA_SIZE
1438 #else
1439 # error
1440 #endif
1441
1442 #define CPU_TEMP_BUF_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long))
1443 #define REG_SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * SZR)
1444
1445 #define FRAME_SIZE ((TCG_TARGET_CALL_STACK_OFFSET \
1446 + TCG_STATIC_CALL_ARGS_SIZE \
1447 + CPU_TEMP_BUF_SIZE \
1448 + REG_SAVE_SIZE \
1449 + TCG_TARGET_STACK_ALIGN - 1) \
1450 & -TCG_TARGET_STACK_ALIGN)
1451
1452 #define REG_SAVE_BOT (FRAME_SIZE - REG_SAVE_SIZE)
1453
1454 static void tcg_target_qemu_prologue(TCGContext *s)
1455 {
1456 int i;
1457
1458 tcg_set_frame(s, TCG_REG_CALL_STACK, REG_SAVE_BOT - CPU_TEMP_BUF_SIZE,
1459 CPU_TEMP_BUF_SIZE);
1460
1461 #ifdef _CALL_AIX
1462 {
1463 void **desc = (void **)s->code_ptr;
1464 desc[0] = desc + 2; /* entry point */
1465 desc[1] = 0; /* environment pointer */
1466 s->code_ptr = (void *)(desc + 2); /* skip over descriptor */
1467 }
1468 #endif
1469
1470 /* Prologue */
1471 tcg_out32(s, MFSPR | RT(TCG_REG_R0) | LR);
1472 tcg_out32(s, STDU | SAI(TCG_REG_R1, TCG_REG_R1, -FRAME_SIZE));
1473
1474 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
1475 tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
1476 TCG_REG_R1, REG_SAVE_BOT + i * SZR);
1477 }
1478 tcg_out_st(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET);
1479
1480 #ifdef CONFIG_USE_GUEST_BASE
1481 if (GUEST_BASE) {
1482 tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, GUEST_BASE);
1483 tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG);
1484 }
1485 #endif
1486
1487 tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]);
1488 tcg_out32(s, MTSPR | RS(tcg_target_call_iarg_regs[1]) | CTR);
1489 tcg_out32(s, BCCTR | BO_ALWAYS);
1490
1491 /* Epilogue */
1492 tb_ret_addr = s->code_ptr;
1493
1494 tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_R0, TCG_REG_R1, FRAME_SIZE+LR_OFFSET);
1495 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i) {
1496 tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i],
1497 TCG_REG_R1, REG_SAVE_BOT + i * SZR);
1498 }
1499 tcg_out32(s, MTSPR | RS(TCG_REG_R0) | LR);
1500 tcg_out32(s, ADDI | TAI(TCG_REG_R1, TCG_REG_R1, FRAME_SIZE));
1501 tcg_out32(s, BCLR | BO_ALWAYS);
1502 }
1503
1504 static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
1505 const int *const_args)
1506 {
1507 TCGArg a0, a1, a2;
1508 int c;
1509
1510 switch (opc) {
1511 case INDEX_op_exit_tb:
1512 tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_R3, args[0]);
1513 tcg_out_b(s, 0, tb_ret_addr);
1514 break;
1515 case INDEX_op_goto_tb:
1516 if (s->tb_jmp_offset) {
1517 /* Direct jump method. */
1518 s->tb_jmp_offset[args[0]] = tcg_current_code_size(s);
1519 s->code_ptr += 7;
1520 } else {
1521 /* Indirect jump method. */
1522 tcg_abort();
1523 }
1524 s->tb_next_offset[args[0]] = tcg_current_code_size(s);
1525 break;
1526 case INDEX_op_br:
1527 {
1528 TCGLabel *l = &s->labels[args[0]];
1529
1530 if (l->has_value) {
1531 tcg_out_b(s, 0, l->u.value_ptr);
1532 } else {
1533 tcg_out_reloc(s, s->code_ptr, R_PPC_REL24, args[0], 0);
1534 tcg_out_b_noaddr(s, B);
1535 }
1536 }
1537 break;
1538 case INDEX_op_ld8u_i32:
1539 case INDEX_op_ld8u_i64:
1540 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
1541 break;
1542 case INDEX_op_ld8s_i32:
1543 case INDEX_op_ld8s_i64:
1544 tcg_out_mem_long(s, LBZ, LBZX, args[0], args[1], args[2]);
1545 tcg_out32(s, EXTSB | RS(args[0]) | RA(args[0]));
1546 break;
1547 case INDEX_op_ld16u_i32:
1548 case INDEX_op_ld16u_i64:
1549 tcg_out_mem_long(s, LHZ, LHZX, args[0], args[1], args[2]);
1550 break;
1551 case INDEX_op_ld16s_i32:
1552 case INDEX_op_ld16s_i64:
1553 tcg_out_mem_long(s, LHA, LHAX, args[0], args[1], args[2]);
1554 break;
1555 case INDEX_op_ld_i32:
1556 case INDEX_op_ld32u_i64:
1557 tcg_out_mem_long(s, LWZ, LWZX, args[0], args[1], args[2]);
1558 break;
1559 case INDEX_op_ld32s_i64:
1560 tcg_out_mem_long(s, LWA, LWAX, args[0], args[1], args[2]);
1561 break;
1562 case INDEX_op_ld_i64:
1563 tcg_out_mem_long(s, LD, LDX, args[0], args[1], args[2]);
1564 break;
1565 case INDEX_op_st8_i32:
1566 case INDEX_op_st8_i64:
1567 tcg_out_mem_long(s, STB, STBX, args[0], args[1], args[2]);
1568 break;
1569 case INDEX_op_st16_i32:
1570 case INDEX_op_st16_i64:
1571 tcg_out_mem_long(s, STH, STHX, args[0], args[1], args[2]);
1572 break;
1573 case INDEX_op_st_i32:
1574 case INDEX_op_st32_i64:
1575 tcg_out_mem_long(s, STW, STWX, args[0], args[1], args[2]);
1576 break;
1577 case INDEX_op_st_i64:
1578 tcg_out_mem_long(s, STD, STDX, args[0], args[1], args[2]);
1579 break;
1580
1581 case INDEX_op_add_i32:
1582 a0 = args[0], a1 = args[1], a2 = args[2];
1583 if (const_args[2]) {
1584 do_addi_32:
1585 tcg_out_mem_long(s, ADDI, ADD, a0, a1, (int32_t)a2);
1586 } else {
1587 tcg_out32(s, ADD | TAB(a0, a1, a2));
1588 }
1589 break;
1590 case INDEX_op_sub_i32:
1591 a0 = args[0], a1 = args[1], a2 = args[2];
1592 if (const_args[1]) {
1593 if (const_args[2]) {
1594 tcg_out_movi(s, TCG_TYPE_I32, a0, a1 - a2);
1595 } else {
1596 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
1597 }
1598 } else if (const_args[2]) {
1599 a2 = -a2;
1600 goto do_addi_32;
1601 } else {
1602 tcg_out32(s, SUBF | TAB(a0, a2, a1));
1603 }
1604 break;
1605
1606 case INDEX_op_and_i32:
1607 a0 = args[0], a1 = args[1], a2 = args[2];
1608 if (const_args[2]) {
1609 tcg_out_andi32(s, a0, a1, a2);
1610 } else {
1611 tcg_out32(s, AND | SAB(a1, a0, a2));
1612 }
1613 break;
1614 case INDEX_op_and_i64:
1615 a0 = args[0], a1 = args[1], a2 = args[2];
1616 if (const_args[2]) {
1617 tcg_out_andi64(s, a0, a1, a2);
1618 } else {
1619 tcg_out32(s, AND | SAB(a1, a0, a2));
1620 }
1621 break;
1622 case INDEX_op_or_i64:
1623 case INDEX_op_or_i32:
1624 a0 = args[0], a1 = args[1], a2 = args[2];
1625 if (const_args[2]) {
1626 tcg_out_ori32(s, a0, a1, a2);
1627 } else {
1628 tcg_out32(s, OR | SAB(a1, a0, a2));
1629 }
1630 break;
1631 case INDEX_op_xor_i64:
1632 case INDEX_op_xor_i32:
1633 a0 = args[0], a1 = args[1], a2 = args[2];
1634 if (const_args[2]) {
1635 tcg_out_xori32(s, a0, a1, a2);
1636 } else {
1637 tcg_out32(s, XOR | SAB(a1, a0, a2));
1638 }
1639 break;
1640 case INDEX_op_andc_i32:
1641 a0 = args[0], a1 = args[1], a2 = args[2];
1642 if (const_args[2]) {
1643 tcg_out_andi32(s, a0, a1, ~a2);
1644 } else {
1645 tcg_out32(s, ANDC | SAB(a1, a0, a2));
1646 }
1647 break;
1648 case INDEX_op_andc_i64:
1649 a0 = args[0], a1 = args[1], a2 = args[2];
1650 if (const_args[2]) {
1651 tcg_out_andi64(s, a0, a1, ~a2);
1652 } else {
1653 tcg_out32(s, ANDC | SAB(a1, a0, a2));
1654 }
1655 break;
1656 case INDEX_op_orc_i32:
1657 if (const_args[2]) {
1658 tcg_out_ori32(s, args[0], args[1], ~args[2]);
1659 break;
1660 }
1661 /* FALLTHRU */
1662 case INDEX_op_orc_i64:
1663 tcg_out32(s, ORC | SAB(args[1], args[0], args[2]));
1664 break;
1665 case INDEX_op_eqv_i32:
1666 if (const_args[2]) {
1667 tcg_out_xori32(s, args[0], args[1], ~args[2]);
1668 break;
1669 }
1670 /* FALLTHRU */
1671 case INDEX_op_eqv_i64:
1672 tcg_out32(s, EQV | SAB(args[1], args[0], args[2]));
1673 break;
1674 case INDEX_op_nand_i32:
1675 case INDEX_op_nand_i64:
1676 tcg_out32(s, NAND | SAB(args[1], args[0], args[2]));
1677 break;
1678 case INDEX_op_nor_i32:
1679 case INDEX_op_nor_i64:
1680 tcg_out32(s, NOR | SAB(args[1], args[0], args[2]));
1681 break;
1682
1683 case INDEX_op_mul_i32:
1684 a0 = args[0], a1 = args[1], a2 = args[2];
1685 if (const_args[2]) {
1686 tcg_out32(s, MULLI | TAI(a0, a1, a2));
1687 } else {
1688 tcg_out32(s, MULLW | TAB(a0, a1, a2));
1689 }
1690 break;
1691
1692 case INDEX_op_div_i32:
1693 tcg_out32(s, DIVW | TAB(args[0], args[1], args[2]));
1694 break;
1695
1696 case INDEX_op_divu_i32:
1697 tcg_out32(s, DIVWU | TAB(args[0], args[1], args[2]));
1698 break;
1699
1700 case INDEX_op_shl_i32:
1701 if (const_args[2]) {
1702 tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31 - args[2]);
1703 } else {
1704 tcg_out32(s, SLW | SAB(args[1], args[0], args[2]));
1705 }
1706 break;
1707 case INDEX_op_shr_i32:
1708 if (const_args[2]) {
1709 tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], args[2], 31);
1710 } else {
1711 tcg_out32(s, SRW | SAB(args[1], args[0], args[2]));
1712 }
1713 break;
1714 case INDEX_op_sar_i32:
1715 if (const_args[2]) {
1716 tcg_out32(s, SRAWI | RS(args[1]) | RA(args[0]) | SH(args[2]));
1717 } else {
1718 tcg_out32(s, SRAW | SAB(args[1], args[0], args[2]));
1719 }
1720 break;
1721 case INDEX_op_rotl_i32:
1722 if (const_args[2]) {
1723 tcg_out_rlw(s, RLWINM, args[0], args[1], args[2], 0, 31);
1724 } else {
1725 tcg_out32(s, RLWNM | SAB(args[1], args[0], args[2])
1726 | MB(0) | ME(31));
1727 }
1728 break;
1729 case INDEX_op_rotr_i32:
1730 if (const_args[2]) {
1731 tcg_out_rlw(s, RLWINM, args[0], args[1], 32 - args[2], 0, 31);
1732 } else {
1733 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 32));
1734 tcg_out32(s, RLWNM | SAB(args[1], args[0], TCG_REG_R0)
1735 | MB(0) | ME(31));
1736 }
1737 break;
1738
1739 case INDEX_op_brcond_i32:
1740 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1741 args[3], TCG_TYPE_I32);
1742 break;
1743
1744 case INDEX_op_brcond_i64:
1745 tcg_out_brcond(s, args[2], args[0], args[1], const_args[1],
1746 args[3], TCG_TYPE_I64);
1747 break;
1748
1749 case INDEX_op_neg_i32:
1750 case INDEX_op_neg_i64:
1751 tcg_out32(s, NEG | RT(args[0]) | RA(args[1]));
1752 break;
1753
1754 case INDEX_op_not_i32:
1755 case INDEX_op_not_i64:
1756 tcg_out32(s, NOR | SAB(args[1], args[0], args[1]));
1757 break;
1758
1759 case INDEX_op_add_i64:
1760 a0 = args[0], a1 = args[1], a2 = args[2];
1761 if (const_args[2]) {
1762 do_addi_64:
1763 tcg_out_mem_long(s, ADDI, ADD, a0, a1, a2);
1764 } else {
1765 tcg_out32(s, ADD | TAB(a0, a1, a2));
1766 }
1767 break;
1768 case INDEX_op_sub_i64:
1769 a0 = args[0], a1 = args[1], a2 = args[2];
1770 if (const_args[1]) {
1771 if (const_args[2]) {
1772 tcg_out_movi(s, TCG_TYPE_I64, a0, a1 - a2);
1773 } else {
1774 tcg_out32(s, SUBFIC | TAI(a0, a2, a1));
1775 }
1776 } else if (const_args[2]) {
1777 a2 = -a2;
1778 goto do_addi_64;
1779 } else {
1780 tcg_out32(s, SUBF | TAB(a0, a2, a1));
1781 }
1782 break;
1783
1784 case INDEX_op_shl_i64:
1785 if (const_args[2]) {
1786 tcg_out_shli64(s, args[0], args[1], args[2]);
1787 } else {
1788 tcg_out32(s, SLD | SAB(args[1], args[0], args[2]));
1789 }
1790 break;
1791 case INDEX_op_shr_i64:
1792 if (const_args[2]) {
1793 tcg_out_shri64(s, args[0], args[1], args[2]);
1794 } else {
1795 tcg_out32(s, SRD | SAB(args[1], args[0], args[2]));
1796 }
1797 break;
1798 case INDEX_op_sar_i64:
1799 if (const_args[2]) {
1800 int sh = SH(args[2] & 0x1f) | (((args[2] >> 5) & 1) << 1);
1801 tcg_out32(s, SRADI | RA(args[0]) | RS(args[1]) | sh);
1802 } else {
1803 tcg_out32(s, SRAD | SAB(args[1], args[0], args[2]));
1804 }
1805 break;
1806 case INDEX_op_rotl_i64:
1807 if (const_args[2]) {
1808 tcg_out_rld(s, RLDICL, args[0], args[1], args[2], 0);
1809 } else {
1810 tcg_out32(s, RLDCL | SAB(args[1], args[0], args[2]) | MB64(0));
1811 }
1812 break;
1813 case INDEX_op_rotr_i64:
1814 if (const_args[2]) {
1815 tcg_out_rld(s, RLDICL, args[0], args[1], 64 - args[2], 0);
1816 } else {
1817 tcg_out32(s, SUBFIC | TAI(TCG_REG_R0, args[2], 64));
1818 tcg_out32(s, RLDCL | SAB(args[1], args[0], TCG_REG_R0) | MB64(0));
1819 }
1820 break;
1821
1822 case INDEX_op_mul_i64:
1823 a0 = args[0], a1 = args[1], a2 = args[2];
1824 if (const_args[2]) {
1825 tcg_out32(s, MULLI | TAI(a0, a1, a2));
1826 } else {
1827 tcg_out32(s, MULLD | TAB(a0, a1, a2));
1828 }
1829 break;
1830 case INDEX_op_div_i64:
1831 tcg_out32(s, DIVD | TAB(args[0], args[1], args[2]));
1832 break;
1833 case INDEX_op_divu_i64:
1834 tcg_out32(s, DIVDU | TAB(args[0], args[1], args[2]));
1835 break;
1836
1837 case INDEX_op_qemu_ld_i32:
1838 case INDEX_op_qemu_ld_i64:
1839 tcg_out_qemu_ld(s, args[0], args[1], args[2], args[3]);
1840 break;
1841 case INDEX_op_qemu_st_i32:
1842 case INDEX_op_qemu_st_i64:
1843 tcg_out_qemu_st(s, args[0], args[1], args[2], args[3]);
1844 break;
1845
1846 case INDEX_op_ext8s_i32:
1847 case INDEX_op_ext8s_i64:
1848 c = EXTSB;
1849 goto gen_ext;
1850 case INDEX_op_ext16s_i32:
1851 case INDEX_op_ext16s_i64:
1852 c = EXTSH;
1853 goto gen_ext;
1854 case INDEX_op_ext32s_i64:
1855 c = EXTSW;
1856 goto gen_ext;
1857 gen_ext:
1858 tcg_out32(s, c | RS(args[1]) | RA(args[0]));
1859 break;
1860
1861 case INDEX_op_setcond_i32:
1862 tcg_out_setcond(s, TCG_TYPE_I32, args[3], args[0], args[1], args[2],
1863 const_args[2]);
1864 break;
1865 case INDEX_op_setcond_i64:
1866 tcg_out_setcond(s, TCG_TYPE_I64, args[3], args[0], args[1], args[2],
1867 const_args[2]);
1868 break;
1869
1870 case INDEX_op_bswap16_i32:
1871 case INDEX_op_bswap16_i64:
1872 a0 = args[0], a1 = args[1];
1873 /* a1 = abcd */
1874 if (a0 != a1) {
1875 /* a0 = (a1 r<< 24) & 0xff # 000c */
1876 tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
1877 /* a0 = (a0 & ~0xff00) | (a1 r<< 8) & 0xff00 # 00dc */
1878 tcg_out_rlw(s, RLWIMI, a0, a1, 8, 16, 23);
1879 } else {
1880 /* r0 = (a1 r<< 8) & 0xff00 # 00d0 */
1881 tcg_out_rlw(s, RLWINM, TCG_REG_R0, a1, 8, 16, 23);
1882 /* a0 = (a1 r<< 24) & 0xff # 000c */
1883 tcg_out_rlw(s, RLWINM, a0, a1, 24, 24, 31);
1884 /* a0 = a0 | r0 # 00dc */
1885 tcg_out32(s, OR | SAB(TCG_REG_R0, a0, a0));
1886 }
1887 break;
1888
1889 case INDEX_op_bswap32_i32:
1890 case INDEX_op_bswap32_i64:
1891 /* Stolen from gcc's builtin_bswap32 */
1892 a1 = args[1];
1893 a0 = args[0] == a1 ? TCG_REG_R0 : args[0];
1894
1895 /* a1 = args[1] # abcd */
1896 /* a0 = rotate_left (a1, 8) # bcda */
1897 tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
1898 /* a0 = (a0 & ~0xff000000) | ((a1 r<< 24) & 0xff000000) # dcda */
1899 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
1900 /* a0 = (a0 & ~0x0000ff00) | ((a1 r<< 24) & 0x0000ff00) # dcba */
1901 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
1902
1903 if (a0 == TCG_REG_R0) {
1904 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
1905 }
1906 break;
1907
1908 case INDEX_op_bswap64_i64:
1909 a0 = args[0], a1 = args[1], a2 = TCG_REG_R0;
1910 if (a0 == a1) {
1911 a0 = TCG_REG_R0;
1912 a2 = a1;
1913 }
1914
1915 /* a1 = # abcd efgh */
1916 /* a0 = rl32(a1, 8) # 0000 fghe */
1917 tcg_out_rlw(s, RLWINM, a0, a1, 8, 0, 31);
1918 /* a0 = dep(a0, rl32(a1, 24), 0xff000000) # 0000 hghe */
1919 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 0, 7);
1920 /* a0 = dep(a0, rl32(a1, 24), 0x0000ff00) # 0000 hgfe */
1921 tcg_out_rlw(s, RLWIMI, a0, a1, 24, 16, 23);
1922
1923 /* a0 = rl64(a0, 32) # hgfe 0000 */
1924 /* a2 = rl64(a1, 32) # efgh abcd */
1925 tcg_out_rld(s, RLDICL, a0, a0, 32, 0);
1926 tcg_out_rld(s, RLDICL, a2, a1, 32, 0);
1927
1928 /* a0 = dep(a0, rl32(a2, 8), 0xffffffff) # hgfe bcda */
1929 tcg_out_rlw(s, RLWIMI, a0, a2, 8, 0, 31);
1930 /* a0 = dep(a0, rl32(a2, 24), 0xff000000) # hgfe dcda */
1931 tcg_out_rlw(s, RLWIMI, a0, a2, 24, 0, 7);
1932 /* a0 = dep(a0, rl32(a2, 24), 0x0000ff00) # hgfe dcba */
1933 tcg_out_rlw(s, RLWIMI, a0, a2, 24, 16, 23);
1934
1935 if (a0 == 0) {
1936 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
1937 }
1938 break;
1939
1940 case INDEX_op_deposit_i32:
1941 if (const_args[2]) {
1942 uint32_t mask = ((2u << (args[4] - 1)) - 1) << args[3];
1943 tcg_out_andi32(s, args[0], args[0], ~mask);
1944 } else {
1945 tcg_out_rlw(s, RLWIMI, args[0], args[2], args[3],
1946 32 - args[3] - args[4], 31 - args[3]);
1947 }
1948 break;
1949 case INDEX_op_deposit_i64:
1950 if (const_args[2]) {
1951 uint64_t mask = ((2ull << (args[4] - 1)) - 1) << args[3];
1952 tcg_out_andi64(s, args[0], args[0], ~mask);
1953 } else {
1954 tcg_out_rld(s, RLDIMI, args[0], args[2], args[3],
1955 64 - args[3] - args[4]);
1956 }
1957 break;
1958
1959 case INDEX_op_movcond_i32:
1960 tcg_out_movcond(s, TCG_TYPE_I32, args[5], args[0], args[1], args[2],
1961 args[3], args[4], const_args[2]);
1962 break;
1963 case INDEX_op_movcond_i64:
1964 tcg_out_movcond(s, TCG_TYPE_I64, args[5], args[0], args[1], args[2],
1965 args[3], args[4], const_args[2]);
1966 break;
1967
1968 case INDEX_op_add2_i64:
1969 /* Note that the CA bit is defined based on the word size of the
1970 environment. So in 64-bit mode it's always carry-out of bit 63.
1971 The fallback code using deposit works just as well for 32-bit. */
1972 a0 = args[0], a1 = args[1];
1973 if (a0 == args[3] || (!const_args[5] && a0 == args[5])) {
1974 a0 = TCG_REG_R0;
1975 }
1976 if (const_args[4]) {
1977 tcg_out32(s, ADDIC | TAI(a0, args[2], args[4]));
1978 } else {
1979 tcg_out32(s, ADDC | TAB(a0, args[2], args[4]));
1980 }
1981 if (const_args[5]) {
1982 tcg_out32(s, (args[5] ? ADDME : ADDZE) | RT(a1) | RA(args[3]));
1983 } else {
1984 tcg_out32(s, ADDE | TAB(a1, args[3], args[5]));
1985 }
1986 if (a0 != args[0]) {
1987 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
1988 }
1989 break;
1990
1991 case INDEX_op_sub2_i64:
1992 a0 = args[0], a1 = args[1];
1993 if (a0 == args[5] || (!const_args[4] && a0 == args[4])) {
1994 a0 = TCG_REG_R0;
1995 }
1996 if (const_args[2]) {
1997 tcg_out32(s, SUBFIC | TAI(a0, args[3], args[2]));
1998 } else {
1999 tcg_out32(s, SUBFC | TAB(a0, args[3], args[2]));
2000 }
2001 if (const_args[4]) {
2002 tcg_out32(s, (args[4] ? SUBFME : SUBFZE) | RT(a1) | RA(args[5]));
2003 } else {
2004 tcg_out32(s, SUBFE | TAB(a1, args[5], args[4]));
2005 }
2006 if (a0 != args[0]) {
2007 tcg_out_mov(s, TCG_TYPE_REG, args[0], a0);
2008 }
2009 break;
2010
2011 case INDEX_op_muluh_i64:
2012 tcg_out32(s, MULHDU | TAB(args[0], args[1], args[2]));
2013 break;
2014 case INDEX_op_mulsh_i64:
2015 tcg_out32(s, MULHD | TAB(args[0], args[1], args[2]));
2016 break;
2017
2018 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
2019 case INDEX_op_mov_i64:
2020 case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
2021 case INDEX_op_movi_i64:
2022 case INDEX_op_call: /* Always emitted via tcg_out_call. */
2023 default:
2024 tcg_abort();
2025 }
2026 }
2027
2028 static const TCGTargetOpDef ppc_op_defs[] = {
2029 { INDEX_op_exit_tb, { } },
2030 { INDEX_op_goto_tb, { } },
2031 { INDEX_op_br, { } },
2032
2033 { INDEX_op_ld8u_i32, { "r", "r" } },
2034 { INDEX_op_ld8s_i32, { "r", "r" } },
2035 { INDEX_op_ld16u_i32, { "r", "r" } },
2036 { INDEX_op_ld16s_i32, { "r", "r" } },
2037 { INDEX_op_ld_i32, { "r", "r" } },
2038 { INDEX_op_ld_i64, { "r", "r" } },
2039 { INDEX_op_st8_i32, { "r", "r" } },
2040 { INDEX_op_st8_i64, { "r", "r" } },
2041 { INDEX_op_st16_i32, { "r", "r" } },
2042 { INDEX_op_st16_i64, { "r", "r" } },
2043 { INDEX_op_st_i32, { "r", "r" } },
2044 { INDEX_op_st_i64, { "r", "r" } },
2045 { INDEX_op_st32_i64, { "r", "r" } },
2046
2047 { INDEX_op_ld8u_i64, { "r", "r" } },
2048 { INDEX_op_ld8s_i64, { "r", "r" } },
2049 { INDEX_op_ld16u_i64, { "r", "r" } },
2050 { INDEX_op_ld16s_i64, { "r", "r" } },
2051 { INDEX_op_ld32u_i64, { "r", "r" } },
2052 { INDEX_op_ld32s_i64, { "r", "r" } },
2053
2054 { INDEX_op_add_i32, { "r", "r", "ri" } },
2055 { INDEX_op_mul_i32, { "r", "r", "rI" } },
2056 { INDEX_op_div_i32, { "r", "r", "r" } },
2057 { INDEX_op_divu_i32, { "r", "r", "r" } },
2058 { INDEX_op_sub_i32, { "r", "rI", "ri" } },
2059 { INDEX_op_and_i32, { "r", "r", "ri" } },
2060 { INDEX_op_or_i32, { "r", "r", "ri" } },
2061 { INDEX_op_xor_i32, { "r", "r", "ri" } },
2062 { INDEX_op_andc_i32, { "r", "r", "ri" } },
2063 { INDEX_op_orc_i32, { "r", "r", "ri" } },
2064 { INDEX_op_eqv_i32, { "r", "r", "ri" } },
2065 { INDEX_op_nand_i32, { "r", "r", "r" } },
2066 { INDEX_op_nor_i32, { "r", "r", "r" } },
2067
2068 { INDEX_op_shl_i32, { "r", "r", "ri" } },
2069 { INDEX_op_shr_i32, { "r", "r", "ri" } },
2070 { INDEX_op_sar_i32, { "r", "r", "ri" } },
2071 { INDEX_op_rotl_i32, { "r", "r", "ri" } },
2072 { INDEX_op_rotr_i32, { "r", "r", "ri" } },
2073
2074 { INDEX_op_brcond_i32, { "r", "ri" } },
2075 { INDEX_op_brcond_i64, { "r", "ri" } },
2076
2077 { INDEX_op_neg_i32, { "r", "r" } },
2078 { INDEX_op_not_i32, { "r", "r" } },
2079
2080 { INDEX_op_add_i64, { "r", "r", "rT" } },
2081 { INDEX_op_sub_i64, { "r", "rI", "rT" } },
2082 { INDEX_op_and_i64, { "r", "r", "ri" } },
2083 { INDEX_op_or_i64, { "r", "r", "rU" } },
2084 { INDEX_op_xor_i64, { "r", "r", "rU" } },
2085 { INDEX_op_andc_i64, { "r", "r", "ri" } },
2086 { INDEX_op_orc_i64, { "r", "r", "r" } },
2087 { INDEX_op_eqv_i64, { "r", "r", "r" } },
2088 { INDEX_op_nand_i64, { "r", "r", "r" } },
2089 { INDEX_op_nor_i64, { "r", "r", "r" } },
2090
2091 { INDEX_op_shl_i64, { "r", "r", "ri" } },
2092 { INDEX_op_shr_i64, { "r", "r", "ri" } },
2093 { INDEX_op_sar_i64, { "r", "r", "ri" } },
2094 { INDEX_op_rotl_i64, { "r", "r", "ri" } },
2095 { INDEX_op_rotr_i64, { "r", "r", "ri" } },
2096
2097 { INDEX_op_mul_i64, { "r", "r", "rI" } },
2098 { INDEX_op_div_i64, { "r", "r", "r" } },
2099 { INDEX_op_divu_i64, { "r", "r", "r" } },
2100
2101 { INDEX_op_neg_i64, { "r", "r" } },
2102 { INDEX_op_not_i64, { "r", "r" } },
2103
2104 { INDEX_op_qemu_ld_i32, { "r", "L" } },
2105 { INDEX_op_qemu_ld_i64, { "r", "L" } },
2106 { INDEX_op_qemu_st_i32, { "S", "S" } },
2107 { INDEX_op_qemu_st_i64, { "S", "S" } },
2108
2109 { INDEX_op_ext8s_i32, { "r", "r" } },
2110 { INDEX_op_ext16s_i32, { "r", "r" } },
2111 { INDEX_op_ext8s_i64, { "r", "r" } },
2112 { INDEX_op_ext16s_i64, { "r", "r" } },
2113 { INDEX_op_ext32s_i64, { "r", "r" } },
2114
2115 { INDEX_op_setcond_i32, { "r", "r", "ri" } },
2116 { INDEX_op_setcond_i64, { "r", "r", "ri" } },
2117 { INDEX_op_movcond_i32, { "r", "r", "ri", "rZ", "rZ" } },
2118 { INDEX_op_movcond_i64, { "r", "r", "ri", "rZ", "rZ" } },
2119
2120 { INDEX_op_bswap16_i32, { "r", "r" } },
2121 { INDEX_op_bswap16_i64, { "r", "r" } },
2122 { INDEX_op_bswap32_i32, { "r", "r" } },
2123 { INDEX_op_bswap32_i64, { "r", "r" } },
2124 { INDEX_op_bswap64_i64, { "r", "r" } },
2125
2126 { INDEX_op_deposit_i32, { "r", "0", "rZ" } },
2127 { INDEX_op_deposit_i64, { "r", "0", "rZ" } },
2128
2129 { INDEX_op_add2_i64, { "r", "r", "r", "r", "rI", "rZM" } },
2130 { INDEX_op_sub2_i64, { "r", "r", "rI", "r", "rZM", "r" } },
2131 { INDEX_op_mulsh_i64, { "r", "r", "r" } },
2132 { INDEX_op_muluh_i64, { "r", "r", "r" } },
2133
2134 { -1 },
2135 };
2136
2137 static void tcg_target_init(TCGContext *s)
2138 {
2139 unsigned long hwcap = qemu_getauxval(AT_HWCAP);
2140 if (hwcap & PPC_FEATURE_ARCH_2_06) {
2141 have_isa_2_06 = true;
2142 }
2143
2144 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff);
2145 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff);
2146 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
2147 (1 << TCG_REG_R0) |
2148 (1 << TCG_REG_R2) |
2149 (1 << TCG_REG_R3) |
2150 (1 << TCG_REG_R4) |
2151 (1 << TCG_REG_R5) |
2152 (1 << TCG_REG_R6) |
2153 (1 << TCG_REG_R7) |
2154 (1 << TCG_REG_R8) |
2155 (1 << TCG_REG_R9) |
2156 (1 << TCG_REG_R10) |
2157 (1 << TCG_REG_R11) |
2158 (1 << TCG_REG_R12));
2159
2160 tcg_regset_clear(s->reserved_regs);
2161 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R0); /* tcg temp */
2162 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R1); /* stack pointer */
2163 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R2); /* mem temp */
2164 #ifdef __APPLE__
2165 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R11); /* ??? */
2166 #endif
2167 tcg_regset_set_reg(s->reserved_regs, TCG_REG_R13); /* thread pointer */
2168
2169 tcg_add_target_add_op_defs(ppc_op_defs);
2170 }
2171
2172 typedef struct {
2173 DebugFrameCIE cie;
2174 DebugFrameFDEHeader fde;
2175 uint8_t fde_def_cfa[4];
2176 uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2 + 3];
2177 } DebugFrame;
2178
2179 /* We're expecting a 2 byte uleb128 encoded value. */
2180 QEMU_BUILD_BUG_ON(FRAME_SIZE >= (1 << 14));
2181
2182 #define ELF_HOST_MACHINE EM_PPC64
2183
2184 static DebugFrame debug_frame = {
2185 .cie.len = sizeof(DebugFrameCIE)-4, /* length after .len member */
2186 .cie.id = -1,
2187 .cie.version = 1,
2188 .cie.code_align = 1,
2189 .cie.data_align = (-SZR & 0x7f), /* sleb128 -SZR */
2190 .cie.return_column = 65,
2191
2192 /* Total FDE size does not include the "len" member. */
2193 .fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, fde.cie_offset),
2194
2195 .fde_def_cfa = {
2196 12, TCG_REG_R1, /* DW_CFA_def_cfa r1, ... */
2197 (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */
2198 (FRAME_SIZE >> 7)
2199 },
2200 .fde_reg_ofs = {
2201 /* DW_CFA_offset_extended_sf, lr, LR_OFFSET */
2202 0x11, 65, (LR_OFFSET / -SZR) & 0x7f,
2203 }
2204 };
2205
2206 void tcg_register_jit(void *buf, size_t buf_size)
2207 {
2208 uint8_t *p = &debug_frame.fde_reg_ofs[3];
2209 int i;
2210
2211 for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); ++i, p += 2) {
2212 p[0] = 0x80 + tcg_target_callee_save_regs[i];
2213 p[1] = (FRAME_SIZE - (REG_SAVE_BOT + i * SZR)) / SZR;
2214 }
2215
2216 debug_frame.fde.func_start = (uintptr_t)buf;
2217 debug_frame.fde.func_len = buf_size;
2218
2219 tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame));
2220 }