Merge remote-tracking branch 'remotes/cody/tags/block-pull-request' into staging
[qemu.git] / tcg / tcg-op.h
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "tcg.h"
26 #include "exec/helper-proto.h"
27 #include "exec/helper-gen.h"
28
29 /* Basic output routines. Not for general consumption. */
30
31 void tcg_gen_op1(TCGContext *, TCGOpcode, TCGArg);
32 void tcg_gen_op2(TCGContext *, TCGOpcode, TCGArg, TCGArg);
33 void tcg_gen_op3(TCGContext *, TCGOpcode, TCGArg, TCGArg, TCGArg);
34 void tcg_gen_op4(TCGContext *, TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg);
35 void tcg_gen_op5(TCGContext *, TCGOpcode, TCGArg, TCGArg, TCGArg,
36 TCGArg, TCGArg);
37 void tcg_gen_op6(TCGContext *, TCGOpcode, TCGArg, TCGArg, TCGArg,
38 TCGArg, TCGArg, TCGArg);
39
40
41 static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 a1)
42 {
43 tcg_gen_op1(&tcg_ctx, opc, GET_TCGV_I32(a1));
44 }
45
46 static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 a1)
47 {
48 tcg_gen_op1(&tcg_ctx, opc, GET_TCGV_I64(a1));
49 }
50
51 static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg a1)
52 {
53 tcg_gen_op1(&tcg_ctx, opc, a1);
54 }
55
56 static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2)
57 {
58 tcg_gen_op2(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2));
59 }
60
61 static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2)
62 {
63 tcg_gen_op2(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2));
64 }
65
66 static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 a1, TCGArg a2)
67 {
68 tcg_gen_op2(&tcg_ctx, opc, GET_TCGV_I32(a1), a2);
69 }
70
71 static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 a1, TCGArg a2)
72 {
73 tcg_gen_op2(&tcg_ctx, opc, GET_TCGV_I64(a1), a2);
74 }
75
76 static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg a1, TCGArg a2)
77 {
78 tcg_gen_op2(&tcg_ctx, opc, a1, a2);
79 }
80
81 static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 a1,
82 TCGv_i32 a2, TCGv_i32 a3)
83 {
84 tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I32(a1),
85 GET_TCGV_I32(a2), GET_TCGV_I32(a3));
86 }
87
88 static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 a1,
89 TCGv_i64 a2, TCGv_i64 a3)
90 {
91 tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I64(a1),
92 GET_TCGV_I64(a2), GET_TCGV_I64(a3));
93 }
94
95 static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 a1,
96 TCGv_i32 a2, TCGArg a3)
97 {
98 tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), a3);
99 }
100
101 static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 a1,
102 TCGv_i64 a2, TCGArg a3)
103 {
104 tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), a3);
105 }
106
107 static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val,
108 TCGv_ptr base, TCGArg offset)
109 {
110 tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I32(val), GET_TCGV_PTR(base), offset);
111 }
112
113 static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val,
114 TCGv_ptr base, TCGArg offset)
115 {
116 tcg_gen_op3(&tcg_ctx, opc, GET_TCGV_I64(val), GET_TCGV_PTR(base), offset);
117 }
118
119 static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
120 TCGv_i32 a3, TCGv_i32 a4)
121 {
122 tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
123 GET_TCGV_I32(a3), GET_TCGV_I32(a4));
124 }
125
126 static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
127 TCGv_i64 a3, TCGv_i64 a4)
128 {
129 tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
130 GET_TCGV_I64(a3), GET_TCGV_I64(a4));
131 }
132
133 static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
134 TCGv_i32 a3, TCGArg a4)
135 {
136 tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
137 GET_TCGV_I32(a3), a4);
138 }
139
140 static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
141 TCGv_i64 a3, TCGArg a4)
142 {
143 tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
144 GET_TCGV_I64(a3), a4);
145 }
146
147 static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
148 TCGArg a3, TCGArg a4)
149 {
150 tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2), a3, a4);
151 }
152
153 static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
154 TCGArg a3, TCGArg a4)
155 {
156 tcg_gen_op4(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2), a3, a4);
157 }
158
159 static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
160 TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5)
161 {
162 tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
163 GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5));
164 }
165
166 static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
167 TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5)
168 {
169 tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
170 GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5));
171 }
172
173 static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
174 TCGv_i32 a3, TCGv_i32 a4, TCGArg a5)
175 {
176 tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
177 GET_TCGV_I32(a3), GET_TCGV_I32(a4), a5);
178 }
179
180 static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
181 TCGv_i64 a3, TCGv_i64 a4, TCGArg a5)
182 {
183 tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
184 GET_TCGV_I64(a3), GET_TCGV_I64(a4), a5);
185 }
186
187 static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
188 TCGv_i32 a3, TCGArg a4, TCGArg a5)
189 {
190 tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
191 GET_TCGV_I32(a3), a4, a5);
192 }
193
194 static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
195 TCGv_i64 a3, TCGArg a4, TCGArg a5)
196 {
197 tcg_gen_op5(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
198 GET_TCGV_I64(a3), a4, a5);
199 }
200
201 static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
202 TCGv_i32 a3, TCGv_i32 a4,
203 TCGv_i32 a5, TCGv_i32 a6)
204 {
205 tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
206 GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5),
207 GET_TCGV_I32(a6));
208 }
209
210 static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
211 TCGv_i64 a3, TCGv_i64 a4,
212 TCGv_i64 a5, TCGv_i64 a6)
213 {
214 tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
215 GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5),
216 GET_TCGV_I64(a6));
217 }
218
219 static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
220 TCGv_i32 a3, TCGv_i32 a4,
221 TCGv_i32 a5, TCGArg a6)
222 {
223 tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
224 GET_TCGV_I32(a3), GET_TCGV_I32(a4), GET_TCGV_I32(a5), a6);
225 }
226
227 static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
228 TCGv_i64 a3, TCGv_i64 a4,
229 TCGv_i64 a5, TCGArg a6)
230 {
231 tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
232 GET_TCGV_I64(a3), GET_TCGV_I64(a4), GET_TCGV_I64(a5), a6);
233 }
234
235 static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2,
236 TCGv_i32 a3, TCGv_i32 a4,
237 TCGArg a5, TCGArg a6)
238 {
239 tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I32(a1), GET_TCGV_I32(a2),
240 GET_TCGV_I32(a3), GET_TCGV_I32(a4), a5, a6);
241 }
242
243 static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2,
244 TCGv_i64 a3, TCGv_i64 a4,
245 TCGArg a5, TCGArg a6)
246 {
247 tcg_gen_op6(&tcg_ctx, opc, GET_TCGV_I64(a1), GET_TCGV_I64(a2),
248 GET_TCGV_I64(a3), GET_TCGV_I64(a4), a5, a6);
249 }
250
251
252 /* Generic ops. */
253
254 static inline void gen_set_label(TCGLabel *l)
255 {
256 tcg_gen_op1(&tcg_ctx, INDEX_op_set_label, label_arg(l));
257 }
258
259 static inline void tcg_gen_br(TCGLabel *l)
260 {
261 tcg_gen_op1(&tcg_ctx, INDEX_op_br, label_arg(l));
262 }
263
264 void tcg_gen_mb(TCGBar);
265
266 /* Helper calls. */
267
268 /* 32 bit ops */
269
270 void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
271 void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2);
272 void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
273 void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2);
274 void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
275 void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
276 void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2);
277 void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2);
278 void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2);
279 void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2);
280 void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
281 void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
282 void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
283 void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
284 void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
285 void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
286 void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
287 void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
288 void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
289 void tcg_gen_clz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
290 void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
291 void tcg_gen_clzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2);
292 void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2);
293 void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg);
294 void tcg_gen_ctpop_i32(TCGv_i32 a1, TCGv_i32 a2);
295 void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
296 void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2);
297 void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
298 void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, unsigned arg2);
299 void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2,
300 unsigned int ofs, unsigned int len);
301 void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg,
302 unsigned int ofs, unsigned int len);
303 void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg,
304 unsigned int ofs, unsigned int len);
305 void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg,
306 unsigned int ofs, unsigned int len);
307 void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLabel *);
308 void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *);
309 void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret,
310 TCGv_i32 arg1, TCGv_i32 arg2);
311 void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret,
312 TCGv_i32 arg1, int32_t arg2);
313 void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1,
314 TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2);
315 void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
316 TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh);
317 void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al,
318 TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh);
319 void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
320 void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
321 void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2);
322 void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg);
323 void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg);
324 void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg);
325 void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg);
326 void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg);
327 void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg);
328
329 static inline void tcg_gen_discard_i32(TCGv_i32 arg)
330 {
331 tcg_gen_op1_i32(INDEX_op_discard, arg);
332 }
333
334 static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg)
335 {
336 if (!TCGV_EQUAL_I32(ret, arg)) {
337 tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg);
338 }
339 }
340
341 static inline void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg)
342 {
343 tcg_gen_op2i_i32(INDEX_op_movi_i32, ret, arg);
344 }
345
346 static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2,
347 tcg_target_long offset)
348 {
349 tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset);
350 }
351
352 static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2,
353 tcg_target_long offset)
354 {
355 tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset);
356 }
357
358 static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2,
359 tcg_target_long offset)
360 {
361 tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset);
362 }
363
364 static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2,
365 tcg_target_long offset)
366 {
367 tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset);
368 }
369
370 static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2,
371 tcg_target_long offset)
372 {
373 tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset);
374 }
375
376 static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2,
377 tcg_target_long offset)
378 {
379 tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset);
380 }
381
382 static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2,
383 tcg_target_long offset)
384 {
385 tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset);
386 }
387
388 static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2,
389 tcg_target_long offset)
390 {
391 tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset);
392 }
393
394 static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
395 {
396 tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2);
397 }
398
399 static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
400 {
401 tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2);
402 }
403
404 static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
405 {
406 tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2);
407 }
408
409 static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
410 {
411 tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2);
412 }
413
414 static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
415 {
416 tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2);
417 }
418
419 static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
420 {
421 tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2);
422 }
423
424 static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
425 {
426 tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2);
427 }
428
429 static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
430 {
431 tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2);
432 }
433
434 static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
435 {
436 tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2);
437 }
438
439 static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg)
440 {
441 if (TCG_TARGET_HAS_neg_i32) {
442 tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg);
443 } else {
444 tcg_gen_subfi_i32(ret, 0, arg);
445 }
446 }
447
448 static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg)
449 {
450 if (TCG_TARGET_HAS_not_i32) {
451 tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg);
452 } else {
453 tcg_gen_xori_i32(ret, arg, -1);
454 }
455 }
456
457 /* 64 bit ops */
458
459 void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
460 void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2);
461 void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
462 void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2);
463 void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
464 void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
465 void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2);
466 void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2);
467 void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2);
468 void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2);
469 void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
470 void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
471 void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
472 void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
473 void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
474 void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
475 void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
476 void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
477 void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
478 void tcg_gen_clz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
479 void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
480 void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2);
481 void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2);
482 void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg);
483 void tcg_gen_ctpop_i64(TCGv_i64 a1, TCGv_i64 a2);
484 void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
485 void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2);
486 void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
487 void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, unsigned arg2);
488 void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2,
489 unsigned int ofs, unsigned int len);
490 void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg,
491 unsigned int ofs, unsigned int len);
492 void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg,
493 unsigned int ofs, unsigned int len);
494 void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg,
495 unsigned int ofs, unsigned int len);
496 void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *);
497 void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *);
498 void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret,
499 TCGv_i64 arg1, TCGv_i64 arg2);
500 void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret,
501 TCGv_i64 arg1, int64_t arg2);
502 void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1,
503 TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2);
504 void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
505 TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh);
506 void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al,
507 TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh);
508 void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
509 void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
510 void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2);
511 void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg);
512 void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg);
513 void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg);
514 void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg);
515 void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg);
516 void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg);
517 void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg);
518 void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg);
519 void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg);
520 void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg);
521
522 #if TCG_TARGET_REG_BITS == 64
523 static inline void tcg_gen_discard_i64(TCGv_i64 arg)
524 {
525 tcg_gen_op1_i64(INDEX_op_discard, arg);
526 }
527
528 static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg)
529 {
530 if (!TCGV_EQUAL_I64(ret, arg)) {
531 tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg);
532 }
533 }
534
535 static inline void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg)
536 {
537 tcg_gen_op2i_i64(INDEX_op_movi_i64, ret, arg);
538 }
539
540 static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2,
541 tcg_target_long offset)
542 {
543 tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset);
544 }
545
546 static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2,
547 tcg_target_long offset)
548 {
549 tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset);
550 }
551
552 static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2,
553 tcg_target_long offset)
554 {
555 tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset);
556 }
557
558 static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2,
559 tcg_target_long offset)
560 {
561 tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset);
562 }
563
564 static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2,
565 tcg_target_long offset)
566 {
567 tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset);
568 }
569
570 static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2,
571 tcg_target_long offset)
572 {
573 tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset);
574 }
575
576 static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2,
577 tcg_target_long offset)
578 {
579 tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset);
580 }
581
582 static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
583 tcg_target_long offset)
584 {
585 tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset);
586 }
587
588 static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
589 tcg_target_long offset)
590 {
591 tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset);
592 }
593
594 static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
595 tcg_target_long offset)
596 {
597 tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset);
598 }
599
600 static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2,
601 tcg_target_long offset)
602 {
603 tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset);
604 }
605
606 static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
607 {
608 tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2);
609 }
610
611 static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
612 {
613 tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2);
614 }
615
616 static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
617 {
618 tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2);
619 }
620
621 static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
622 {
623 tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2);
624 }
625
626 static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
627 {
628 tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2);
629 }
630
631 static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
632 {
633 tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2);
634 }
635
636 static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
637 {
638 tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2);
639 }
640
641 static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
642 {
643 tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2);
644 }
645
646 static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
647 {
648 tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2);
649 }
650 #else /* TCG_TARGET_REG_BITS == 32 */
651 static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2,
652 tcg_target_long offset)
653 {
654 tcg_gen_st8_i32(TCGV_LOW(arg1), arg2, offset);
655 }
656
657 static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2,
658 tcg_target_long offset)
659 {
660 tcg_gen_st16_i32(TCGV_LOW(arg1), arg2, offset);
661 }
662
663 static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2,
664 tcg_target_long offset)
665 {
666 tcg_gen_st_i32(TCGV_LOW(arg1), arg2, offset);
667 }
668
669 static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
670 {
671 tcg_gen_add2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1),
672 TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2));
673 }
674
675 static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
676 {
677 tcg_gen_sub2_i32(TCGV_LOW(ret), TCGV_HIGH(ret), TCGV_LOW(arg1),
678 TCGV_HIGH(arg1), TCGV_LOW(arg2), TCGV_HIGH(arg2));
679 }
680
681 void tcg_gen_discard_i64(TCGv_i64 arg);
682 void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg);
683 void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg);
684 void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
685 void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
686 void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
687 void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
688 void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
689 void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
690 void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
691 void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset);
692 void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
693 void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
694 void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
695 void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
696 void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
697 void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
698 void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
699 #endif /* TCG_TARGET_REG_BITS */
700
701 static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg)
702 {
703 if (TCG_TARGET_HAS_neg_i64) {
704 tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg);
705 } else {
706 tcg_gen_subfi_i64(ret, 0, arg);
707 }
708 }
709
710 /* Size changing operations. */
711
712 void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg);
713 void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg);
714 void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high);
715 void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg);
716 void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg);
717 void tcg_gen_extr_i64_i32(TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg);
718 void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg);
719
720 static inline void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i64 hi)
721 {
722 tcg_gen_deposit_i64(ret, lo, hi, 32, 32);
723 }
724
725 /* QEMU specific operations. */
726
727 #ifndef TARGET_LONG_BITS
728 #error must include QEMU headers
729 #endif
730
731 #if TARGET_INSN_START_WORDS == 1
732 # if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
733 static inline void tcg_gen_insn_start(target_ulong pc)
734 {
735 tcg_gen_op1(&tcg_ctx, INDEX_op_insn_start, pc);
736 }
737 # else
738 static inline void tcg_gen_insn_start(target_ulong pc)
739 {
740 tcg_gen_op2(&tcg_ctx, INDEX_op_insn_start,
741 (uint32_t)pc, (uint32_t)(pc >> 32));
742 }
743 # endif
744 #elif TARGET_INSN_START_WORDS == 2
745 # if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
746 static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)
747 {
748 tcg_gen_op2(&tcg_ctx, INDEX_op_insn_start, pc, a1);
749 }
750 # else
751 static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)
752 {
753 tcg_gen_op4(&tcg_ctx, INDEX_op_insn_start,
754 (uint32_t)pc, (uint32_t)(pc >> 32),
755 (uint32_t)a1, (uint32_t)(a1 >> 32));
756 }
757 # endif
758 #elif TARGET_INSN_START_WORDS == 3
759 # if TARGET_LONG_BITS <= TCG_TARGET_REG_BITS
760 static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,
761 target_ulong a2)
762 {
763 tcg_gen_op3(&tcg_ctx, INDEX_op_insn_start, pc, a1, a2);
764 }
765 # else
766 static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,
767 target_ulong a2)
768 {
769 tcg_gen_op6(&tcg_ctx, INDEX_op_insn_start,
770 (uint32_t)pc, (uint32_t)(pc >> 32),
771 (uint32_t)a1, (uint32_t)(a1 >> 32),
772 (uint32_t)a2, (uint32_t)(a2 >> 32));
773 }
774 # endif
775 #else
776 # error "Unhandled number of operands to insn_start"
777 #endif
778
779 static inline void tcg_gen_exit_tb(uintptr_t val)
780 {
781 tcg_gen_op1i(INDEX_op_exit_tb, val);
782 }
783
784 /**
785 * tcg_gen_goto_tb() - output goto_tb TCG operation
786 * @idx: Direct jump slot index (0 or 1)
787 *
788 * See tcg/README for more info about this TCG operation.
789 *
790 * NOTE: In softmmu emulation, direct jumps with goto_tb are only safe within
791 * the pages this TB resides in because we don't take care of direct jumps when
792 * address mapping changes, e.g. in tlb_flush(). In user mode, there's only a
793 * static address translation, so the destination address is always valid, TBs
794 * are always invalidated properly, and direct jumps are reset when mapping
795 * changes.
796 */
797 void tcg_gen_goto_tb(unsigned idx);
798
799 #if TARGET_LONG_BITS == 32
800 #define tcg_temp_new() tcg_temp_new_i32()
801 #define tcg_global_reg_new tcg_global_reg_new_i32
802 #define tcg_global_mem_new tcg_global_mem_new_i32
803 #define tcg_temp_local_new() tcg_temp_local_new_i32()
804 #define tcg_temp_free tcg_temp_free_i32
805 #define TCGV_UNUSED(x) TCGV_UNUSED_I32(x)
806 #define TCGV_IS_UNUSED(x) TCGV_IS_UNUSED_I32(x)
807 #define TCGV_EQUAL(a, b) TCGV_EQUAL_I32(a, b)
808 #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32
809 #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32
810 #else
811 #define tcg_temp_new() tcg_temp_new_i64()
812 #define tcg_global_reg_new tcg_global_reg_new_i64
813 #define tcg_global_mem_new tcg_global_mem_new_i64
814 #define tcg_temp_local_new() tcg_temp_local_new_i64()
815 #define tcg_temp_free tcg_temp_free_i64
816 #define TCGV_UNUSED(x) TCGV_UNUSED_I64(x)
817 #define TCGV_IS_UNUSED(x) TCGV_IS_UNUSED_I64(x)
818 #define TCGV_EQUAL(a, b) TCGV_EQUAL_I64(a, b)
819 #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64
820 #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64
821 #endif
822
823 void tcg_gen_qemu_ld_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp);
824 void tcg_gen_qemu_st_i32(TCGv_i32, TCGv, TCGArg, TCGMemOp);
825 void tcg_gen_qemu_ld_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp);
826 void tcg_gen_qemu_st_i64(TCGv_i64, TCGv, TCGArg, TCGMemOp);
827
828 static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
829 {
830 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_UB);
831 }
832
833 static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
834 {
835 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_SB);
836 }
837
838 static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
839 {
840 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUW);
841 }
842
843 static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
844 {
845 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESW);
846 }
847
848 static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
849 {
850 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TEUL);
851 }
852
853 static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
854 {
855 tcg_gen_qemu_ld_tl(ret, addr, mem_index, MO_TESL);
856 }
857
858 static inline void tcg_gen_qemu_ld64(TCGv_i64 ret, TCGv addr, int mem_index)
859 {
860 tcg_gen_qemu_ld_i64(ret, addr, mem_index, MO_TEQ);
861 }
862
863 static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
864 {
865 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_UB);
866 }
867
868 static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
869 {
870 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUW);
871 }
872
873 static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
874 {
875 tcg_gen_qemu_st_tl(arg, addr, mem_index, MO_TEUL);
876 }
877
878 static inline void tcg_gen_qemu_st64(TCGv_i64 arg, TCGv addr, int mem_index)
879 {
880 tcg_gen_qemu_st_i64(arg, addr, mem_index, MO_TEQ);
881 }
882
883 void tcg_gen_atomic_cmpxchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGv_i32,
884 TCGArg, TCGMemOp);
885 void tcg_gen_atomic_cmpxchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGv_i64,
886 TCGArg, TCGMemOp);
887
888 void tcg_gen_atomic_xchg_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
889 void tcg_gen_atomic_xchg_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
890 void tcg_gen_atomic_fetch_add_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
891 void tcg_gen_atomic_fetch_add_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
892 void tcg_gen_atomic_fetch_and_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
893 void tcg_gen_atomic_fetch_and_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
894 void tcg_gen_atomic_fetch_or_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
895 void tcg_gen_atomic_fetch_or_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
896 void tcg_gen_atomic_fetch_xor_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
897 void tcg_gen_atomic_fetch_xor_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
898 void tcg_gen_atomic_add_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
899 void tcg_gen_atomic_add_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
900 void tcg_gen_atomic_and_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
901 void tcg_gen_atomic_and_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
902 void tcg_gen_atomic_or_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
903 void tcg_gen_atomic_or_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
904 void tcg_gen_atomic_xor_fetch_i32(TCGv_i32, TCGv, TCGv_i32, TCGArg, TCGMemOp);
905 void tcg_gen_atomic_xor_fetch_i64(TCGv_i64, TCGv, TCGv_i64, TCGArg, TCGMemOp);
906
907 #if TARGET_LONG_BITS == 64
908 #define tcg_gen_movi_tl tcg_gen_movi_i64
909 #define tcg_gen_mov_tl tcg_gen_mov_i64
910 #define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
911 #define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
912 #define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
913 #define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
914 #define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
915 #define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
916 #define tcg_gen_ld_tl tcg_gen_ld_i64
917 #define tcg_gen_st8_tl tcg_gen_st8_i64
918 #define tcg_gen_st16_tl tcg_gen_st16_i64
919 #define tcg_gen_st32_tl tcg_gen_st32_i64
920 #define tcg_gen_st_tl tcg_gen_st_i64
921 #define tcg_gen_add_tl tcg_gen_add_i64
922 #define tcg_gen_addi_tl tcg_gen_addi_i64
923 #define tcg_gen_sub_tl tcg_gen_sub_i64
924 #define tcg_gen_neg_tl tcg_gen_neg_i64
925 #define tcg_gen_subfi_tl tcg_gen_subfi_i64
926 #define tcg_gen_subi_tl tcg_gen_subi_i64
927 #define tcg_gen_and_tl tcg_gen_and_i64
928 #define tcg_gen_andi_tl tcg_gen_andi_i64
929 #define tcg_gen_or_tl tcg_gen_or_i64
930 #define tcg_gen_ori_tl tcg_gen_ori_i64
931 #define tcg_gen_xor_tl tcg_gen_xor_i64
932 #define tcg_gen_xori_tl tcg_gen_xori_i64
933 #define tcg_gen_not_tl tcg_gen_not_i64
934 #define tcg_gen_shl_tl tcg_gen_shl_i64
935 #define tcg_gen_shli_tl tcg_gen_shli_i64
936 #define tcg_gen_shr_tl tcg_gen_shr_i64
937 #define tcg_gen_shri_tl tcg_gen_shri_i64
938 #define tcg_gen_sar_tl tcg_gen_sar_i64
939 #define tcg_gen_sari_tl tcg_gen_sari_i64
940 #define tcg_gen_brcond_tl tcg_gen_brcond_i64
941 #define tcg_gen_brcondi_tl tcg_gen_brcondi_i64
942 #define tcg_gen_setcond_tl tcg_gen_setcond_i64
943 #define tcg_gen_setcondi_tl tcg_gen_setcondi_i64
944 #define tcg_gen_mul_tl tcg_gen_mul_i64
945 #define tcg_gen_muli_tl tcg_gen_muli_i64
946 #define tcg_gen_div_tl tcg_gen_div_i64
947 #define tcg_gen_rem_tl tcg_gen_rem_i64
948 #define tcg_gen_divu_tl tcg_gen_divu_i64
949 #define tcg_gen_remu_tl tcg_gen_remu_i64
950 #define tcg_gen_discard_tl tcg_gen_discard_i64
951 #define tcg_gen_trunc_tl_i32 tcg_gen_extrl_i64_i32
952 #define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
953 #define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
954 #define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
955 #define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
956 #define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
957 #define tcg_gen_ext8u_tl tcg_gen_ext8u_i64
958 #define tcg_gen_ext8s_tl tcg_gen_ext8s_i64
959 #define tcg_gen_ext16u_tl tcg_gen_ext16u_i64
960 #define tcg_gen_ext16s_tl tcg_gen_ext16s_i64
961 #define tcg_gen_ext32u_tl tcg_gen_ext32u_i64
962 #define tcg_gen_ext32s_tl tcg_gen_ext32s_i64
963 #define tcg_gen_bswap16_tl tcg_gen_bswap16_i64
964 #define tcg_gen_bswap32_tl tcg_gen_bswap32_i64
965 #define tcg_gen_bswap64_tl tcg_gen_bswap64_i64
966 #define tcg_gen_concat_tl_i64 tcg_gen_concat32_i64
967 #define tcg_gen_extr_i64_tl tcg_gen_extr32_i64
968 #define tcg_gen_andc_tl tcg_gen_andc_i64
969 #define tcg_gen_eqv_tl tcg_gen_eqv_i64
970 #define tcg_gen_nand_tl tcg_gen_nand_i64
971 #define tcg_gen_nor_tl tcg_gen_nor_i64
972 #define tcg_gen_orc_tl tcg_gen_orc_i64
973 #define tcg_gen_clz_tl tcg_gen_clz_i64
974 #define tcg_gen_ctz_tl tcg_gen_ctz_i64
975 #define tcg_gen_clzi_tl tcg_gen_clzi_i64
976 #define tcg_gen_ctzi_tl tcg_gen_ctzi_i64
977 #define tcg_gen_clrsb_tl tcg_gen_clrsb_i64
978 #define tcg_gen_ctpop_tl tcg_gen_ctpop_i64
979 #define tcg_gen_rotl_tl tcg_gen_rotl_i64
980 #define tcg_gen_rotli_tl tcg_gen_rotli_i64
981 #define tcg_gen_rotr_tl tcg_gen_rotr_i64
982 #define tcg_gen_rotri_tl tcg_gen_rotri_i64
983 #define tcg_gen_deposit_tl tcg_gen_deposit_i64
984 #define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i64
985 #define tcg_gen_extract_tl tcg_gen_extract_i64
986 #define tcg_gen_sextract_tl tcg_gen_sextract_i64
987 #define tcg_const_tl tcg_const_i64
988 #define tcg_const_local_tl tcg_const_local_i64
989 #define tcg_gen_movcond_tl tcg_gen_movcond_i64
990 #define tcg_gen_add2_tl tcg_gen_add2_i64
991 #define tcg_gen_sub2_tl tcg_gen_sub2_i64
992 #define tcg_gen_mulu2_tl tcg_gen_mulu2_i64
993 #define tcg_gen_muls2_tl tcg_gen_muls2_i64
994 #define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i64
995 #define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i64
996 #define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i64
997 #define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i64
998 #define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i64
999 #define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i64
1000 #define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i64
1001 #define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i64
1002 #define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i64
1003 #define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i64
1004 #define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i64
1005 #else
1006 #define tcg_gen_movi_tl tcg_gen_movi_i32
1007 #define tcg_gen_mov_tl tcg_gen_mov_i32
1008 #define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
1009 #define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
1010 #define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
1011 #define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
1012 #define tcg_gen_ld32u_tl tcg_gen_ld_i32
1013 #define tcg_gen_ld32s_tl tcg_gen_ld_i32
1014 #define tcg_gen_ld_tl tcg_gen_ld_i32
1015 #define tcg_gen_st8_tl tcg_gen_st8_i32
1016 #define tcg_gen_st16_tl tcg_gen_st16_i32
1017 #define tcg_gen_st32_tl tcg_gen_st_i32
1018 #define tcg_gen_st_tl tcg_gen_st_i32
1019 #define tcg_gen_add_tl tcg_gen_add_i32
1020 #define tcg_gen_addi_tl tcg_gen_addi_i32
1021 #define tcg_gen_sub_tl tcg_gen_sub_i32
1022 #define tcg_gen_neg_tl tcg_gen_neg_i32
1023 #define tcg_gen_subfi_tl tcg_gen_subfi_i32
1024 #define tcg_gen_subi_tl tcg_gen_subi_i32
1025 #define tcg_gen_and_tl tcg_gen_and_i32
1026 #define tcg_gen_andi_tl tcg_gen_andi_i32
1027 #define tcg_gen_or_tl tcg_gen_or_i32
1028 #define tcg_gen_ori_tl tcg_gen_ori_i32
1029 #define tcg_gen_xor_tl tcg_gen_xor_i32
1030 #define tcg_gen_xori_tl tcg_gen_xori_i32
1031 #define tcg_gen_not_tl tcg_gen_not_i32
1032 #define tcg_gen_shl_tl tcg_gen_shl_i32
1033 #define tcg_gen_shli_tl tcg_gen_shli_i32
1034 #define tcg_gen_shr_tl tcg_gen_shr_i32
1035 #define tcg_gen_shri_tl tcg_gen_shri_i32
1036 #define tcg_gen_sar_tl tcg_gen_sar_i32
1037 #define tcg_gen_sari_tl tcg_gen_sari_i32
1038 #define tcg_gen_brcond_tl tcg_gen_brcond_i32
1039 #define tcg_gen_brcondi_tl tcg_gen_brcondi_i32
1040 #define tcg_gen_setcond_tl tcg_gen_setcond_i32
1041 #define tcg_gen_setcondi_tl tcg_gen_setcondi_i32
1042 #define tcg_gen_mul_tl tcg_gen_mul_i32
1043 #define tcg_gen_muli_tl tcg_gen_muli_i32
1044 #define tcg_gen_div_tl tcg_gen_div_i32
1045 #define tcg_gen_rem_tl tcg_gen_rem_i32
1046 #define tcg_gen_divu_tl tcg_gen_divu_i32
1047 #define tcg_gen_remu_tl tcg_gen_remu_i32
1048 #define tcg_gen_discard_tl tcg_gen_discard_i32
1049 #define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
1050 #define tcg_gen_trunc_i64_tl tcg_gen_extrl_i64_i32
1051 #define tcg_gen_extu_i32_tl tcg_gen_mov_i32
1052 #define tcg_gen_ext_i32_tl tcg_gen_mov_i32
1053 #define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
1054 #define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
1055 #define tcg_gen_ext8u_tl tcg_gen_ext8u_i32
1056 #define tcg_gen_ext8s_tl tcg_gen_ext8s_i32
1057 #define tcg_gen_ext16u_tl tcg_gen_ext16u_i32
1058 #define tcg_gen_ext16s_tl tcg_gen_ext16s_i32
1059 #define tcg_gen_ext32u_tl tcg_gen_mov_i32
1060 #define tcg_gen_ext32s_tl tcg_gen_mov_i32
1061 #define tcg_gen_bswap16_tl tcg_gen_bswap16_i32
1062 #define tcg_gen_bswap32_tl tcg_gen_bswap32_i32
1063 #define tcg_gen_concat_tl_i64 tcg_gen_concat_i32_i64
1064 #define tcg_gen_extr_i64_tl tcg_gen_extr_i64_i32
1065 #define tcg_gen_andc_tl tcg_gen_andc_i32
1066 #define tcg_gen_eqv_tl tcg_gen_eqv_i32
1067 #define tcg_gen_nand_tl tcg_gen_nand_i32
1068 #define tcg_gen_nor_tl tcg_gen_nor_i32
1069 #define tcg_gen_orc_tl tcg_gen_orc_i32
1070 #define tcg_gen_clz_tl tcg_gen_clz_i32
1071 #define tcg_gen_ctz_tl tcg_gen_ctz_i32
1072 #define tcg_gen_clzi_tl tcg_gen_clzi_i32
1073 #define tcg_gen_ctzi_tl tcg_gen_ctzi_i32
1074 #define tcg_gen_clrsb_tl tcg_gen_clrsb_i32
1075 #define tcg_gen_ctpop_tl tcg_gen_ctpop_i32
1076 #define tcg_gen_rotl_tl tcg_gen_rotl_i32
1077 #define tcg_gen_rotli_tl tcg_gen_rotli_i32
1078 #define tcg_gen_rotr_tl tcg_gen_rotr_i32
1079 #define tcg_gen_rotri_tl tcg_gen_rotri_i32
1080 #define tcg_gen_deposit_tl tcg_gen_deposit_i32
1081 #define tcg_gen_deposit_z_tl tcg_gen_deposit_z_i32
1082 #define tcg_gen_extract_tl tcg_gen_extract_i32
1083 #define tcg_gen_sextract_tl tcg_gen_sextract_i32
1084 #define tcg_const_tl tcg_const_i32
1085 #define tcg_const_local_tl tcg_const_local_i32
1086 #define tcg_gen_movcond_tl tcg_gen_movcond_i32
1087 #define tcg_gen_add2_tl tcg_gen_add2_i32
1088 #define tcg_gen_sub2_tl tcg_gen_sub2_i32
1089 #define tcg_gen_mulu2_tl tcg_gen_mulu2_i32
1090 #define tcg_gen_muls2_tl tcg_gen_muls2_i32
1091 #define tcg_gen_mulsu2_tl tcg_gen_mulsu2_i32
1092 #define tcg_gen_atomic_cmpxchg_tl tcg_gen_atomic_cmpxchg_i32
1093 #define tcg_gen_atomic_xchg_tl tcg_gen_atomic_xchg_i32
1094 #define tcg_gen_atomic_fetch_add_tl tcg_gen_atomic_fetch_add_i32
1095 #define tcg_gen_atomic_fetch_and_tl tcg_gen_atomic_fetch_and_i32
1096 #define tcg_gen_atomic_fetch_or_tl tcg_gen_atomic_fetch_or_i32
1097 #define tcg_gen_atomic_fetch_xor_tl tcg_gen_atomic_fetch_xor_i32
1098 #define tcg_gen_atomic_add_fetch_tl tcg_gen_atomic_add_fetch_i32
1099 #define tcg_gen_atomic_and_fetch_tl tcg_gen_atomic_and_fetch_i32
1100 #define tcg_gen_atomic_or_fetch_tl tcg_gen_atomic_or_fetch_i32
1101 #define tcg_gen_atomic_xor_fetch_tl tcg_gen_atomic_xor_fetch_i32
1102 #endif
1103
1104 #if UINTPTR_MAX == UINT32_MAX
1105 # define tcg_gen_ld_ptr(R, A, O) \
1106 tcg_gen_ld_i32(TCGV_PTR_TO_NAT(R), (A), (O))
1107 # define tcg_gen_discard_ptr(A) \
1108 tcg_gen_discard_i32(TCGV_PTR_TO_NAT(A))
1109 # define tcg_gen_add_ptr(R, A, B) \
1110 tcg_gen_add_i32(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), TCGV_PTR_TO_NAT(B))
1111 # define tcg_gen_addi_ptr(R, A, B) \
1112 tcg_gen_addi_i32(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), (B))
1113 # define tcg_gen_ext_i32_ptr(R, A) \
1114 tcg_gen_mov_i32(TCGV_PTR_TO_NAT(R), (A))
1115 #else
1116 # define tcg_gen_ld_ptr(R, A, O) \
1117 tcg_gen_ld_i64(TCGV_PTR_TO_NAT(R), (A), (O))
1118 # define tcg_gen_discard_ptr(A) \
1119 tcg_gen_discard_i64(TCGV_PTR_TO_NAT(A))
1120 # define tcg_gen_add_ptr(R, A, B) \
1121 tcg_gen_add_i64(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), TCGV_PTR_TO_NAT(B))
1122 # define tcg_gen_addi_ptr(R, A, B) \
1123 tcg_gen_addi_i64(TCGV_PTR_TO_NAT(R), TCGV_PTR_TO_NAT(A), (B))
1124 # define tcg_gen_ext_i32_ptr(R, A) \
1125 tcg_gen_ext_i32_i64(TCGV_PTR_TO_NAT(R), (A))
1126 #endif /* UINTPTR_MAX == UINT32_MAX */