migration: convert unix socket protocol to use QIOChannel
[qemu.git] / tcg / tcg.h
1 /*
2 * Tiny Code Generator for QEMU
3 *
4 * Copyright (c) 2008 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #ifndef TCG_H
26 #define TCG_H
27
28 #include "qemu-common.h"
29 #include "cpu.h"
30 #include "exec/tb-context.h"
31 #include "qemu/bitops.h"
32 #include "tcg-target.h"
33
34 /* XXX: make safe guess about sizes */
35 #define MAX_OP_PER_INSTR 266
36
37 #if HOST_LONG_BITS == 32
38 #define MAX_OPC_PARAM_PER_ARG 2
39 #else
40 #define MAX_OPC_PARAM_PER_ARG 1
41 #endif
42 #define MAX_OPC_PARAM_IARGS 5
43 #define MAX_OPC_PARAM_OARGS 1
44 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
45
46 /* A Call op needs up to 4 + 2N parameters on 32-bit archs,
47 * and up to 4 + N parameters on 64-bit archs
48 * (N = number of input arguments + output arguments). */
49 #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
50 #define OPC_BUF_SIZE 640
51 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
52
53 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
54
55 #define CPU_TEMP_BUF_NLONGS 128
56
57 /* Default target word size to pointer size. */
58 #ifndef TCG_TARGET_REG_BITS
59 # if UINTPTR_MAX == UINT32_MAX
60 # define TCG_TARGET_REG_BITS 32
61 # elif UINTPTR_MAX == UINT64_MAX
62 # define TCG_TARGET_REG_BITS 64
63 # else
64 # error Unknown pointer size for tcg target
65 # endif
66 #endif
67
68 #if TCG_TARGET_REG_BITS == 32
69 typedef int32_t tcg_target_long;
70 typedef uint32_t tcg_target_ulong;
71 #define TCG_PRIlx PRIx32
72 #define TCG_PRIld PRId32
73 #elif TCG_TARGET_REG_BITS == 64
74 typedef int64_t tcg_target_long;
75 typedef uint64_t tcg_target_ulong;
76 #define TCG_PRIlx PRIx64
77 #define TCG_PRIld PRId64
78 #else
79 #error unsupported
80 #endif
81
82 #if TCG_TARGET_NB_REGS <= 32
83 typedef uint32_t TCGRegSet;
84 #elif TCG_TARGET_NB_REGS <= 64
85 typedef uint64_t TCGRegSet;
86 #else
87 #error unsupported
88 #endif
89
90 #if TCG_TARGET_REG_BITS == 32
91 /* Turn some undef macros into false macros. */
92 #define TCG_TARGET_HAS_extrl_i64_i32 0
93 #define TCG_TARGET_HAS_extrh_i64_i32 0
94 #define TCG_TARGET_HAS_div_i64 0
95 #define TCG_TARGET_HAS_rem_i64 0
96 #define TCG_TARGET_HAS_div2_i64 0
97 #define TCG_TARGET_HAS_rot_i64 0
98 #define TCG_TARGET_HAS_ext8s_i64 0
99 #define TCG_TARGET_HAS_ext16s_i64 0
100 #define TCG_TARGET_HAS_ext32s_i64 0
101 #define TCG_TARGET_HAS_ext8u_i64 0
102 #define TCG_TARGET_HAS_ext16u_i64 0
103 #define TCG_TARGET_HAS_ext32u_i64 0
104 #define TCG_TARGET_HAS_bswap16_i64 0
105 #define TCG_TARGET_HAS_bswap32_i64 0
106 #define TCG_TARGET_HAS_bswap64_i64 0
107 #define TCG_TARGET_HAS_neg_i64 0
108 #define TCG_TARGET_HAS_not_i64 0
109 #define TCG_TARGET_HAS_andc_i64 0
110 #define TCG_TARGET_HAS_orc_i64 0
111 #define TCG_TARGET_HAS_eqv_i64 0
112 #define TCG_TARGET_HAS_nand_i64 0
113 #define TCG_TARGET_HAS_nor_i64 0
114 #define TCG_TARGET_HAS_deposit_i64 0
115 #define TCG_TARGET_HAS_movcond_i64 0
116 #define TCG_TARGET_HAS_add2_i64 0
117 #define TCG_TARGET_HAS_sub2_i64 0
118 #define TCG_TARGET_HAS_mulu2_i64 0
119 #define TCG_TARGET_HAS_muls2_i64 0
120 #define TCG_TARGET_HAS_muluh_i64 0
121 #define TCG_TARGET_HAS_mulsh_i64 0
122 /* Turn some undef macros into true macros. */
123 #define TCG_TARGET_HAS_add2_i32 1
124 #define TCG_TARGET_HAS_sub2_i32 1
125 #endif
126
127 #ifndef TCG_TARGET_deposit_i32_valid
128 #define TCG_TARGET_deposit_i32_valid(ofs, len) 1
129 #endif
130 #ifndef TCG_TARGET_deposit_i64_valid
131 #define TCG_TARGET_deposit_i64_valid(ofs, len) 1
132 #endif
133
134 /* Only one of DIV or DIV2 should be defined. */
135 #if defined(TCG_TARGET_HAS_div_i32)
136 #define TCG_TARGET_HAS_div2_i32 0
137 #elif defined(TCG_TARGET_HAS_div2_i32)
138 #define TCG_TARGET_HAS_div_i32 0
139 #define TCG_TARGET_HAS_rem_i32 0
140 #endif
141 #if defined(TCG_TARGET_HAS_div_i64)
142 #define TCG_TARGET_HAS_div2_i64 0
143 #elif defined(TCG_TARGET_HAS_div2_i64)
144 #define TCG_TARGET_HAS_div_i64 0
145 #define TCG_TARGET_HAS_rem_i64 0
146 #endif
147
148 /* For 32-bit targets, some sort of unsigned widening multiply is required. */
149 #if TCG_TARGET_REG_BITS == 32 \
150 && !(defined(TCG_TARGET_HAS_mulu2_i32) \
151 || defined(TCG_TARGET_HAS_muluh_i32))
152 # error "Missing unsigned widening multiply"
153 #endif
154
155 #ifndef TARGET_INSN_START_EXTRA_WORDS
156 # define TARGET_INSN_START_WORDS 1
157 #else
158 # define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS)
159 #endif
160
161 typedef enum TCGOpcode {
162 #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name,
163 #include "tcg-opc.h"
164 #undef DEF
165 NB_OPS,
166 } TCGOpcode;
167
168 #define tcg_regset_clear(d) (d) = 0
169 #define tcg_regset_set(d, s) (d) = (s)
170 #define tcg_regset_set32(d, reg, val32) (d) |= (val32) << (reg)
171 #define tcg_regset_set_reg(d, r) (d) |= 1L << (r)
172 #define tcg_regset_reset_reg(d, r) (d) &= ~(1L << (r))
173 #define tcg_regset_test_reg(d, r) (((d) >> (r)) & 1)
174 #define tcg_regset_or(d, a, b) (d) = (a) | (b)
175 #define tcg_regset_and(d, a, b) (d) = (a) & (b)
176 #define tcg_regset_andnot(d, a, b) (d) = (a) & ~(b)
177 #define tcg_regset_not(d, a) (d) = ~(a)
178
179 #ifndef TCG_TARGET_INSN_UNIT_SIZE
180 # error "Missing TCG_TARGET_INSN_UNIT_SIZE"
181 #elif TCG_TARGET_INSN_UNIT_SIZE == 1
182 typedef uint8_t tcg_insn_unit;
183 #elif TCG_TARGET_INSN_UNIT_SIZE == 2
184 typedef uint16_t tcg_insn_unit;
185 #elif TCG_TARGET_INSN_UNIT_SIZE == 4
186 typedef uint32_t tcg_insn_unit;
187 #elif TCG_TARGET_INSN_UNIT_SIZE == 8
188 typedef uint64_t tcg_insn_unit;
189 #else
190 /* The port better have done this. */
191 #endif
192
193
194 typedef struct TCGRelocation {
195 struct TCGRelocation *next;
196 int type;
197 tcg_insn_unit *ptr;
198 intptr_t addend;
199 } TCGRelocation;
200
201 typedef struct TCGLabel {
202 unsigned has_value : 1;
203 unsigned id : 31;
204 union {
205 uintptr_t value;
206 tcg_insn_unit *value_ptr;
207 TCGRelocation *first_reloc;
208 } u;
209 } TCGLabel;
210
211 typedef struct TCGPool {
212 struct TCGPool *next;
213 int size;
214 uint8_t data[0] __attribute__ ((aligned));
215 } TCGPool;
216
217 #define TCG_POOL_CHUNK_SIZE 32768
218
219 #define TCG_MAX_TEMPS 512
220 #define TCG_MAX_INSNS 512
221
222 /* when the size of the arguments of a called function is smaller than
223 this value, they are statically allocated in the TB stack frame */
224 #define TCG_STATIC_CALL_ARGS_SIZE 128
225
226 typedef enum TCGType {
227 TCG_TYPE_I32,
228 TCG_TYPE_I64,
229 TCG_TYPE_COUNT, /* number of different types */
230
231 /* An alias for the size of the host register. */
232 #if TCG_TARGET_REG_BITS == 32
233 TCG_TYPE_REG = TCG_TYPE_I32,
234 #else
235 TCG_TYPE_REG = TCG_TYPE_I64,
236 #endif
237
238 /* An alias for the size of the native pointer. */
239 #if UINTPTR_MAX == UINT32_MAX
240 TCG_TYPE_PTR = TCG_TYPE_I32,
241 #else
242 TCG_TYPE_PTR = TCG_TYPE_I64,
243 #endif
244
245 /* An alias for the size of the target "long", aka register. */
246 #if TARGET_LONG_BITS == 64
247 TCG_TYPE_TL = TCG_TYPE_I64,
248 #else
249 TCG_TYPE_TL = TCG_TYPE_I32,
250 #endif
251 } TCGType;
252
253 /* Constants for qemu_ld and qemu_st for the Memory Operation field. */
254 typedef enum TCGMemOp {
255 MO_8 = 0,
256 MO_16 = 1,
257 MO_32 = 2,
258 MO_64 = 3,
259 MO_SIZE = 3, /* Mask for the above. */
260
261 MO_SIGN = 4, /* Sign-extended, otherwise zero-extended. */
262
263 MO_BSWAP = 8, /* Host reverse endian. */
264 #ifdef HOST_WORDS_BIGENDIAN
265 MO_LE = MO_BSWAP,
266 MO_BE = 0,
267 #else
268 MO_LE = 0,
269 MO_BE = MO_BSWAP,
270 #endif
271 #ifdef TARGET_WORDS_BIGENDIAN
272 MO_TE = MO_BE,
273 #else
274 MO_TE = MO_LE,
275 #endif
276
277 /* MO_UNALN accesses are never checked for alignment.
278 MO_ALIGN accesses will result in a call to the CPU's
279 do_unaligned_access hook if the guest address is not aligned.
280 The default depends on whether the target CPU defines ALIGNED_ONLY. */
281 MO_AMASK = 16,
282 #ifdef ALIGNED_ONLY
283 MO_ALIGN = 0,
284 MO_UNALN = MO_AMASK,
285 #else
286 MO_ALIGN = MO_AMASK,
287 MO_UNALN = 0,
288 #endif
289
290 /* Combinations of the above, for ease of use. */
291 MO_UB = MO_8,
292 MO_UW = MO_16,
293 MO_UL = MO_32,
294 MO_SB = MO_SIGN | MO_8,
295 MO_SW = MO_SIGN | MO_16,
296 MO_SL = MO_SIGN | MO_32,
297 MO_Q = MO_64,
298
299 MO_LEUW = MO_LE | MO_UW,
300 MO_LEUL = MO_LE | MO_UL,
301 MO_LESW = MO_LE | MO_SW,
302 MO_LESL = MO_LE | MO_SL,
303 MO_LEQ = MO_LE | MO_Q,
304
305 MO_BEUW = MO_BE | MO_UW,
306 MO_BEUL = MO_BE | MO_UL,
307 MO_BESW = MO_BE | MO_SW,
308 MO_BESL = MO_BE | MO_SL,
309 MO_BEQ = MO_BE | MO_Q,
310
311 MO_TEUW = MO_TE | MO_UW,
312 MO_TEUL = MO_TE | MO_UL,
313 MO_TESW = MO_TE | MO_SW,
314 MO_TESL = MO_TE | MO_SL,
315 MO_TEQ = MO_TE | MO_Q,
316
317 MO_SSIZE = MO_SIZE | MO_SIGN,
318 } TCGMemOp;
319
320 typedef tcg_target_ulong TCGArg;
321
322 /* Define a type and accessor macros for variables. Using pointer types
323 is nice because it gives some level of type safely. Converting to and
324 from intptr_t rather than int reduces the number of sign-extension
325 instructions that get implied on 64-bit hosts. Users of tcg_gen_* don't
326 need to know about any of this, and should treat TCGv as an opaque type.
327 In addition we do typechecking for different types of variables. TCGv_i32
328 and TCGv_i64 are 32/64-bit variables respectively. TCGv and TCGv_ptr
329 are aliases for target_ulong and host pointer sized values respectively. */
330
331 typedef struct TCGv_i32_d *TCGv_i32;
332 typedef struct TCGv_i64_d *TCGv_i64;
333 typedef struct TCGv_ptr_d *TCGv_ptr;
334 typedef TCGv_ptr TCGv_env;
335 #if TARGET_LONG_BITS == 32
336 #define TCGv TCGv_i32
337 #elif TARGET_LONG_BITS == 64
338 #define TCGv TCGv_i64
339 #else
340 #error Unhandled TARGET_LONG_BITS value
341 #endif
342
343 static inline TCGv_i32 QEMU_ARTIFICIAL MAKE_TCGV_I32(intptr_t i)
344 {
345 return (TCGv_i32)i;
346 }
347
348 static inline TCGv_i64 QEMU_ARTIFICIAL MAKE_TCGV_I64(intptr_t i)
349 {
350 return (TCGv_i64)i;
351 }
352
353 static inline TCGv_ptr QEMU_ARTIFICIAL MAKE_TCGV_PTR(intptr_t i)
354 {
355 return (TCGv_ptr)i;
356 }
357
358 static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_I32(TCGv_i32 t)
359 {
360 return (intptr_t)t;
361 }
362
363 static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_I64(TCGv_i64 t)
364 {
365 return (intptr_t)t;
366 }
367
368 static inline intptr_t QEMU_ARTIFICIAL GET_TCGV_PTR(TCGv_ptr t)
369 {
370 return (intptr_t)t;
371 }
372
373 #if TCG_TARGET_REG_BITS == 32
374 #define TCGV_LOW(t) MAKE_TCGV_I32(GET_TCGV_I64(t))
375 #define TCGV_HIGH(t) MAKE_TCGV_I32(GET_TCGV_I64(t) + 1)
376 #endif
377
378 #define TCGV_EQUAL_I32(a, b) (GET_TCGV_I32(a) == GET_TCGV_I32(b))
379 #define TCGV_EQUAL_I64(a, b) (GET_TCGV_I64(a) == GET_TCGV_I64(b))
380 #define TCGV_EQUAL_PTR(a, b) (GET_TCGV_PTR(a) == GET_TCGV_PTR(b))
381
382 /* Dummy definition to avoid compiler warnings. */
383 #define TCGV_UNUSED_I32(x) x = MAKE_TCGV_I32(-1)
384 #define TCGV_UNUSED_I64(x) x = MAKE_TCGV_I64(-1)
385 #define TCGV_UNUSED_PTR(x) x = MAKE_TCGV_PTR(-1)
386
387 #define TCGV_IS_UNUSED_I32(x) (GET_TCGV_I32(x) == -1)
388 #define TCGV_IS_UNUSED_I64(x) (GET_TCGV_I64(x) == -1)
389 #define TCGV_IS_UNUSED_PTR(x) (GET_TCGV_PTR(x) == -1)
390
391 /* call flags */
392 /* Helper does not read globals (either directly or through an exception). It
393 implies TCG_CALL_NO_WRITE_GLOBALS. */
394 #define TCG_CALL_NO_READ_GLOBALS 0x0010
395 /* Helper does not write globals */
396 #define TCG_CALL_NO_WRITE_GLOBALS 0x0020
397 /* Helper can be safely suppressed if the return value is not used. */
398 #define TCG_CALL_NO_SIDE_EFFECTS 0x0040
399
400 /* convenience version of most used call flags */
401 #define TCG_CALL_NO_RWG TCG_CALL_NO_READ_GLOBALS
402 #define TCG_CALL_NO_WG TCG_CALL_NO_WRITE_GLOBALS
403 #define TCG_CALL_NO_SE TCG_CALL_NO_SIDE_EFFECTS
404 #define TCG_CALL_NO_RWG_SE (TCG_CALL_NO_RWG | TCG_CALL_NO_SE)
405 #define TCG_CALL_NO_WG_SE (TCG_CALL_NO_WG | TCG_CALL_NO_SE)
406
407 /* used to align parameters */
408 #define TCG_CALL_DUMMY_TCGV MAKE_TCGV_I32(-1)
409 #define TCG_CALL_DUMMY_ARG ((TCGArg)(-1))
410
411 /* Conditions. Note that these are laid out for easy manipulation by
412 the functions below:
413 bit 0 is used for inverting;
414 bit 1 is signed,
415 bit 2 is unsigned,
416 bit 3 is used with bit 0 for swapping signed/unsigned. */
417 typedef enum {
418 /* non-signed */
419 TCG_COND_NEVER = 0 | 0 | 0 | 0,
420 TCG_COND_ALWAYS = 0 | 0 | 0 | 1,
421 TCG_COND_EQ = 8 | 0 | 0 | 0,
422 TCG_COND_NE = 8 | 0 | 0 | 1,
423 /* signed */
424 TCG_COND_LT = 0 | 0 | 2 | 0,
425 TCG_COND_GE = 0 | 0 | 2 | 1,
426 TCG_COND_LE = 8 | 0 | 2 | 0,
427 TCG_COND_GT = 8 | 0 | 2 | 1,
428 /* unsigned */
429 TCG_COND_LTU = 0 | 4 | 0 | 0,
430 TCG_COND_GEU = 0 | 4 | 0 | 1,
431 TCG_COND_LEU = 8 | 4 | 0 | 0,
432 TCG_COND_GTU = 8 | 4 | 0 | 1,
433 } TCGCond;
434
435 /* Invert the sense of the comparison. */
436 static inline TCGCond tcg_invert_cond(TCGCond c)
437 {
438 return (TCGCond)(c ^ 1);
439 }
440
441 /* Swap the operands in a comparison. */
442 static inline TCGCond tcg_swap_cond(TCGCond c)
443 {
444 return c & 6 ? (TCGCond)(c ^ 9) : c;
445 }
446
447 /* Create an "unsigned" version of a "signed" comparison. */
448 static inline TCGCond tcg_unsigned_cond(TCGCond c)
449 {
450 return c & 2 ? (TCGCond)(c ^ 6) : c;
451 }
452
453 /* Must a comparison be considered unsigned? */
454 static inline bool is_unsigned_cond(TCGCond c)
455 {
456 return (c & 4) != 0;
457 }
458
459 /* Create a "high" version of a double-word comparison.
460 This removes equality from a LTE or GTE comparison. */
461 static inline TCGCond tcg_high_cond(TCGCond c)
462 {
463 switch (c) {
464 case TCG_COND_GE:
465 case TCG_COND_LE:
466 case TCG_COND_GEU:
467 case TCG_COND_LEU:
468 return (TCGCond)(c ^ 8);
469 default:
470 return c;
471 }
472 }
473
474 typedef enum TCGTempVal {
475 TEMP_VAL_DEAD,
476 TEMP_VAL_REG,
477 TEMP_VAL_MEM,
478 TEMP_VAL_CONST,
479 } TCGTempVal;
480
481 typedef struct TCGTemp {
482 TCGReg reg:8;
483 TCGTempVal val_type:8;
484 TCGType base_type:8;
485 TCGType type:8;
486 unsigned int fixed_reg:1;
487 unsigned int indirect_reg:1;
488 unsigned int indirect_base:1;
489 unsigned int mem_coherent:1;
490 unsigned int mem_allocated:1;
491 unsigned int temp_local:1; /* If true, the temp is saved across
492 basic blocks. Otherwise, it is not
493 preserved across basic blocks. */
494 unsigned int temp_allocated:1; /* never used for code gen */
495
496 tcg_target_long val;
497 struct TCGTemp *mem_base;
498 intptr_t mem_offset;
499 const char *name;
500 } TCGTemp;
501
502 typedef struct TCGContext TCGContext;
503
504 typedef struct TCGTempSet {
505 unsigned long l[BITS_TO_LONGS(TCG_MAX_TEMPS)];
506 } TCGTempSet;
507
508 typedef struct TCGOp {
509 TCGOpcode opc : 8;
510
511 /* The number of out and in parameter for a call. */
512 unsigned callo : 2;
513 unsigned calli : 6;
514
515 /* Index of the arguments for this op, or -1 for zero-operand ops. */
516 signed args : 16;
517
518 /* Index of the prex/next op, or -1 for the end of the list. */
519 signed prev : 16;
520 signed next : 16;
521 } TCGOp;
522
523 QEMU_BUILD_BUG_ON(NB_OPS > 0xff);
524 QEMU_BUILD_BUG_ON(OPC_BUF_SIZE >= 0x7fff);
525 QEMU_BUILD_BUG_ON(OPPARAM_BUF_SIZE >= 0x7fff);
526
527 struct TCGContext {
528 uint8_t *pool_cur, *pool_end;
529 TCGPool *pool_first, *pool_current, *pool_first_large;
530 int nb_labels;
531 int nb_globals;
532 int nb_temps;
533
534 /* goto_tb support */
535 tcg_insn_unit *code_buf;
536 uint16_t *tb_jmp_reset_offset; /* tb->jmp_reset_offset */
537 uint16_t *tb_jmp_insn_offset; /* tb->jmp_insn_offset if USE_DIRECT_JUMP */
538 uintptr_t *tb_jmp_target_addr; /* tb->jmp_target_addr if !USE_DIRECT_JUMP */
539
540 /* liveness analysis */
541 uint16_t *op_dead_args; /* for each operation, each bit tells if the
542 corresponding argument is dead */
543 uint8_t *op_sync_args; /* for each operation, each bit tells if the
544 corresponding output argument needs to be
545 sync to memory. */
546
547 TCGRegSet reserved_regs;
548 intptr_t current_frame_offset;
549 intptr_t frame_start;
550 intptr_t frame_end;
551 TCGTemp *frame_temp;
552
553 tcg_insn_unit *code_ptr;
554
555 GHashTable *helpers;
556
557 #ifdef CONFIG_PROFILER
558 /* profiling info */
559 int64_t tb_count1;
560 int64_t tb_count;
561 int64_t op_count; /* total insn count */
562 int op_count_max; /* max insn per TB */
563 int64_t temp_count;
564 int temp_count_max;
565 int64_t del_op_count;
566 int64_t code_in_len;
567 int64_t code_out_len;
568 int64_t search_out_len;
569 int64_t interm_time;
570 int64_t code_time;
571 int64_t la_time;
572 int64_t opt_time;
573 int64_t restore_count;
574 int64_t restore_time;
575 #endif
576
577 #ifdef CONFIG_DEBUG_TCG
578 int temps_in_use;
579 int goto_tb_issue_mask;
580 #endif
581
582 int gen_first_op_idx;
583 int gen_last_op_idx;
584 int gen_next_op_idx;
585 int gen_next_parm_idx;
586
587 /* Code generation. Note that we specifically do not use tcg_insn_unit
588 here, because there's too much arithmetic throughout that relies
589 on addition and subtraction working on bytes. Rely on the GCC
590 extension that allows arithmetic on void*. */
591 int code_gen_max_blocks;
592 void *code_gen_prologue;
593 void *code_gen_buffer;
594 size_t code_gen_buffer_size;
595 void *code_gen_ptr;
596
597 /* Threshold to flush the translated code buffer. */
598 void *code_gen_highwater;
599
600 TBContext tb_ctx;
601
602 /* The TCGBackendData structure is private to tcg-target.inc.c. */
603 struct TCGBackendData *be;
604
605 TCGTempSet free_temps[TCG_TYPE_COUNT * 2];
606 TCGTemp temps[TCG_MAX_TEMPS]; /* globals first, temps after */
607
608 /* Tells which temporary holds a given register.
609 It does not take into account fixed registers */
610 TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS];
611
612 TCGOp gen_op_buf[OPC_BUF_SIZE];
613 TCGArg gen_opparam_buf[OPPARAM_BUF_SIZE];
614
615 uint16_t gen_insn_end_off[TCG_MAX_INSNS];
616 target_ulong gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS];
617 };
618
619 extern TCGContext tcg_ctx;
620
621 static inline void tcg_set_insn_param(int op_idx, int arg, TCGArg v)
622 {
623 int op_argi = tcg_ctx.gen_op_buf[op_idx].args;
624 tcg_ctx.gen_opparam_buf[op_argi + arg] = v;
625 }
626
627 /* The number of opcodes emitted so far. */
628 static inline int tcg_op_buf_count(void)
629 {
630 return tcg_ctx.gen_next_op_idx;
631 }
632
633 /* Test for whether to terminate the TB for using too many opcodes. */
634 static inline bool tcg_op_buf_full(void)
635 {
636 return tcg_op_buf_count() >= OPC_MAX_SIZE;
637 }
638
639 /* pool based memory allocation */
640
641 void *tcg_malloc_internal(TCGContext *s, int size);
642 void tcg_pool_reset(TCGContext *s);
643 void tcg_pool_delete(TCGContext *s);
644
645 void tb_lock(void);
646 void tb_unlock(void);
647 void tb_lock_reset(void);
648
649 static inline void *tcg_malloc(int size)
650 {
651 TCGContext *s = &tcg_ctx;
652 uint8_t *ptr, *ptr_end;
653 size = (size + sizeof(long) - 1) & ~(sizeof(long) - 1);
654 ptr = s->pool_cur;
655 ptr_end = ptr + size;
656 if (unlikely(ptr_end > s->pool_end)) {
657 return tcg_malloc_internal(&tcg_ctx, size);
658 } else {
659 s->pool_cur = ptr_end;
660 return ptr;
661 }
662 }
663
664 void tcg_context_init(TCGContext *s);
665 void tcg_prologue_init(TCGContext *s);
666 void tcg_func_start(TCGContext *s);
667
668 int tcg_gen_code(TCGContext *s, TranslationBlock *tb);
669
670 void tcg_set_frame(TCGContext *s, TCGReg reg, intptr_t start, intptr_t size);
671
672 int tcg_global_mem_new_internal(TCGType, TCGv_ptr, intptr_t, const char *);
673
674 TCGv_i32 tcg_global_reg_new_i32(TCGReg reg, const char *name);
675 TCGv_i64 tcg_global_reg_new_i64(TCGReg reg, const char *name);
676
677 TCGv_i32 tcg_temp_new_internal_i32(int temp_local);
678 TCGv_i64 tcg_temp_new_internal_i64(int temp_local);
679
680 void tcg_temp_free_i32(TCGv_i32 arg);
681 void tcg_temp_free_i64(TCGv_i64 arg);
682
683 static inline TCGv_i32 tcg_global_mem_new_i32(TCGv_ptr reg, intptr_t offset,
684 const char *name)
685 {
686 int idx = tcg_global_mem_new_internal(TCG_TYPE_I32, reg, offset, name);
687 return MAKE_TCGV_I32(idx);
688 }
689
690 static inline TCGv_i32 tcg_temp_new_i32(void)
691 {
692 return tcg_temp_new_internal_i32(0);
693 }
694
695 static inline TCGv_i32 tcg_temp_local_new_i32(void)
696 {
697 return tcg_temp_new_internal_i32(1);
698 }
699
700 static inline TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t offset,
701 const char *name)
702 {
703 int idx = tcg_global_mem_new_internal(TCG_TYPE_I64, reg, offset, name);
704 return MAKE_TCGV_I64(idx);
705 }
706
707 static inline TCGv_i64 tcg_temp_new_i64(void)
708 {
709 return tcg_temp_new_internal_i64(0);
710 }
711
712 static inline TCGv_i64 tcg_temp_local_new_i64(void)
713 {
714 return tcg_temp_new_internal_i64(1);
715 }
716
717 #if defined(CONFIG_DEBUG_TCG)
718 /* If you call tcg_clear_temp_count() at the start of a section of
719 * code which is not supposed to leak any TCG temporaries, then
720 * calling tcg_check_temp_count() at the end of the section will
721 * return 1 if the section did in fact leak a temporary.
722 */
723 void tcg_clear_temp_count(void);
724 int tcg_check_temp_count(void);
725 #else
726 #define tcg_clear_temp_count() do { } while (0)
727 #define tcg_check_temp_count() 0
728 #endif
729
730 void tcg_dump_info(FILE *f, fprintf_function cpu_fprintf);
731 void tcg_dump_op_count(FILE *f, fprintf_function cpu_fprintf);
732
733 #define TCG_CT_ALIAS 0x80
734 #define TCG_CT_IALIAS 0x40
735 #define TCG_CT_REG 0x01
736 #define TCG_CT_CONST 0x02 /* any constant of register size */
737
738 typedef struct TCGArgConstraint {
739 uint16_t ct;
740 uint8_t alias_index;
741 union {
742 TCGRegSet regs;
743 } u;
744 } TCGArgConstraint;
745
746 #define TCG_MAX_OP_ARGS 16
747
748 /* Bits for TCGOpDef->flags, 8 bits available. */
749 enum {
750 /* Instruction defines the end of a basic block. */
751 TCG_OPF_BB_END = 0x01,
752 /* Instruction clobbers call registers and potentially update globals. */
753 TCG_OPF_CALL_CLOBBER = 0x02,
754 /* Instruction has side effects: it cannot be removed if its outputs
755 are not used, and might trigger exceptions. */
756 TCG_OPF_SIDE_EFFECTS = 0x04,
757 /* Instruction operands are 64-bits (otherwise 32-bits). */
758 TCG_OPF_64BIT = 0x08,
759 /* Instruction is optional and not implemented by the host, or insn
760 is generic and should not be implemened by the host. */
761 TCG_OPF_NOT_PRESENT = 0x10,
762 };
763
764 typedef struct TCGOpDef {
765 const char *name;
766 uint8_t nb_oargs, nb_iargs, nb_cargs, nb_args;
767 uint8_t flags;
768 TCGArgConstraint *args_ct;
769 int *sorted_args;
770 #if defined(CONFIG_DEBUG_TCG)
771 int used;
772 #endif
773 } TCGOpDef;
774
775 extern TCGOpDef tcg_op_defs[];
776 extern const size_t tcg_op_defs_max;
777
778 typedef struct TCGTargetOpDef {
779 TCGOpcode op;
780 const char *args_ct_str[TCG_MAX_OP_ARGS];
781 } TCGTargetOpDef;
782
783 #define tcg_abort() \
784 do {\
785 fprintf(stderr, "%s:%d: tcg fatal error\n", __FILE__, __LINE__);\
786 abort();\
787 } while (0)
788
789 #ifdef CONFIG_DEBUG_TCG
790 # define tcg_debug_assert(X) do { assert(X); } while (0)
791 #elif QEMU_GNUC_PREREQ(4, 5)
792 # define tcg_debug_assert(X) \
793 do { if (!(X)) { __builtin_unreachable(); } } while (0)
794 #else
795 # define tcg_debug_assert(X) do { (void)(X); } while (0)
796 #endif
797
798 void tcg_add_target_add_op_defs(const TCGTargetOpDef *tdefs);
799
800 #if UINTPTR_MAX == UINT32_MAX
801 #define TCGV_NAT_TO_PTR(n) MAKE_TCGV_PTR(GET_TCGV_I32(n))
802 #define TCGV_PTR_TO_NAT(n) MAKE_TCGV_I32(GET_TCGV_PTR(n))
803
804 #define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i32((intptr_t)(V)))
805 #define tcg_global_reg_new_ptr(R, N) \
806 TCGV_NAT_TO_PTR(tcg_global_reg_new_i32((R), (N)))
807 #define tcg_global_mem_new_ptr(R, O, N) \
808 TCGV_NAT_TO_PTR(tcg_global_mem_new_i32((R), (O), (N)))
809 #define tcg_temp_new_ptr() TCGV_NAT_TO_PTR(tcg_temp_new_i32())
810 #define tcg_temp_free_ptr(T) tcg_temp_free_i32(TCGV_PTR_TO_NAT(T))
811 #else
812 #define TCGV_NAT_TO_PTR(n) MAKE_TCGV_PTR(GET_TCGV_I64(n))
813 #define TCGV_PTR_TO_NAT(n) MAKE_TCGV_I64(GET_TCGV_PTR(n))
814
815 #define tcg_const_ptr(V) TCGV_NAT_TO_PTR(tcg_const_i64((intptr_t)(V)))
816 #define tcg_global_reg_new_ptr(R, N) \
817 TCGV_NAT_TO_PTR(tcg_global_reg_new_i64((R), (N)))
818 #define tcg_global_mem_new_ptr(R, O, N) \
819 TCGV_NAT_TO_PTR(tcg_global_mem_new_i64((R), (O), (N)))
820 #define tcg_temp_new_ptr() TCGV_NAT_TO_PTR(tcg_temp_new_i64())
821 #define tcg_temp_free_ptr(T) tcg_temp_free_i64(TCGV_PTR_TO_NAT(T))
822 #endif
823
824 void tcg_gen_callN(TCGContext *s, void *func,
825 TCGArg ret, int nargs, TCGArg *args);
826
827 void tcg_op_remove(TCGContext *s, TCGOp *op);
828 void tcg_optimize(TCGContext *s);
829
830 /* only used for debugging purposes */
831 void tcg_dump_ops(TCGContext *s);
832
833 void dump_ops(const uint16_t *opc_buf, const TCGArg *opparam_buf);
834 TCGv_i32 tcg_const_i32(int32_t val);
835 TCGv_i64 tcg_const_i64(int64_t val);
836 TCGv_i32 tcg_const_local_i32(int32_t val);
837 TCGv_i64 tcg_const_local_i64(int64_t val);
838
839 TCGLabel *gen_new_label(void);
840
841 /**
842 * label_arg
843 * @l: label
844 *
845 * Encode a label for storage in the TCG opcode stream.
846 */
847
848 static inline TCGArg label_arg(TCGLabel *l)
849 {
850 return (uintptr_t)l;
851 }
852
853 /**
854 * arg_label
855 * @i: value
856 *
857 * The opposite of label_arg. Retrieve a label from the
858 * encoding of the TCG opcode stream.
859 */
860
861 static inline TCGLabel *arg_label(TCGArg i)
862 {
863 return (TCGLabel *)(uintptr_t)i;
864 }
865
866 /**
867 * tcg_ptr_byte_diff
868 * @a, @b: addresses to be differenced
869 *
870 * There are many places within the TCG backends where we need a byte
871 * difference between two pointers. While this can be accomplished
872 * with local casting, it's easy to get wrong -- especially if one is
873 * concerned with the signedness of the result.
874 *
875 * This version relies on GCC's void pointer arithmetic to get the
876 * correct result.
877 */
878
879 static inline ptrdiff_t tcg_ptr_byte_diff(void *a, void *b)
880 {
881 return a - b;
882 }
883
884 /**
885 * tcg_pcrel_diff
886 * @s: the tcg context
887 * @target: address of the target
888 *
889 * Produce a pc-relative difference, from the current code_ptr
890 * to the destination address.
891 */
892
893 static inline ptrdiff_t tcg_pcrel_diff(TCGContext *s, void *target)
894 {
895 return tcg_ptr_byte_diff(target, s->code_ptr);
896 }
897
898 /**
899 * tcg_current_code_size
900 * @s: the tcg context
901 *
902 * Compute the current code size within the translation block.
903 * This is used to fill in qemu's data structures for goto_tb.
904 */
905
906 static inline size_t tcg_current_code_size(TCGContext *s)
907 {
908 return tcg_ptr_byte_diff(s->code_ptr, s->code_buf);
909 }
910
911 /* Combine the TCGMemOp and mmu_idx parameters into a single value. */
912 typedef uint32_t TCGMemOpIdx;
913
914 /**
915 * make_memop_idx
916 * @op: memory operation
917 * @idx: mmu index
918 *
919 * Encode these values into a single parameter.
920 */
921 static inline TCGMemOpIdx make_memop_idx(TCGMemOp op, unsigned idx)
922 {
923 tcg_debug_assert(idx <= 15);
924 return (op << 4) | idx;
925 }
926
927 /**
928 * get_memop
929 * @oi: combined op/idx parameter
930 *
931 * Extract the memory operation from the combined value.
932 */
933 static inline TCGMemOp get_memop(TCGMemOpIdx oi)
934 {
935 return oi >> 4;
936 }
937
938 /**
939 * get_mmuidx
940 * @oi: combined op/idx parameter
941 *
942 * Extract the mmu index from the combined value.
943 */
944 static inline unsigned get_mmuidx(TCGMemOpIdx oi)
945 {
946 return oi & 15;
947 }
948
949 /**
950 * tcg_qemu_tb_exec:
951 * @env: pointer to CPUArchState for the CPU
952 * @tb_ptr: address of generated code for the TB to execute
953 *
954 * Start executing code from a given translation block.
955 * Where translation blocks have been linked, execution
956 * may proceed from the given TB into successive ones.
957 * Control eventually returns only when some action is needed
958 * from the top-level loop: either control must pass to a TB
959 * which has not yet been directly linked, or an asynchronous
960 * event such as an interrupt needs handling.
961 *
962 * Return: The return value is the value passed to the corresponding
963 * tcg_gen_exit_tb() at translation time of the last TB attempted to execute.
964 * The value is either zero or a 4-byte aligned pointer to that TB combined
965 * with additional information in its two least significant bits. The
966 * additional information is encoded as follows:
967 * 0, 1: the link between this TB and the next is via the specified
968 * TB index (0 or 1). That is, we left the TB via (the equivalent
969 * of) "goto_tb <index>". The main loop uses this to determine
970 * how to link the TB just executed to the next.
971 * 2: we are using instruction counting code generation, and we
972 * did not start executing this TB because the instruction counter
973 * would hit zero midway through it. In this case the pointer
974 * returned is the TB we were about to execute, and the caller must
975 * arrange to execute the remaining count of instructions.
976 * 3: we stopped because the CPU's exit_request flag was set
977 * (usually meaning that there is an interrupt that needs to be
978 * handled). The pointer returned is the TB we were about to execute
979 * when we noticed the pending exit request.
980 *
981 * If the bottom two bits indicate an exit-via-index then the CPU
982 * state is correctly synchronised and ready for execution of the next
983 * TB (and in particular the guest PC is the address to execute next).
984 * Otherwise, we gave up on execution of this TB before it started, and
985 * the caller must fix up the CPU state by calling the CPU's
986 * synchronize_from_tb() method with the TB pointer we return (falling
987 * back to calling the CPU's set_pc method with tb->pb if no
988 * synchronize_from_tb() method exists).
989 *
990 * Note that TCG targets may use a different definition of tcg_qemu_tb_exec
991 * to this default (which just calls the prologue.code emitted by
992 * tcg_target_qemu_prologue()).
993 */
994 #define TB_EXIT_MASK 3
995 #define TB_EXIT_IDX0 0
996 #define TB_EXIT_IDX1 1
997 #define TB_EXIT_ICOUNT_EXPIRED 2
998 #define TB_EXIT_REQUESTED 3
999
1000 #ifdef HAVE_TCG_QEMU_TB_EXEC
1001 uintptr_t tcg_qemu_tb_exec(CPUArchState *env, uint8_t *tb_ptr);
1002 #else
1003 # define tcg_qemu_tb_exec(env, tb_ptr) \
1004 ((uintptr_t (*)(void *, void *))tcg_ctx.code_gen_prologue)(env, tb_ptr)
1005 #endif
1006
1007 void tcg_register_jit(void *buf, size_t buf_size);
1008
1009 /*
1010 * Memory helpers that will be used by TCG generated code.
1011 */
1012 #ifdef CONFIG_SOFTMMU
1013 /* Value zero-extended to tcg register size. */
1014 tcg_target_ulong helper_ret_ldub_mmu(CPUArchState *env, target_ulong addr,
1015 TCGMemOpIdx oi, uintptr_t retaddr);
1016 tcg_target_ulong helper_le_lduw_mmu(CPUArchState *env, target_ulong addr,
1017 TCGMemOpIdx oi, uintptr_t retaddr);
1018 tcg_target_ulong helper_le_ldul_mmu(CPUArchState *env, target_ulong addr,
1019 TCGMemOpIdx oi, uintptr_t retaddr);
1020 uint64_t helper_le_ldq_mmu(CPUArchState *env, target_ulong addr,
1021 TCGMemOpIdx oi, uintptr_t retaddr);
1022 tcg_target_ulong helper_be_lduw_mmu(CPUArchState *env, target_ulong addr,
1023 TCGMemOpIdx oi, uintptr_t retaddr);
1024 tcg_target_ulong helper_be_ldul_mmu(CPUArchState *env, target_ulong addr,
1025 TCGMemOpIdx oi, uintptr_t retaddr);
1026 uint64_t helper_be_ldq_mmu(CPUArchState *env, target_ulong addr,
1027 TCGMemOpIdx oi, uintptr_t retaddr);
1028
1029 /* Value sign-extended to tcg register size. */
1030 tcg_target_ulong helper_ret_ldsb_mmu(CPUArchState *env, target_ulong addr,
1031 TCGMemOpIdx oi, uintptr_t retaddr);
1032 tcg_target_ulong helper_le_ldsw_mmu(CPUArchState *env, target_ulong addr,
1033 TCGMemOpIdx oi, uintptr_t retaddr);
1034 tcg_target_ulong helper_le_ldsl_mmu(CPUArchState *env, target_ulong addr,
1035 TCGMemOpIdx oi, uintptr_t retaddr);
1036 tcg_target_ulong helper_be_ldsw_mmu(CPUArchState *env, target_ulong addr,
1037 TCGMemOpIdx oi, uintptr_t retaddr);
1038 tcg_target_ulong helper_be_ldsl_mmu(CPUArchState *env, target_ulong addr,
1039 TCGMemOpIdx oi, uintptr_t retaddr);
1040
1041 void helper_ret_stb_mmu(CPUArchState *env, target_ulong addr, uint8_t val,
1042 TCGMemOpIdx oi, uintptr_t retaddr);
1043 void helper_le_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
1044 TCGMemOpIdx oi, uintptr_t retaddr);
1045 void helper_le_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
1046 TCGMemOpIdx oi, uintptr_t retaddr);
1047 void helper_le_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
1048 TCGMemOpIdx oi, uintptr_t retaddr);
1049 void helper_be_stw_mmu(CPUArchState *env, target_ulong addr, uint16_t val,
1050 TCGMemOpIdx oi, uintptr_t retaddr);
1051 void helper_be_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val,
1052 TCGMemOpIdx oi, uintptr_t retaddr);
1053 void helper_be_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val,
1054 TCGMemOpIdx oi, uintptr_t retaddr);
1055
1056 uint8_t helper_ret_ldb_cmmu(CPUArchState *env, target_ulong addr,
1057 TCGMemOpIdx oi, uintptr_t retaddr);
1058 uint16_t helper_le_ldw_cmmu(CPUArchState *env, target_ulong addr,
1059 TCGMemOpIdx oi, uintptr_t retaddr);
1060 uint32_t helper_le_ldl_cmmu(CPUArchState *env, target_ulong addr,
1061 TCGMemOpIdx oi, uintptr_t retaddr);
1062 uint64_t helper_le_ldq_cmmu(CPUArchState *env, target_ulong addr,
1063 TCGMemOpIdx oi, uintptr_t retaddr);
1064 uint16_t helper_be_ldw_cmmu(CPUArchState *env, target_ulong addr,
1065 TCGMemOpIdx oi, uintptr_t retaddr);
1066 uint32_t helper_be_ldl_cmmu(CPUArchState *env, target_ulong addr,
1067 TCGMemOpIdx oi, uintptr_t retaddr);
1068 uint64_t helper_be_ldq_cmmu(CPUArchState *env, target_ulong addr,
1069 TCGMemOpIdx oi, uintptr_t retaddr);
1070
1071 /* Temporary aliases until backends are converted. */
1072 #ifdef TARGET_WORDS_BIGENDIAN
1073 # define helper_ret_ldsw_mmu helper_be_ldsw_mmu
1074 # define helper_ret_lduw_mmu helper_be_lduw_mmu
1075 # define helper_ret_ldsl_mmu helper_be_ldsl_mmu
1076 # define helper_ret_ldul_mmu helper_be_ldul_mmu
1077 # define helper_ret_ldl_mmu helper_be_ldul_mmu
1078 # define helper_ret_ldq_mmu helper_be_ldq_mmu
1079 # define helper_ret_stw_mmu helper_be_stw_mmu
1080 # define helper_ret_stl_mmu helper_be_stl_mmu
1081 # define helper_ret_stq_mmu helper_be_stq_mmu
1082 # define helper_ret_ldw_cmmu helper_be_ldw_cmmu
1083 # define helper_ret_ldl_cmmu helper_be_ldl_cmmu
1084 # define helper_ret_ldq_cmmu helper_be_ldq_cmmu
1085 #else
1086 # define helper_ret_ldsw_mmu helper_le_ldsw_mmu
1087 # define helper_ret_lduw_mmu helper_le_lduw_mmu
1088 # define helper_ret_ldsl_mmu helper_le_ldsl_mmu
1089 # define helper_ret_ldul_mmu helper_le_ldul_mmu
1090 # define helper_ret_ldl_mmu helper_le_ldul_mmu
1091 # define helper_ret_ldq_mmu helper_le_ldq_mmu
1092 # define helper_ret_stw_mmu helper_le_stw_mmu
1093 # define helper_ret_stl_mmu helper_le_stl_mmu
1094 # define helper_ret_stq_mmu helper_le_stq_mmu
1095 # define helper_ret_ldw_cmmu helper_le_ldw_cmmu
1096 # define helper_ret_ldl_cmmu helper_le_ldl_cmmu
1097 # define helper_ret_ldq_cmmu helper_le_ldq_cmmu
1098 #endif
1099
1100 #endif /* CONFIG_SOFTMMU */
1101
1102 #endif /* TCG_H */