linux-user: Support for restarting system calls for OpenRISC targets
[qemu.git] / tests / ide-test.c
1 /*
2 * IDE test cases
3 *
4 * Copyright (c) 2013 Kevin Wolf <kwolf@redhat.com>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26
27 #include <glib.h>
28
29 #include "libqtest.h"
30 #include "libqos/libqos.h"
31 #include "libqos/pci-pc.h"
32 #include "libqos/malloc-pc.h"
33
34 #include "qemu-common.h"
35 #include "qemu/bswap.h"
36 #include "hw/pci/pci_ids.h"
37 #include "hw/pci/pci_regs.h"
38
39 #define TEST_IMAGE_SIZE 64 * 1024 * 1024
40
41 #define IDE_PCI_DEV 1
42 #define IDE_PCI_FUNC 1
43
44 #define IDE_BASE 0x1f0
45 #define IDE_PRIMARY_IRQ 14
46
47 #define ATAPI_BLOCK_SIZE 2048
48
49 /* How many bytes to receive via ATAPI PIO at one time.
50 * Must be less than 0xFFFF. */
51 #define BYTE_COUNT_LIMIT 5120
52
53 enum {
54 reg_data = 0x0,
55 reg_feature = 0x1,
56 reg_nsectors = 0x2,
57 reg_lba_low = 0x3,
58 reg_lba_middle = 0x4,
59 reg_lba_high = 0x5,
60 reg_device = 0x6,
61 reg_status = 0x7,
62 reg_command = 0x7,
63 };
64
65 enum {
66 BSY = 0x80,
67 DRDY = 0x40,
68 DF = 0x20,
69 DRQ = 0x08,
70 ERR = 0x01,
71 };
72
73 enum {
74 DEV = 0x10,
75 LBA = 0x40,
76 };
77
78 enum {
79 bmreg_cmd = 0x0,
80 bmreg_status = 0x2,
81 bmreg_prdt = 0x4,
82 };
83
84 enum {
85 CMD_READ_DMA = 0xc8,
86 CMD_WRITE_DMA = 0xca,
87 CMD_FLUSH_CACHE = 0xe7,
88 CMD_IDENTIFY = 0xec,
89 CMD_PACKET = 0xa0,
90
91 CMDF_ABORT = 0x100,
92 CMDF_NO_BM = 0x200,
93 };
94
95 enum {
96 BM_CMD_START = 0x1,
97 BM_CMD_WRITE = 0x8, /* write = from device to memory */
98 };
99
100 enum {
101 BM_STS_ACTIVE = 0x1,
102 BM_STS_ERROR = 0x2,
103 BM_STS_INTR = 0x4,
104 };
105
106 enum {
107 PRDT_EOT = 0x80000000,
108 };
109
110 #define assert_bit_set(data, mask) g_assert_cmphex((data) & (mask), ==, (mask))
111 #define assert_bit_clear(data, mask) g_assert_cmphex((data) & (mask), ==, 0)
112
113 static QPCIBus *pcibus = NULL;
114 static QGuestAllocator *guest_malloc;
115
116 static char tmp_path[] = "/tmp/qtest.XXXXXX";
117 static char debug_path[] = "/tmp/qtest-blkdebug.XXXXXX";
118
119 static void ide_test_start(const char *cmdline_fmt, ...)
120 {
121 va_list ap;
122 char *cmdline;
123
124 va_start(ap, cmdline_fmt);
125 cmdline = g_strdup_vprintf(cmdline_fmt, ap);
126 va_end(ap);
127
128 qtest_start(cmdline);
129 guest_malloc = pc_alloc_init();
130
131 g_free(cmdline);
132 }
133
134 static void ide_test_quit(void)
135 {
136 pc_alloc_uninit(guest_malloc);
137 guest_malloc = NULL;
138 qtest_end();
139 }
140
141 static QPCIDevice *get_pci_device(uint16_t *bmdma_base)
142 {
143 QPCIDevice *dev;
144 uint16_t vendor_id, device_id;
145
146 if (!pcibus) {
147 pcibus = qpci_init_pc();
148 }
149
150 /* Find PCI device and verify it's the right one */
151 dev = qpci_device_find(pcibus, QPCI_DEVFN(IDE_PCI_DEV, IDE_PCI_FUNC));
152 g_assert(dev != NULL);
153
154 vendor_id = qpci_config_readw(dev, PCI_VENDOR_ID);
155 device_id = qpci_config_readw(dev, PCI_DEVICE_ID);
156 g_assert(vendor_id == PCI_VENDOR_ID_INTEL);
157 g_assert(device_id == PCI_DEVICE_ID_INTEL_82371SB_1);
158
159 /* Map bmdma BAR */
160 *bmdma_base = (uint16_t)(uintptr_t) qpci_iomap(dev, 4, NULL);
161
162 qpci_device_enable(dev);
163
164 return dev;
165 }
166
167 static void free_pci_device(QPCIDevice *dev)
168 {
169 /* libqos doesn't have a function for this, so free it manually */
170 g_free(dev);
171 }
172
173 typedef struct PrdtEntry {
174 uint32_t addr;
175 uint32_t size;
176 } QEMU_PACKED PrdtEntry;
177
178 #define assert_bit_set(data, mask) g_assert_cmphex((data) & (mask), ==, (mask))
179 #define assert_bit_clear(data, mask) g_assert_cmphex((data) & (mask), ==, 0)
180
181 static int send_dma_request(int cmd, uint64_t sector, int nb_sectors,
182 PrdtEntry *prdt, int prdt_entries,
183 void(*post_exec)(uint64_t sector, int nb_sectors))
184 {
185 QPCIDevice *dev;
186 uint16_t bmdma_base;
187 uintptr_t guest_prdt;
188 size_t len;
189 bool from_dev;
190 uint8_t status;
191 int flags;
192
193 dev = get_pci_device(&bmdma_base);
194
195 flags = cmd & ~0xff;
196 cmd &= 0xff;
197
198 switch (cmd) {
199 case CMD_READ_DMA:
200 case CMD_PACKET:
201 /* Assuming we only test data reads w/ ATAPI, otherwise we need to know
202 * the SCSI command being sent in the packet, too. */
203 from_dev = true;
204 break;
205 case CMD_WRITE_DMA:
206 from_dev = false;
207 break;
208 default:
209 g_assert_not_reached();
210 }
211
212 if (flags & CMDF_NO_BM) {
213 qpci_config_writew(dev, PCI_COMMAND,
214 PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
215 }
216
217 /* Select device 0 */
218 outb(IDE_BASE + reg_device, 0 | LBA);
219
220 /* Stop any running transfer, clear any pending interrupt */
221 outb(bmdma_base + bmreg_cmd, 0);
222 outb(bmdma_base + bmreg_status, BM_STS_INTR);
223
224 /* Setup PRDT */
225 len = sizeof(*prdt) * prdt_entries;
226 guest_prdt = guest_alloc(guest_malloc, len);
227 memwrite(guest_prdt, prdt, len);
228 outl(bmdma_base + bmreg_prdt, guest_prdt);
229
230 /* ATA DMA command */
231 if (cmd == CMD_PACKET) {
232 /* Enables ATAPI DMA; otherwise PIO is attempted */
233 outb(IDE_BASE + reg_feature, 0x01);
234 } else {
235 outb(IDE_BASE + reg_nsectors, nb_sectors);
236 outb(IDE_BASE + reg_lba_low, sector & 0xff);
237 outb(IDE_BASE + reg_lba_middle, (sector >> 8) & 0xff);
238 outb(IDE_BASE + reg_lba_high, (sector >> 16) & 0xff);
239 }
240
241 outb(IDE_BASE + reg_command, cmd);
242
243 if (post_exec) {
244 post_exec(sector, nb_sectors);
245 }
246
247 /* Start DMA transfer */
248 outb(bmdma_base + bmreg_cmd, BM_CMD_START | (from_dev ? BM_CMD_WRITE : 0));
249
250 if (flags & CMDF_ABORT) {
251 outb(bmdma_base + bmreg_cmd, 0);
252 }
253
254 /* Wait for the DMA transfer to complete */
255 do {
256 status = inb(bmdma_base + bmreg_status);
257 } while ((status & (BM_STS_ACTIVE | BM_STS_INTR)) == BM_STS_ACTIVE);
258
259 g_assert_cmpint(get_irq(IDE_PRIMARY_IRQ), ==, !!(status & BM_STS_INTR));
260
261 /* Check IDE status code */
262 assert_bit_set(inb(IDE_BASE + reg_status), DRDY);
263 assert_bit_clear(inb(IDE_BASE + reg_status), BSY | DRQ);
264
265 /* Reading the status register clears the IRQ */
266 g_assert(!get_irq(IDE_PRIMARY_IRQ));
267
268 /* Stop DMA transfer if still active */
269 if (status & BM_STS_ACTIVE) {
270 outb(bmdma_base + bmreg_cmd, 0);
271 }
272
273 free_pci_device(dev);
274
275 return status;
276 }
277
278 static void test_bmdma_simple_rw(void)
279 {
280 uint8_t status;
281 uint8_t *buf;
282 uint8_t *cmpbuf;
283 size_t len = 512;
284 uintptr_t guest_buf = guest_alloc(guest_malloc, len);
285
286 PrdtEntry prdt[] = {
287 {
288 .addr = cpu_to_le32(guest_buf),
289 .size = cpu_to_le32(len | PRDT_EOT),
290 },
291 };
292
293 buf = g_malloc(len);
294 cmpbuf = g_malloc(len);
295
296 /* Write 0x55 pattern to sector 0 */
297 memset(buf, 0x55, len);
298 memwrite(guest_buf, buf, len);
299
300 status = send_dma_request(CMD_WRITE_DMA, 0, 1, prdt,
301 ARRAY_SIZE(prdt), NULL);
302 g_assert_cmphex(status, ==, BM_STS_INTR);
303 assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);
304
305 /* Write 0xaa pattern to sector 1 */
306 memset(buf, 0xaa, len);
307 memwrite(guest_buf, buf, len);
308
309 status = send_dma_request(CMD_WRITE_DMA, 1, 1, prdt,
310 ARRAY_SIZE(prdt), NULL);
311 g_assert_cmphex(status, ==, BM_STS_INTR);
312 assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);
313
314 /* Read and verify 0x55 pattern in sector 0 */
315 memset(cmpbuf, 0x55, len);
316
317 status = send_dma_request(CMD_READ_DMA, 0, 1, prdt, ARRAY_SIZE(prdt), NULL);
318 g_assert_cmphex(status, ==, BM_STS_INTR);
319 assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);
320
321 memread(guest_buf, buf, len);
322 g_assert(memcmp(buf, cmpbuf, len) == 0);
323
324 /* Read and verify 0xaa pattern in sector 1 */
325 memset(cmpbuf, 0xaa, len);
326
327 status = send_dma_request(CMD_READ_DMA, 1, 1, prdt, ARRAY_SIZE(prdt), NULL);
328 g_assert_cmphex(status, ==, BM_STS_INTR);
329 assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);
330
331 memread(guest_buf, buf, len);
332 g_assert(memcmp(buf, cmpbuf, len) == 0);
333
334
335 g_free(buf);
336 g_free(cmpbuf);
337 }
338
339 static void test_bmdma_short_prdt(void)
340 {
341 uint8_t status;
342
343 PrdtEntry prdt[] = {
344 {
345 .addr = 0,
346 .size = cpu_to_le32(0x10 | PRDT_EOT),
347 },
348 };
349
350 /* Normal request */
351 status = send_dma_request(CMD_READ_DMA, 0, 1,
352 prdt, ARRAY_SIZE(prdt), NULL);
353 g_assert_cmphex(status, ==, 0);
354 assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);
355
356 /* Abort the request before it completes */
357 status = send_dma_request(CMD_READ_DMA | CMDF_ABORT, 0, 1,
358 prdt, ARRAY_SIZE(prdt), NULL);
359 g_assert_cmphex(status, ==, 0);
360 assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);
361 }
362
363 static void test_bmdma_one_sector_short_prdt(void)
364 {
365 uint8_t status;
366
367 /* Read 2 sectors but only give 1 sector in PRDT */
368 PrdtEntry prdt[] = {
369 {
370 .addr = 0,
371 .size = cpu_to_le32(0x200 | PRDT_EOT),
372 },
373 };
374
375 /* Normal request */
376 status = send_dma_request(CMD_READ_DMA, 0, 2,
377 prdt, ARRAY_SIZE(prdt), NULL);
378 g_assert_cmphex(status, ==, 0);
379 assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);
380
381 /* Abort the request before it completes */
382 status = send_dma_request(CMD_READ_DMA | CMDF_ABORT, 0, 2,
383 prdt, ARRAY_SIZE(prdt), NULL);
384 g_assert_cmphex(status, ==, 0);
385 assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);
386 }
387
388 static void test_bmdma_long_prdt(void)
389 {
390 uint8_t status;
391
392 PrdtEntry prdt[] = {
393 {
394 .addr = 0,
395 .size = cpu_to_le32(0x1000 | PRDT_EOT),
396 },
397 };
398
399 /* Normal request */
400 status = send_dma_request(CMD_READ_DMA, 0, 1,
401 prdt, ARRAY_SIZE(prdt), NULL);
402 g_assert_cmphex(status, ==, BM_STS_ACTIVE | BM_STS_INTR);
403 assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);
404
405 /* Abort the request before it completes */
406 status = send_dma_request(CMD_READ_DMA | CMDF_ABORT, 0, 1,
407 prdt, ARRAY_SIZE(prdt), NULL);
408 g_assert_cmphex(status, ==, BM_STS_INTR);
409 assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);
410 }
411
412 static void test_bmdma_no_busmaster(void)
413 {
414 uint8_t status;
415
416 /* No PRDT_EOT, each entry addr 0/size 64k, and in theory qemu shouldn't be
417 * able to access it anyway because the Bus Master bit in the PCI command
418 * register isn't set. This is complete nonsense, but it used to be pretty
419 * good at confusing and occasionally crashing qemu. */
420 PrdtEntry prdt[4096] = { };
421
422 status = send_dma_request(CMD_READ_DMA | CMDF_NO_BM, 0, 512,
423 prdt, ARRAY_SIZE(prdt), NULL);
424
425 /* Not entirely clear what the expected result is, but this is what we get
426 * in practice. At least we want to be aware of any changes. */
427 g_assert_cmphex(status, ==, BM_STS_ACTIVE | BM_STS_INTR);
428 assert_bit_clear(inb(IDE_BASE + reg_status), DF | ERR);
429 }
430
431 static void test_bmdma_setup(void)
432 {
433 ide_test_start(
434 "-drive file=%s,if=ide,serial=%s,cache=writeback,format=raw "
435 "-global ide-hd.ver=%s",
436 tmp_path, "testdisk", "version");
437 qtest_irq_intercept_in(global_qtest, "ioapic");
438 }
439
440 static void test_bmdma_teardown(void)
441 {
442 ide_test_quit();
443 }
444
445 static void string_cpu_to_be16(uint16_t *s, size_t bytes)
446 {
447 g_assert((bytes & 1) == 0);
448 bytes /= 2;
449
450 while (bytes--) {
451 *s = cpu_to_be16(*s);
452 s++;
453 }
454 }
455
456 static void test_identify(void)
457 {
458 uint8_t data;
459 uint16_t buf[256];
460 int i;
461 int ret;
462
463 ide_test_start(
464 "-drive file=%s,if=ide,serial=%s,cache=writeback,format=raw "
465 "-global ide-hd.ver=%s",
466 tmp_path, "testdisk", "version");
467
468 /* IDENTIFY command on device 0*/
469 outb(IDE_BASE + reg_device, 0);
470 outb(IDE_BASE + reg_command, CMD_IDENTIFY);
471
472 /* Read in the IDENTIFY buffer and check registers */
473 data = inb(IDE_BASE + reg_device);
474 g_assert_cmpint(data & DEV, ==, 0);
475
476 for (i = 0; i < 256; i++) {
477 data = inb(IDE_BASE + reg_status);
478 assert_bit_set(data, DRDY | DRQ);
479 assert_bit_clear(data, BSY | DF | ERR);
480
481 ((uint16_t*) buf)[i] = inw(IDE_BASE + reg_data);
482 }
483
484 data = inb(IDE_BASE + reg_status);
485 assert_bit_set(data, DRDY);
486 assert_bit_clear(data, BSY | DF | ERR | DRQ);
487
488 /* Check serial number/version in the buffer */
489 string_cpu_to_be16(&buf[10], 20);
490 ret = memcmp(&buf[10], "testdisk ", 20);
491 g_assert(ret == 0);
492
493 string_cpu_to_be16(&buf[23], 8);
494 ret = memcmp(&buf[23], "version ", 8);
495 g_assert(ret == 0);
496
497 /* Write cache enabled bit */
498 assert_bit_set(buf[85], 0x20);
499
500 ide_test_quit();
501 }
502
503 static void test_flush(void)
504 {
505 uint8_t data;
506
507 ide_test_start(
508 "-drive file=blkdebug::%s,if=ide,cache=writeback,format=raw",
509 tmp_path);
510
511 /* Delay the completion of the flush request until we explicitly do it */
512 g_free(hmp("qemu-io ide0-hd0 \"break flush_to_os A\""));
513
514 /* FLUSH CACHE command on device 0*/
515 outb(IDE_BASE + reg_device, 0);
516 outb(IDE_BASE + reg_command, CMD_FLUSH_CACHE);
517
518 /* Check status while request is in flight*/
519 data = inb(IDE_BASE + reg_status);
520 assert_bit_set(data, BSY | DRDY);
521 assert_bit_clear(data, DF | ERR | DRQ);
522
523 /* Complete the command */
524 g_free(hmp("qemu-io ide0-hd0 \"resume A\""));
525
526 /* Check registers */
527 data = inb(IDE_BASE + reg_device);
528 g_assert_cmpint(data & DEV, ==, 0);
529
530 do {
531 data = inb(IDE_BASE + reg_status);
532 } while (data & BSY);
533
534 assert_bit_set(data, DRDY);
535 assert_bit_clear(data, BSY | DF | ERR | DRQ);
536
537 ide_test_quit();
538 }
539
540 static void test_retry_flush(const char *machine)
541 {
542 uint8_t data;
543 const char *s;
544
545 prepare_blkdebug_script(debug_path, "flush_to_disk");
546
547 ide_test_start(
548 "-vnc none "
549 "-drive file=blkdebug:%s:%s,if=ide,cache=writeback,format=raw,"
550 "rerror=stop,werror=stop",
551 debug_path, tmp_path);
552
553 /* FLUSH CACHE command on device 0*/
554 outb(IDE_BASE + reg_device, 0);
555 outb(IDE_BASE + reg_command, CMD_FLUSH_CACHE);
556
557 /* Check status while request is in flight*/
558 data = inb(IDE_BASE + reg_status);
559 assert_bit_set(data, BSY | DRDY);
560 assert_bit_clear(data, DF | ERR | DRQ);
561
562 qmp_eventwait("STOP");
563
564 /* Complete the command */
565 s = "{'execute':'cont' }";
566 qmp_discard_response(s);
567
568 /* Check registers */
569 data = inb(IDE_BASE + reg_device);
570 g_assert_cmpint(data & DEV, ==, 0);
571
572 do {
573 data = inb(IDE_BASE + reg_status);
574 } while (data & BSY);
575
576 assert_bit_set(data, DRDY);
577 assert_bit_clear(data, BSY | DF | ERR | DRQ);
578
579 ide_test_quit();
580 }
581
582 static void test_flush_nodev(void)
583 {
584 ide_test_start("");
585
586 /* FLUSH CACHE command on device 0*/
587 outb(IDE_BASE + reg_device, 0);
588 outb(IDE_BASE + reg_command, CMD_FLUSH_CACHE);
589
590 /* Just testing that qemu doesn't crash... */
591
592 ide_test_quit();
593 }
594
595 static void test_pci_retry_flush(void)
596 {
597 test_retry_flush("pc");
598 }
599
600 static void test_isa_retry_flush(void)
601 {
602 test_retry_flush("isapc");
603 }
604
605 typedef struct Read10CDB {
606 uint8_t opcode;
607 uint8_t flags;
608 uint32_t lba;
609 uint8_t reserved;
610 uint16_t nblocks;
611 uint8_t control;
612 uint16_t padding;
613 } __attribute__((__packed__)) Read10CDB;
614
615 static void send_scsi_cdb_read10(uint64_t lba, int nblocks)
616 {
617 Read10CDB pkt = { .padding = 0 };
618 int i;
619
620 g_assert_cmpint(lba, <=, UINT32_MAX);
621 g_assert_cmpint(nblocks, <=, UINT16_MAX);
622 g_assert_cmpint(nblocks, >=, 0);
623
624 /* Construct SCSI CDB packet */
625 pkt.opcode = 0x28;
626 pkt.lba = cpu_to_be32(lba);
627 pkt.nblocks = cpu_to_be16(nblocks);
628
629 /* Send Packet */
630 for (i = 0; i < sizeof(Read10CDB)/2; i++) {
631 outw(IDE_BASE + reg_data, cpu_to_le16(((uint16_t *)&pkt)[i]));
632 }
633 }
634
635 static void nsleep(int64_t nsecs)
636 {
637 const struct timespec val = { .tv_nsec = nsecs };
638 nanosleep(&val, NULL);
639 clock_set(nsecs);
640 }
641
642 static uint8_t ide_wait_clear(uint8_t flag)
643 {
644 uint8_t data;
645 time_t st;
646
647 /* Wait with a 5 second timeout */
648 time(&st);
649 while (true) {
650 data = inb(IDE_BASE + reg_status);
651 if (!(data & flag)) {
652 return data;
653 }
654 if (difftime(time(NULL), st) > 5.0) {
655 break;
656 }
657 nsleep(400);
658 }
659 g_assert_not_reached();
660 }
661
662 static void ide_wait_intr(int irq)
663 {
664 time_t st;
665 bool intr;
666
667 time(&st);
668 while (true) {
669 intr = get_irq(irq);
670 if (intr) {
671 return;
672 }
673 if (difftime(time(NULL), st) > 5.0) {
674 break;
675 }
676 nsleep(400);
677 }
678
679 g_assert_not_reached();
680 }
681
682 static void cdrom_pio_impl(int nblocks)
683 {
684 FILE *fh;
685 int patt_blocks = MAX(16, nblocks);
686 size_t patt_len = ATAPI_BLOCK_SIZE * patt_blocks;
687 char *pattern = g_malloc(patt_len);
688 size_t rxsize = ATAPI_BLOCK_SIZE * nblocks;
689 uint16_t *rx = g_malloc0(rxsize);
690 int i, j;
691 uint8_t data;
692 uint16_t limit;
693
694 /* Prepopulate the CDROM with an interesting pattern */
695 generate_pattern(pattern, patt_len, ATAPI_BLOCK_SIZE);
696 fh = fopen(tmp_path, "w+");
697 fwrite(pattern, ATAPI_BLOCK_SIZE, patt_blocks, fh);
698 fclose(fh);
699
700 ide_test_start("-drive if=none,file=%s,media=cdrom,format=raw,id=sr0,index=0 "
701 "-device ide-cd,drive=sr0,bus=ide.0", tmp_path);
702 qtest_irq_intercept_in(global_qtest, "ioapic");
703
704 /* PACKET command on device 0 */
705 outb(IDE_BASE + reg_device, 0);
706 outb(IDE_BASE + reg_lba_middle, BYTE_COUNT_LIMIT & 0xFF);
707 outb(IDE_BASE + reg_lba_high, (BYTE_COUNT_LIMIT >> 8 & 0xFF));
708 outb(IDE_BASE + reg_command, CMD_PACKET);
709 /* HP0: Check_Status_A State */
710 nsleep(400);
711 data = ide_wait_clear(BSY);
712 /* HP1: Send_Packet State */
713 assert_bit_set(data, DRQ | DRDY);
714 assert_bit_clear(data, ERR | DF | BSY);
715
716 /* SCSI CDB (READ10) -- read n*2048 bytes from block 0 */
717 send_scsi_cdb_read10(0, nblocks);
718
719 /* Read data back: occurs in bursts of 'BYTE_COUNT_LIMIT' bytes.
720 * If BYTE_COUNT_LIMIT is odd, we transfer BYTE_COUNT_LIMIT - 1 bytes.
721 * We allow an odd limit only when the remaining transfer size is
722 * less than BYTE_COUNT_LIMIT. However, SCSI's read10 command can only
723 * request n blocks, so our request size is always even.
724 * For this reason, we assume there is never a hanging byte to fetch. */
725 g_assert(!(rxsize & 1));
726 limit = BYTE_COUNT_LIMIT & ~1;
727 for (i = 0; i < DIV_ROUND_UP(rxsize, limit); i++) {
728 size_t offset = i * (limit / 2);
729 size_t rem = (rxsize / 2) - offset;
730
731 /* HP3: INTRQ_Wait */
732 ide_wait_intr(IDE_PRIMARY_IRQ);
733
734 /* HP2: Check_Status_B (and clear IRQ) */
735 data = ide_wait_clear(BSY);
736 assert_bit_set(data, DRQ | DRDY);
737 assert_bit_clear(data, ERR | DF | BSY);
738
739 /* HP4: Transfer_Data */
740 for (j = 0; j < MIN((limit / 2), rem); j++) {
741 rx[offset + j] = le16_to_cpu(inw(IDE_BASE + reg_data));
742 }
743 }
744
745 /* Check for final completion IRQ */
746 ide_wait_intr(IDE_PRIMARY_IRQ);
747
748 /* Sanity check final state */
749 data = ide_wait_clear(DRQ);
750 assert_bit_set(data, DRDY);
751 assert_bit_clear(data, DRQ | ERR | DF | BSY);
752
753 g_assert_cmpint(memcmp(pattern, rx, rxsize), ==, 0);
754 g_free(pattern);
755 g_free(rx);
756 test_bmdma_teardown();
757 }
758
759 static void test_cdrom_pio(void)
760 {
761 cdrom_pio_impl(1);
762 }
763
764 static void test_cdrom_pio_large(void)
765 {
766 /* Test a few loops of the PIO DRQ mechanism. */
767 cdrom_pio_impl(BYTE_COUNT_LIMIT * 4 / ATAPI_BLOCK_SIZE);
768 }
769
770
771 static void test_cdrom_dma(void)
772 {
773 static const size_t len = ATAPI_BLOCK_SIZE;
774 char *pattern = g_malloc(ATAPI_BLOCK_SIZE * 16);
775 char *rx = g_malloc0(len);
776 uintptr_t guest_buf;
777 PrdtEntry prdt[1];
778 FILE *fh;
779
780 ide_test_start("-drive if=none,file=%s,media=cdrom,format=raw,id=sr0,index=0 "
781 "-device ide-cd,drive=sr0,bus=ide.0", tmp_path);
782 qtest_irq_intercept_in(global_qtest, "ioapic");
783
784 guest_buf = guest_alloc(guest_malloc, len);
785 prdt[0].addr = cpu_to_le32(guest_buf);
786 prdt[0].size = cpu_to_le32(len | PRDT_EOT);
787
788 generate_pattern(pattern, ATAPI_BLOCK_SIZE * 16, ATAPI_BLOCK_SIZE);
789 fh = fopen(tmp_path, "w+");
790 fwrite(pattern, ATAPI_BLOCK_SIZE, 16, fh);
791 fclose(fh);
792
793 send_dma_request(CMD_PACKET, 0, 1, prdt, 1, send_scsi_cdb_read10);
794
795 /* Read back data from guest memory into local qtest memory */
796 memread(guest_buf, rx, len);
797 g_assert_cmpint(memcmp(pattern, rx, len), ==, 0);
798
799 g_free(pattern);
800 g_free(rx);
801 test_bmdma_teardown();
802 }
803
804 int main(int argc, char **argv)
805 {
806 const char *arch = qtest_get_arch();
807 int fd;
808 int ret;
809
810 /* Check architecture */
811 if (strcmp(arch, "i386") && strcmp(arch, "x86_64")) {
812 g_test_message("Skipping test for non-x86\n");
813 return 0;
814 }
815
816 /* Create temporary blkdebug instructions */
817 fd = mkstemp(debug_path);
818 g_assert(fd >= 0);
819 close(fd);
820
821 /* Create a temporary raw image */
822 fd = mkstemp(tmp_path);
823 g_assert(fd >= 0);
824 ret = ftruncate(fd, TEST_IMAGE_SIZE);
825 g_assert(ret == 0);
826 close(fd);
827
828 /* Run the tests */
829 g_test_init(&argc, &argv, NULL);
830
831 qtest_add_func("/ide/identify", test_identify);
832
833 qtest_add_func("/ide/bmdma/setup", test_bmdma_setup);
834 qtest_add_func("/ide/bmdma/simple_rw", test_bmdma_simple_rw);
835 qtest_add_func("/ide/bmdma/short_prdt", test_bmdma_short_prdt);
836 qtest_add_func("/ide/bmdma/one_sector_short_prdt",
837 test_bmdma_one_sector_short_prdt);
838 qtest_add_func("/ide/bmdma/long_prdt", test_bmdma_long_prdt);
839 qtest_add_func("/ide/bmdma/no_busmaster", test_bmdma_no_busmaster);
840 qtest_add_func("/ide/bmdma/teardown", test_bmdma_teardown);
841
842 qtest_add_func("/ide/flush", test_flush);
843 qtest_add_func("/ide/flush/nodev", test_flush_nodev);
844 qtest_add_func("/ide/flush/retry_pci", test_pci_retry_flush);
845 qtest_add_func("/ide/flush/retry_isa", test_isa_retry_flush);
846
847 qtest_add_func("/ide/cdrom/pio", test_cdrom_pio);
848 qtest_add_func("/ide/cdrom/pio_large", test_cdrom_pio_large);
849 qtest_add_func("/ide/cdrom/dma", test_cdrom_dma);
850
851 ret = g_test_run();
852
853 /* Cleanup */
854 unlink(tmp_path);
855 unlink(debug_path);
856
857 return ret;
858 }