cirrus: fix off-by-one in cirrus_bitblt_rop_bkwd_transp_*_16
[qemu.git] / tests / ivshmem-test.c
1 /*
2 * QTest testcase for ivshmem
3 *
4 * Copyright (c) 2014 SUSE LINUX Products GmbH
5 * Copyright (c) 2015 Red Hat, Inc.
6 *
7 * This work is licensed under the terms of the GNU GPL, version 2 or later.
8 * See the COPYING file in the top-level directory.
9 */
10
11 #include "qemu/osdep.h"
12 #include <glib/gstdio.h>
13 #include "contrib/ivshmem-server/ivshmem-server.h"
14 #include "libqos/libqos-pc.h"
15 #include "libqos/libqos-spapr.h"
16 #include "libqtest.h"
17 #include "qemu-common.h"
18
19 #define TMPSHMSIZE (1 << 20)
20 static char *tmpshm;
21 static void *tmpshmem;
22 static char *tmpdir;
23 static char *tmpserver;
24
25 static void save_fn(QPCIDevice *dev, int devfn, void *data)
26 {
27 QPCIDevice **pdev = (QPCIDevice **) data;
28
29 *pdev = dev;
30 }
31
32 static QPCIDevice *get_device(QPCIBus *pcibus)
33 {
34 QPCIDevice *dev;
35
36 dev = NULL;
37 qpci_device_foreach(pcibus, 0x1af4, 0x1110, save_fn, &dev);
38 g_assert(dev != NULL);
39
40 return dev;
41 }
42
43 typedef struct _IVState {
44 QOSState *qs;
45 QPCIBar reg_bar, mem_bar;
46 QPCIDevice *dev;
47 } IVState;
48
49 enum Reg {
50 INTRMASK = 0,
51 INTRSTATUS = 4,
52 IVPOSITION = 8,
53 DOORBELL = 12,
54 };
55
56 static const char* reg2str(enum Reg reg) {
57 switch (reg) {
58 case INTRMASK:
59 return "IntrMask";
60 case INTRSTATUS:
61 return "IntrStatus";
62 case IVPOSITION:
63 return "IVPosition";
64 case DOORBELL:
65 return "DoorBell";
66 default:
67 return NULL;
68 }
69 }
70
71 static inline unsigned in_reg(IVState *s, enum Reg reg)
72 {
73 const char *name = reg2str(reg);
74 QTestState *qtest = global_qtest;
75 unsigned res;
76
77 global_qtest = s->qs->qts;
78 res = qpci_io_readl(s->dev, s->reg_bar, reg);
79 g_test_message("*%s -> %x\n", name, res);
80 global_qtest = qtest;
81
82 return res;
83 }
84
85 static inline void out_reg(IVState *s, enum Reg reg, unsigned v)
86 {
87 const char *name = reg2str(reg);
88 QTestState *qtest = global_qtest;
89
90 global_qtest = s->qs->qts;
91 g_test_message("%x -> *%s\n", v, name);
92 qpci_io_writel(s->dev, s->reg_bar, reg, v);
93 global_qtest = qtest;
94 }
95
96 static inline void read_mem(IVState *s, uint64_t off, void *buf, size_t len)
97 {
98 QTestState *qtest = global_qtest;
99
100 global_qtest = s->qs->qts;
101 qpci_memread(s->dev, s->mem_bar, off, buf, len);
102 global_qtest = qtest;
103 }
104
105 static inline void write_mem(IVState *s, uint64_t off,
106 const void *buf, size_t len)
107 {
108 QTestState *qtest = global_qtest;
109
110 global_qtest = s->qs->qts;
111 qpci_memwrite(s->dev, s->mem_bar, off, buf, len);
112 global_qtest = qtest;
113 }
114
115 static void cleanup_vm(IVState *s)
116 {
117 g_free(s->dev);
118 qtest_shutdown(s->qs);
119 }
120
121 static void setup_vm_cmd(IVState *s, const char *cmd, bool msix)
122 {
123 uint64_t barsize;
124 const char *arch = qtest_get_arch();
125
126 if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) {
127 s->qs = qtest_pc_boot(cmd);
128 } else if (strcmp(arch, "ppc64") == 0) {
129 s->qs = qtest_spapr_boot(cmd);
130 } else {
131 g_printerr("ivshmem-test tests are only available on x86 or ppc64\n");
132 exit(EXIT_FAILURE);
133 }
134 s->dev = get_device(s->qs->pcibus);
135
136 s->reg_bar = qpci_iomap(s->dev, 0, &barsize);
137 g_assert_cmpuint(barsize, ==, 256);
138
139 if (msix) {
140 qpci_msix_enable(s->dev);
141 }
142
143 s->mem_bar = qpci_iomap(s->dev, 2, &barsize);
144 g_assert_cmpuint(barsize, ==, TMPSHMSIZE);
145
146 qpci_device_enable(s->dev);
147 }
148
149 static void setup_vm(IVState *s)
150 {
151 char *cmd = g_strdup_printf("-object memory-backend-file"
152 ",id=mb1,size=1M,share,mem-path=/dev/shm%s"
153 " -device ivshmem-plain,memdev=mb1", tmpshm);
154
155 setup_vm_cmd(s, cmd, false);
156
157 g_free(cmd);
158 }
159
160 static void test_ivshmem_single(void)
161 {
162 IVState state, *s;
163 uint32_t data[1024];
164 int i;
165
166 setup_vm(&state);
167 s = &state;
168
169 /* initial state of readable registers */
170 g_assert_cmpuint(in_reg(s, INTRMASK), ==, 0);
171 g_assert_cmpuint(in_reg(s, INTRSTATUS), ==, 0);
172 g_assert_cmpuint(in_reg(s, IVPOSITION), ==, 0);
173
174 /* trigger interrupt via registers */
175 out_reg(s, INTRMASK, 0xffffffff);
176 g_assert_cmpuint(in_reg(s, INTRMASK), ==, 0xffffffff);
177 out_reg(s, INTRSTATUS, 1);
178 /* check interrupt status */
179 g_assert_cmpuint(in_reg(s, INTRSTATUS), ==, 1);
180 /* reading clears */
181 g_assert_cmpuint(in_reg(s, INTRSTATUS), ==, 0);
182 /* TODO intercept actual interrupt (needs qtest work) */
183
184 /* invalid register access */
185 out_reg(s, IVPOSITION, 1);
186 in_reg(s, DOORBELL);
187
188 /* ring the (non-functional) doorbell */
189 out_reg(s, DOORBELL, 8 << 16);
190
191 /* write shared memory */
192 for (i = 0; i < G_N_ELEMENTS(data); i++) {
193 data[i] = i;
194 }
195 write_mem(s, 0, data, sizeof(data));
196
197 /* verify write */
198 for (i = 0; i < G_N_ELEMENTS(data); i++) {
199 g_assert_cmpuint(((uint32_t *)tmpshmem)[i], ==, i);
200 }
201
202 /* read it back and verify read */
203 memset(data, 0, sizeof(data));
204 read_mem(s, 0, data, sizeof(data));
205 for (i = 0; i < G_N_ELEMENTS(data); i++) {
206 g_assert_cmpuint(data[i], ==, i);
207 }
208
209 cleanup_vm(s);
210 }
211
212 static void test_ivshmem_pair(void)
213 {
214 IVState state1, state2, *s1, *s2;
215 char *data;
216 int i;
217
218 setup_vm(&state1);
219 s1 = &state1;
220 setup_vm(&state2);
221 s2 = &state2;
222
223 data = g_malloc0(TMPSHMSIZE);
224
225 /* host write, guest 1 & 2 read */
226 memset(tmpshmem, 0x42, TMPSHMSIZE);
227 read_mem(s1, 0, data, TMPSHMSIZE);
228 for (i = 0; i < TMPSHMSIZE; i++) {
229 g_assert_cmpuint(data[i], ==, 0x42);
230 }
231 read_mem(s2, 0, data, TMPSHMSIZE);
232 for (i = 0; i < TMPSHMSIZE; i++) {
233 g_assert_cmpuint(data[i], ==, 0x42);
234 }
235
236 /* guest 1 write, guest 2 read */
237 memset(data, 0x43, TMPSHMSIZE);
238 write_mem(s1, 0, data, TMPSHMSIZE);
239 memset(data, 0, TMPSHMSIZE);
240 read_mem(s2, 0, data, TMPSHMSIZE);
241 for (i = 0; i < TMPSHMSIZE; i++) {
242 g_assert_cmpuint(data[i], ==, 0x43);
243 }
244
245 /* guest 2 write, guest 1 read */
246 memset(data, 0x44, TMPSHMSIZE);
247 write_mem(s2, 0, data, TMPSHMSIZE);
248 memset(data, 0, TMPSHMSIZE);
249 read_mem(s1, 0, data, TMPSHMSIZE);
250 for (i = 0; i < TMPSHMSIZE; i++) {
251 g_assert_cmpuint(data[i], ==, 0x44);
252 }
253
254 cleanup_vm(s1);
255 cleanup_vm(s2);
256 g_free(data);
257 }
258
259 typedef struct ServerThread {
260 GThread *thread;
261 IvshmemServer *server;
262 int pipe[2]; /* to handle quit */
263 } ServerThread;
264
265 static void *server_thread(void *data)
266 {
267 ServerThread *t = data;
268 IvshmemServer *server = t->server;
269
270 while (true) {
271 fd_set fds;
272 int maxfd, ret;
273
274 FD_ZERO(&fds);
275 FD_SET(t->pipe[0], &fds);
276 maxfd = t->pipe[0] + 1;
277
278 ivshmem_server_get_fds(server, &fds, &maxfd);
279
280 ret = select(maxfd, &fds, NULL, NULL, NULL);
281
282 if (ret < 0) {
283 if (errno == EINTR) {
284 continue;
285 }
286
287 g_critical("select error: %s\n", strerror(errno));
288 break;
289 }
290 if (ret == 0) {
291 continue;
292 }
293
294 if (FD_ISSET(t->pipe[0], &fds)) {
295 break;
296 }
297
298 if (ivshmem_server_handle_fds(server, &fds, maxfd) < 0) {
299 g_critical("ivshmem_server_handle_fds() failed\n");
300 break;
301 }
302 }
303
304 return NULL;
305 }
306
307 static void setup_vm_with_server(IVState *s, int nvectors, bool msi)
308 {
309 char *cmd = g_strdup_printf("-chardev socket,id=chr0,path=%s,nowait "
310 "-device ivshmem%s,chardev=chr0,vectors=%d",
311 tmpserver,
312 msi ? "-doorbell" : ",size=1M,msi=off",
313 nvectors);
314
315 setup_vm_cmd(s, cmd, msi);
316
317 g_free(cmd);
318 }
319
320 static void test_ivshmem_server(bool msi)
321 {
322 IVState state1, state2, *s1, *s2;
323 ServerThread thread;
324 IvshmemServer server;
325 int ret, vm1, vm2;
326 int nvectors = 2;
327 guint64 end_time = g_get_monotonic_time() + 5 * G_TIME_SPAN_SECOND;
328
329 ret = ivshmem_server_init(&server, tmpserver, tmpshm, true,
330 TMPSHMSIZE, nvectors,
331 g_test_verbose());
332 g_assert_cmpint(ret, ==, 0);
333
334 ret = ivshmem_server_start(&server);
335 g_assert_cmpint(ret, ==, 0);
336
337 thread.server = &server;
338 ret = pipe(thread.pipe);
339 g_assert_cmpint(ret, ==, 0);
340 thread.thread = g_thread_new("ivshmem-server", server_thread, &thread);
341 g_assert(thread.thread != NULL);
342
343 setup_vm_with_server(&state1, nvectors, msi);
344 s1 = &state1;
345 setup_vm_with_server(&state2, nvectors, msi);
346 s2 = &state2;
347
348 /* check got different VM ids */
349 vm1 = in_reg(s1, IVPOSITION);
350 vm2 = in_reg(s2, IVPOSITION);
351 g_assert_cmpint(vm1, >=, 0);
352 g_assert_cmpint(vm2, >=, 0);
353 g_assert_cmpint(vm1, !=, vm2);
354
355 /* check number of MSI-X vectors */
356 global_qtest = s1->qs->qts;
357 if (msi) {
358 ret = qpci_msix_table_size(s1->dev);
359 g_assert_cmpuint(ret, ==, nvectors);
360 }
361
362 /* TODO test behavior before MSI-X is enabled */
363
364 /* ping vm2 -> vm1 on vector 0 */
365 if (msi) {
366 ret = qpci_msix_pending(s1->dev, 0);
367 g_assert_cmpuint(ret, ==, 0);
368 } else {
369 g_assert_cmpuint(in_reg(s1, INTRSTATUS), ==, 0);
370 }
371 out_reg(s2, DOORBELL, vm1 << 16);
372 do {
373 g_usleep(10000);
374 ret = msi ? qpci_msix_pending(s1->dev, 0) : in_reg(s1, INTRSTATUS);
375 } while (ret == 0 && g_get_monotonic_time() < end_time);
376 g_assert_cmpuint(ret, !=, 0);
377
378 /* ping vm1 -> vm2 on vector 1 */
379 global_qtest = s2->qs->qts;
380 if (msi) {
381 ret = qpci_msix_pending(s2->dev, 1);
382 g_assert_cmpuint(ret, ==, 0);
383 } else {
384 g_assert_cmpuint(in_reg(s2, INTRSTATUS), ==, 0);
385 }
386 out_reg(s1, DOORBELL, vm2 << 16 | 1);
387 do {
388 g_usleep(10000);
389 ret = msi ? qpci_msix_pending(s2->dev, 1) : in_reg(s2, INTRSTATUS);
390 } while (ret == 0 && g_get_monotonic_time() < end_time);
391 g_assert_cmpuint(ret, !=, 0);
392
393 cleanup_vm(s2);
394 cleanup_vm(s1);
395
396 if (qemu_write_full(thread.pipe[1], "q", 1) != 1) {
397 g_error("qemu_write_full: %s", g_strerror(errno));
398 }
399
400 g_thread_join(thread.thread);
401
402 ivshmem_server_close(&server);
403 close(thread.pipe[1]);
404 close(thread.pipe[0]);
405 }
406
407 static void test_ivshmem_server_msi(void)
408 {
409 test_ivshmem_server(true);
410 }
411
412 static void test_ivshmem_server_irq(void)
413 {
414 test_ivshmem_server(false);
415 }
416
417 #define PCI_SLOT_HP 0x06
418
419 static void test_ivshmem_hotplug(void)
420 {
421 const char *arch = qtest_get_arch();
422 gchar *opts;
423
424 qtest_start("");
425
426 opts = g_strdup_printf("'shm': '%s', 'size': '1M'", tmpshm);
427
428 qpci_plug_device_test("ivshmem", "iv1", PCI_SLOT_HP, opts);
429 if (strcmp(arch, "ppc64") != 0) {
430 qpci_unplug_acpi_device_test("iv1", PCI_SLOT_HP);
431 }
432
433 qtest_end();
434 g_free(opts);
435 }
436
437 static void test_ivshmem_memdev(void)
438 {
439 IVState state;
440
441 /* just for the sake of checking memory-backend property */
442 setup_vm_cmd(&state, "-object memory-backend-ram,size=1M,id=mb1"
443 " -device ivshmem-plain,memdev=mb1", false);
444
445 cleanup_vm(&state);
446 }
447
448 static void cleanup(void)
449 {
450 if (tmpshmem) {
451 munmap(tmpshmem, TMPSHMSIZE);
452 tmpshmem = NULL;
453 }
454
455 if (tmpshm) {
456 shm_unlink(tmpshm);
457 g_free(tmpshm);
458 tmpshm = NULL;
459 }
460
461 if (tmpserver) {
462 g_unlink(tmpserver);
463 g_free(tmpserver);
464 tmpserver = NULL;
465 }
466
467 if (tmpdir) {
468 g_rmdir(tmpdir);
469 tmpdir = NULL;
470 }
471 }
472
473 static void abrt_handler(void *data)
474 {
475 cleanup();
476 }
477
478 static gchar *mktempshm(int size, int *fd)
479 {
480 while (true) {
481 gchar *name;
482
483 name = g_strdup_printf("/qtest-%u-%u", getpid(), g_random_int());
484 *fd = shm_open(name, O_CREAT|O_RDWR|O_EXCL,
485 S_IRWXU|S_IRWXG|S_IRWXO);
486 if (*fd > 0) {
487 g_assert(ftruncate(*fd, size) == 0);
488 return name;
489 }
490
491 g_free(name);
492
493 if (errno != EEXIST) {
494 perror("shm_open");
495 return NULL;
496 }
497 }
498 }
499
500 int main(int argc, char **argv)
501 {
502 int ret, fd;
503 const char *arch = qtest_get_arch();
504 gchar dir[] = "/tmp/ivshmem-test.XXXXXX";
505
506 #if !GLIB_CHECK_VERSION(2, 31, 0)
507 if (!g_thread_supported()) {
508 g_thread_init(NULL);
509 }
510 #endif
511
512 g_test_init(&argc, &argv, NULL);
513
514 qtest_add_abrt_handler(abrt_handler, NULL);
515 /* shm */
516 tmpshm = mktempshm(TMPSHMSIZE, &fd);
517 if (!tmpshm) {
518 return 0;
519 }
520 tmpshmem = mmap(0, TMPSHMSIZE, PROT_READ|PROT_WRITE, MAP_SHARED, fd, 0);
521 g_assert(tmpshmem != MAP_FAILED);
522 /* server */
523 if (mkdtemp(dir) == NULL) {
524 g_error("mkdtemp: %s", g_strerror(errno));
525 }
526 tmpdir = dir;
527 tmpserver = g_strconcat(tmpdir, "/server", NULL);
528
529 qtest_add_func("/ivshmem/single", test_ivshmem_single);
530 qtest_add_func("/ivshmem/hotplug", test_ivshmem_hotplug);
531 qtest_add_func("/ivshmem/memdev", test_ivshmem_memdev);
532 if (g_test_slow()) {
533 qtest_add_func("/ivshmem/pair", test_ivshmem_pair);
534 if (strcmp(arch, "ppc64") != 0) {
535 qtest_add_func("/ivshmem/server-msi", test_ivshmem_server_msi);
536 qtest_add_func("/ivshmem/server-irq", test_ivshmem_server_irq);
537 }
538 }
539
540 ret = g_test_run();
541
542 cleanup();
543
544 return ret;
545 }