cirrus: fix off-by-one in cirrus_bitblt_rop_bkwd_transp_*_16
[qemu.git] / tests / pnv-xscom-test.c
1 /*
2 * QTest testcase for PowerNV XSCOM bus
3 *
4 * Copyright (c) 2016, IBM Corporation.
5 *
6 * This work is licensed under the terms of the GNU GPL, version 2 or
7 * later. See the COPYING file in the top-level directory.
8 */
9 #include "qemu/osdep.h"
10
11 #include "libqtest.h"
12
13 typedef enum PnvChipType {
14 PNV_CHIP_POWER8E, /* AKA Murano (default) */
15 PNV_CHIP_POWER8, /* AKA Venice */
16 PNV_CHIP_POWER8NVL, /* AKA Naples */
17 PNV_CHIP_POWER9, /* AKA Nimbus */
18 } PnvChipType;
19
20 typedef struct PnvChip {
21 PnvChipType chip_type;
22 const char *cpu_model;
23 uint64_t xscom_base;
24 uint64_t xscom_core_base;
25 uint64_t cfam_id;
26 uint32_t first_core;
27 } PnvChip;
28
29 static const PnvChip pnv_chips[] = {
30 {
31 .chip_type = PNV_CHIP_POWER8,
32 .cpu_model = "POWER8",
33 .xscom_base = 0x0003fc0000000000ull,
34 .xscom_core_base = 0x10000000ull,
35 .cfam_id = 0x220ea04980000000ull,
36 .first_core = 0x1,
37 }, {
38 .chip_type = PNV_CHIP_POWER8NVL,
39 .cpu_model = "POWER8NVL",
40 .xscom_base = 0x0003fc0000000000ull,
41 .xscom_core_base = 0x10000000ull,
42 .cfam_id = 0x120d304980000000ull,
43 .first_core = 0x1,
44 },
45 #if 0 /* POWER9 support is not ready yet */
46 {
47 .chip_type = PNV_CHIP_POWER9,
48 .cpu_model = "POWER9",
49 .xscom_base = 0x000603fc00000000ull,
50 .xscom_core_base = 0x0ull,
51 .cfam_id = 0x100d104980000000ull,
52 .first_core = 0x20,
53 },
54 #endif
55 };
56
57 static uint64_t pnv_xscom_addr(const PnvChip *chip, uint32_t pcba)
58 {
59 uint64_t addr = chip->xscom_base;
60
61 if (chip->chip_type == PNV_CHIP_POWER9) {
62 addr |= ((uint64_t) pcba << 3);
63 } else {
64 addr |= (((uint64_t) pcba << 4) & ~0xffull) |
65 (((uint64_t) pcba << 3) & 0x78);
66 }
67 return addr;
68 }
69
70 static uint64_t pnv_xscom_read(const PnvChip *chip, uint32_t pcba)
71 {
72 return readq(pnv_xscom_addr(chip, pcba));
73 }
74
75 static void test_xscom_cfam_id(const PnvChip *chip)
76 {
77 uint64_t f000f = pnv_xscom_read(chip, 0xf000f);
78
79 g_assert_cmphex(f000f, ==, chip->cfam_id);
80 }
81
82 static void test_cfam_id(const void *data)
83 {
84 char *args;
85 const PnvChip *chip = data;
86
87 args = g_strdup_printf("-M powernv,accel=tcg -cpu %s", chip->cpu_model);
88
89 qtest_start(args);
90 test_xscom_cfam_id(chip);
91 qtest_quit(global_qtest);
92
93 g_free(args);
94 }
95
96 #define PNV_XSCOM_EX_CORE_BASE(chip, i) \
97 ((chip)->xscom_core_base | (((uint64_t)i) << 24))
98 #define PNV_XSCOM_EX_DTS_RESULT0 0x50000
99
100 static void test_xscom_core(const PnvChip *chip)
101 {
102 uint32_t first_core_dts0 =
103 PNV_XSCOM_EX_CORE_BASE(chip, chip->first_core) |
104 PNV_XSCOM_EX_DTS_RESULT0;
105 uint64_t dts0 = pnv_xscom_read(chip, first_core_dts0);
106
107 g_assert_cmphex(dts0, ==, 0x26f024f023f0000ull);
108 }
109
110 static void test_core(const void *data)
111 {
112 char *args;
113 const PnvChip *chip = data;
114
115 args = g_strdup_printf("-M powernv,accel=tcg -cpu %s", chip->cpu_model);
116
117 qtest_start(args);
118 test_xscom_core(chip);
119 qtest_quit(global_qtest);
120
121 g_free(args);
122 }
123
124 static void add_test(const char *name, void (*test)(const void *data))
125 {
126 int i;
127
128 for (i = 0; i < ARRAY_SIZE(pnv_chips); i++) {
129 char *tname = g_strdup_printf("pnv-xscom/%s/%s", name,
130 pnv_chips[i].cpu_model);
131 qtest_add_data_func(tname, &pnv_chips[i], test);
132 g_free(tname);
133 }
134 }
135
136 int main(int argc, char **argv)
137 {
138 g_test_init(&argc, &argv, NULL);
139
140 add_test("cfam_id", test_cfam_id);
141 add_test("core", test_core);
142 return g_test_run();
143 }