nbd: Don't use *_to_cpup() functions
[qemu.git] / user-exec.c
1 /*
2 * User emulator execution
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include "cpu.h"
21 #include "disas/disas.h"
22 #include "exec/exec-all.h"
23 #include "tcg.h"
24 #include "qemu/bitops.h"
25 #include "exec/cpu_ldst.h"
26 #include "translate-all.h"
27
28 #undef EAX
29 #undef ECX
30 #undef EDX
31 #undef EBX
32 #undef ESP
33 #undef EBP
34 #undef ESI
35 #undef EDI
36 #undef EIP
37 #ifdef __linux__
38 #include <sys/ucontext.h>
39 #endif
40
41 //#define DEBUG_SIGNAL
42
43 /* exit the current TB from a signal handler. The host registers are
44 restored in a state compatible with the CPU emulator
45 */
46 static void cpu_exit_tb_from_sighandler(CPUState *cpu, sigset_t *old_set)
47 {
48 /* XXX: use siglongjmp ? */
49 sigprocmask(SIG_SETMASK, old_set, NULL);
50 cpu_loop_exit_noexc(cpu);
51 }
52
53 /* 'pc' is the host PC at which the exception was raised. 'address' is
54 the effective address of the memory exception. 'is_write' is 1 if a
55 write caused the exception and otherwise 0'. 'old_set' is the
56 signal set which should be restored */
57 static inline int handle_cpu_signal(uintptr_t pc, unsigned long address,
58 int is_write, sigset_t *old_set)
59 {
60 CPUState *cpu;
61 CPUClass *cc;
62 int ret;
63
64 #if defined(DEBUG_SIGNAL)
65 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
66 pc, address, is_write, *(unsigned long *)old_set);
67 #endif
68 /* XXX: locking issue */
69 if (is_write && h2g_valid(address)) {
70 switch (page_unprotect(h2g(address), pc)) {
71 case 0:
72 /* Fault not caused by a page marked unwritable to protect
73 * cached translations, must be the guest binary's problem
74 */
75 break;
76 case 1:
77 /* Fault caused by protection of cached translation; TBs
78 * invalidated, so resume execution
79 */
80 return 1;
81 case 2:
82 /* Fault caused by protection of cached translation, and the
83 * currently executing TB was modified and must be exited
84 * immediately.
85 */
86 cpu_exit_tb_from_sighandler(current_cpu, old_set);
87 g_assert_not_reached();
88 default:
89 g_assert_not_reached();
90 }
91 }
92
93 /* Convert forcefully to guest address space, invalid addresses
94 are still valid segv ones */
95 address = h2g_nocheck(address);
96
97 cpu = current_cpu;
98 cc = CPU_GET_CLASS(cpu);
99 /* see if it is an MMU fault */
100 g_assert(cc->handle_mmu_fault);
101 ret = cc->handle_mmu_fault(cpu, address, is_write, MMU_USER_IDX);
102 if (ret < 0) {
103 return 0; /* not an MMU fault */
104 }
105 if (ret == 0) {
106 return 1; /* the MMU fault was handled without causing real CPU fault */
107 }
108 /* now we have a real cpu fault */
109 cpu_restore_state(cpu, pc);
110
111 sigprocmask(SIG_SETMASK, old_set, NULL);
112 cpu_loop_exit(cpu);
113
114 /* never comes here */
115 return 1;
116 }
117
118 #if defined(__i386__)
119
120 #if defined(__APPLE__)
121 #include <sys/ucontext.h>
122
123 #define EIP_sig(context) (*((unsigned long *)&(context)->uc_mcontext->ss.eip))
124 #define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
125 #define ERROR_sig(context) ((context)->uc_mcontext->es.err)
126 #define MASK_sig(context) ((context)->uc_sigmask)
127 #elif defined(__NetBSD__)
128 #include <ucontext.h>
129
130 #define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP])
131 #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
132 #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
133 #define MASK_sig(context) ((context)->uc_sigmask)
134 #elif defined(__FreeBSD__) || defined(__DragonFly__)
135 #include <ucontext.h>
136
137 #define EIP_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_eip))
138 #define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
139 #define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
140 #define MASK_sig(context) ((context)->uc_sigmask)
141 #elif defined(__OpenBSD__)
142 #define EIP_sig(context) ((context)->sc_eip)
143 #define TRAP_sig(context) ((context)->sc_trapno)
144 #define ERROR_sig(context) ((context)->sc_err)
145 #define MASK_sig(context) ((context)->sc_mask)
146 #else
147 #define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
148 #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
149 #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
150 #define MASK_sig(context) ((context)->uc_sigmask)
151 #endif
152
153 int cpu_signal_handler(int host_signum, void *pinfo,
154 void *puc)
155 {
156 siginfo_t *info = pinfo;
157 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
158 ucontext_t *uc = puc;
159 #elif defined(__OpenBSD__)
160 struct sigcontext *uc = puc;
161 #else
162 struct ucontext *uc = puc;
163 #endif
164 unsigned long pc;
165 int trapno;
166
167 #ifndef REG_EIP
168 /* for glibc 2.1 */
169 #define REG_EIP EIP
170 #define REG_ERR ERR
171 #define REG_TRAPNO TRAPNO
172 #endif
173 pc = EIP_sig(uc);
174 trapno = TRAP_sig(uc);
175 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
176 trapno == 0xe ?
177 (ERROR_sig(uc) >> 1) & 1 : 0,
178 &MASK_sig(uc));
179 }
180
181 #elif defined(__x86_64__)
182
183 #ifdef __NetBSD__
184 #define PC_sig(context) _UC_MACHINE_PC(context)
185 #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
186 #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
187 #define MASK_sig(context) ((context)->uc_sigmask)
188 #elif defined(__OpenBSD__)
189 #define PC_sig(context) ((context)->sc_rip)
190 #define TRAP_sig(context) ((context)->sc_trapno)
191 #define ERROR_sig(context) ((context)->sc_err)
192 #define MASK_sig(context) ((context)->sc_mask)
193 #elif defined(__FreeBSD__) || defined(__DragonFly__)
194 #include <ucontext.h>
195
196 #define PC_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_rip))
197 #define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
198 #define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
199 #define MASK_sig(context) ((context)->uc_sigmask)
200 #else
201 #define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP])
202 #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
203 #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
204 #define MASK_sig(context) ((context)->uc_sigmask)
205 #endif
206
207 int cpu_signal_handler(int host_signum, void *pinfo,
208 void *puc)
209 {
210 siginfo_t *info = pinfo;
211 unsigned long pc;
212 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
213 ucontext_t *uc = puc;
214 #elif defined(__OpenBSD__)
215 struct sigcontext *uc = puc;
216 #else
217 struct ucontext *uc = puc;
218 #endif
219
220 pc = PC_sig(uc);
221 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
222 TRAP_sig(uc) == 0xe ?
223 (ERROR_sig(uc) >> 1) & 1 : 0,
224 &MASK_sig(uc));
225 }
226
227 #elif defined(_ARCH_PPC)
228
229 /***********************************************************************
230 * signal context platform-specific definitions
231 * From Wine
232 */
233 #ifdef linux
234 /* All Registers access - only for local access */
235 #define REG_sig(reg_name, context) \
236 ((context)->uc_mcontext.regs->reg_name)
237 /* Gpr Registers access */
238 #define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
239 /* Program counter */
240 #define IAR_sig(context) REG_sig(nip, context)
241 /* Machine State Register (Supervisor) */
242 #define MSR_sig(context) REG_sig(msr, context)
243 /* Count register */
244 #define CTR_sig(context) REG_sig(ctr, context)
245 /* User's integer exception register */
246 #define XER_sig(context) REG_sig(xer, context)
247 /* Link register */
248 #define LR_sig(context) REG_sig(link, context)
249 /* Condition register */
250 #define CR_sig(context) REG_sig(ccr, context)
251
252 /* Float Registers access */
253 #define FLOAT_sig(reg_num, context) \
254 (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num])
255 #define FPSCR_sig(context) \
256 (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4)))
257 /* Exception Registers access */
258 #define DAR_sig(context) REG_sig(dar, context)
259 #define DSISR_sig(context) REG_sig(dsisr, context)
260 #define TRAP_sig(context) REG_sig(trap, context)
261 #endif /* linux */
262
263 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
264 #include <ucontext.h>
265 #define IAR_sig(context) ((context)->uc_mcontext.mc_srr0)
266 #define MSR_sig(context) ((context)->uc_mcontext.mc_srr1)
267 #define CTR_sig(context) ((context)->uc_mcontext.mc_ctr)
268 #define XER_sig(context) ((context)->uc_mcontext.mc_xer)
269 #define LR_sig(context) ((context)->uc_mcontext.mc_lr)
270 #define CR_sig(context) ((context)->uc_mcontext.mc_cr)
271 /* Exception Registers access */
272 #define DAR_sig(context) ((context)->uc_mcontext.mc_dar)
273 #define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr)
274 #define TRAP_sig(context) ((context)->uc_mcontext.mc_exc)
275 #endif /* __FreeBSD__|| __FreeBSD_kernel__ */
276
277 #ifdef __APPLE__
278 #include <sys/ucontext.h>
279 typedef struct ucontext SIGCONTEXT;
280 /* All Registers access - only for local access */
281 #define REG_sig(reg_name, context) \
282 ((context)->uc_mcontext->ss.reg_name)
283 #define FLOATREG_sig(reg_name, context) \
284 ((context)->uc_mcontext->fs.reg_name)
285 #define EXCEPREG_sig(reg_name, context) \
286 ((context)->uc_mcontext->es.reg_name)
287 #define VECREG_sig(reg_name, context) \
288 ((context)->uc_mcontext->vs.reg_name)
289 /* Gpr Registers access */
290 #define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
291 /* Program counter */
292 #define IAR_sig(context) REG_sig(srr0, context)
293 /* Machine State Register (Supervisor) */
294 #define MSR_sig(context) REG_sig(srr1, context)
295 #define CTR_sig(context) REG_sig(ctr, context)
296 /* Link register */
297 #define XER_sig(context) REG_sig(xer, context)
298 /* User's integer exception register */
299 #define LR_sig(context) REG_sig(lr, context)
300 /* Condition register */
301 #define CR_sig(context) REG_sig(cr, context)
302 /* Float Registers access */
303 #define FLOAT_sig(reg_num, context) \
304 FLOATREG_sig(fpregs[reg_num], context)
305 #define FPSCR_sig(context) \
306 ((double)FLOATREG_sig(fpscr, context))
307 /* Exception Registers access */
308 /* Fault registers for coredump */
309 #define DAR_sig(context) EXCEPREG_sig(dar, context)
310 #define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
311 /* number of powerpc exception taken */
312 #define TRAP_sig(context) EXCEPREG_sig(exception, context)
313 #endif /* __APPLE__ */
314
315 int cpu_signal_handler(int host_signum, void *pinfo,
316 void *puc)
317 {
318 siginfo_t *info = pinfo;
319 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
320 ucontext_t *uc = puc;
321 #else
322 struct ucontext *uc = puc;
323 #endif
324 unsigned long pc;
325 int is_write;
326
327 pc = IAR_sig(uc);
328 is_write = 0;
329 #if 0
330 /* ppc 4xx case */
331 if (DSISR_sig(uc) & 0x00800000) {
332 is_write = 1;
333 }
334 #else
335 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) {
336 is_write = 1;
337 }
338 #endif
339 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
340 is_write, &uc->uc_sigmask);
341 }
342
343 #elif defined(__alpha__)
344
345 int cpu_signal_handler(int host_signum, void *pinfo,
346 void *puc)
347 {
348 siginfo_t *info = pinfo;
349 struct ucontext *uc = puc;
350 uint32_t *pc = uc->uc_mcontext.sc_pc;
351 uint32_t insn = *pc;
352 int is_write = 0;
353
354 /* XXX: need kernel patch to get write flag faster */
355 switch (insn >> 26) {
356 case 0x0d: /* stw */
357 case 0x0e: /* stb */
358 case 0x0f: /* stq_u */
359 case 0x24: /* stf */
360 case 0x25: /* stg */
361 case 0x26: /* sts */
362 case 0x27: /* stt */
363 case 0x2c: /* stl */
364 case 0x2d: /* stq */
365 case 0x2e: /* stl_c */
366 case 0x2f: /* stq_c */
367 is_write = 1;
368 }
369
370 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
371 is_write, &uc->uc_sigmask);
372 }
373 #elif defined(__sparc__)
374
375 int cpu_signal_handler(int host_signum, void *pinfo,
376 void *puc)
377 {
378 siginfo_t *info = pinfo;
379 int is_write;
380 uint32_t insn;
381 #if !defined(__arch64__) || defined(CONFIG_SOLARIS)
382 uint32_t *regs = (uint32_t *)(info + 1);
383 void *sigmask = (regs + 20);
384 /* XXX: is there a standard glibc define ? */
385 unsigned long pc = regs[1];
386 #else
387 #ifdef __linux__
388 struct sigcontext *sc = puc;
389 unsigned long pc = sc->sigc_regs.tpc;
390 void *sigmask = (void *)sc->sigc_mask;
391 #elif defined(__OpenBSD__)
392 struct sigcontext *uc = puc;
393 unsigned long pc = uc->sc_pc;
394 void *sigmask = (void *)(long)uc->sc_mask;
395 #elif defined(__NetBSD__)
396 ucontext_t *uc = puc;
397 unsigned long pc = _UC_MACHINE_PC(uc);
398 void *sigmask = (void *)&uc->uc_sigmask;
399 #endif
400 #endif
401
402 /* XXX: need kernel patch to get write flag faster */
403 is_write = 0;
404 insn = *(uint32_t *)pc;
405 if ((insn >> 30) == 3) {
406 switch ((insn >> 19) & 0x3f) {
407 case 0x05: /* stb */
408 case 0x15: /* stba */
409 case 0x06: /* sth */
410 case 0x16: /* stha */
411 case 0x04: /* st */
412 case 0x14: /* sta */
413 case 0x07: /* std */
414 case 0x17: /* stda */
415 case 0x0e: /* stx */
416 case 0x1e: /* stxa */
417 case 0x24: /* stf */
418 case 0x34: /* stfa */
419 case 0x27: /* stdf */
420 case 0x37: /* stdfa */
421 case 0x26: /* stqf */
422 case 0x36: /* stqfa */
423 case 0x25: /* stfsr */
424 case 0x3c: /* casa */
425 case 0x3e: /* casxa */
426 is_write = 1;
427 break;
428 }
429 }
430 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
431 is_write, sigmask);
432 }
433
434 #elif defined(__arm__)
435
436 #if defined(__NetBSD__)
437 #include <ucontext.h>
438 #endif
439
440 int cpu_signal_handler(int host_signum, void *pinfo,
441 void *puc)
442 {
443 siginfo_t *info = pinfo;
444 #if defined(__NetBSD__)
445 ucontext_t *uc = puc;
446 #else
447 struct ucontext *uc = puc;
448 #endif
449 unsigned long pc;
450 int is_write;
451
452 #if defined(__NetBSD__)
453 pc = uc->uc_mcontext.__gregs[_REG_R15];
454 #elif defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
455 pc = uc->uc_mcontext.gregs[R15];
456 #else
457 pc = uc->uc_mcontext.arm_pc;
458 #endif
459
460 /* error_code is the FSR value, in which bit 11 is WnR (assuming a v6 or
461 * later processor; on v5 we will always report this as a read).
462 */
463 is_write = extract32(uc->uc_mcontext.error_code, 11, 1);
464 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
465 is_write,
466 &uc->uc_sigmask);
467 }
468
469 #elif defined(__aarch64__)
470
471 int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
472 {
473 siginfo_t *info = pinfo;
474 struct ucontext *uc = puc;
475 uintptr_t pc = uc->uc_mcontext.pc;
476 uint32_t insn = *(uint32_t *)pc;
477 bool is_write;
478
479 /* XXX: need kernel patch to get write flag faster. */
480 is_write = ( (insn & 0xbfff0000) == 0x0c000000 /* C3.3.1 */
481 || (insn & 0xbfe00000) == 0x0c800000 /* C3.3.2 */
482 || (insn & 0xbfdf0000) == 0x0d000000 /* C3.3.3 */
483 || (insn & 0xbfc00000) == 0x0d800000 /* C3.3.4 */
484 || (insn & 0x3f400000) == 0x08000000 /* C3.3.6 */
485 || (insn & 0x3bc00000) == 0x39000000 /* C3.3.13 */
486 || (insn & 0x3fc00000) == 0x3d800000 /* ... 128bit */
487 /* Ingore bits 10, 11 & 21, controlling indexing. */
488 || (insn & 0x3bc00000) == 0x38000000 /* C3.3.8-12 */
489 || (insn & 0x3fe00000) == 0x3c800000 /* ... 128bit */
490 /* Ignore bits 23 & 24, controlling indexing. */
491 || (insn & 0x3a400000) == 0x28000000); /* C3.3.7,14-16 */
492
493 return handle_cpu_signal(pc, (uintptr_t)info->si_addr,
494 is_write, &uc->uc_sigmask);
495 }
496
497 #elif defined(__mc68000)
498
499 int cpu_signal_handler(int host_signum, void *pinfo,
500 void *puc)
501 {
502 siginfo_t *info = pinfo;
503 struct ucontext *uc = puc;
504 unsigned long pc;
505 int is_write;
506
507 pc = uc->uc_mcontext.gregs[16];
508 /* XXX: compute is_write */
509 is_write = 0;
510 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
511 is_write,
512 &uc->uc_sigmask);
513 }
514
515 #elif defined(__ia64)
516
517 #ifndef __ISR_VALID
518 /* This ought to be in <bits/siginfo.h>... */
519 # define __ISR_VALID 1
520 #endif
521
522 int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
523 {
524 siginfo_t *info = pinfo;
525 struct ucontext *uc = puc;
526 unsigned long ip;
527 int is_write = 0;
528
529 ip = uc->uc_mcontext.sc_ip;
530 switch (host_signum) {
531 case SIGILL:
532 case SIGFPE:
533 case SIGSEGV:
534 case SIGBUS:
535 case SIGTRAP:
536 if (info->si_code && (info->si_segvflags & __ISR_VALID)) {
537 /* ISR.W (write-access) is bit 33: */
538 is_write = (info->si_isr >> 33) & 1;
539 }
540 break;
541
542 default:
543 break;
544 }
545 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
546 is_write,
547 (sigset_t *)&uc->uc_sigmask);
548 }
549
550 #elif defined(__s390__)
551
552 int cpu_signal_handler(int host_signum, void *pinfo,
553 void *puc)
554 {
555 siginfo_t *info = pinfo;
556 struct ucontext *uc = puc;
557 unsigned long pc;
558 uint16_t *pinsn;
559 int is_write = 0;
560
561 pc = uc->uc_mcontext.psw.addr;
562
563 /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead
564 of the normal 2 arguments. The 3rd argument contains the "int_code"
565 from the hardware which does in fact contain the is_write value.
566 The rt signal handler, as far as I can tell, does not give this value
567 at all. Not that we could get to it from here even if it were. */
568 /* ??? This is not even close to complete, since it ignores all
569 of the read-modify-write instructions. */
570 pinsn = (uint16_t *)pc;
571 switch (pinsn[0] >> 8) {
572 case 0x50: /* ST */
573 case 0x42: /* STC */
574 case 0x40: /* STH */
575 is_write = 1;
576 break;
577 case 0xc4: /* RIL format insns */
578 switch (pinsn[0] & 0xf) {
579 case 0xf: /* STRL */
580 case 0xb: /* STGRL */
581 case 0x7: /* STHRL */
582 is_write = 1;
583 }
584 break;
585 case 0xe3: /* RXY format insns */
586 switch (pinsn[2] & 0xff) {
587 case 0x50: /* STY */
588 case 0x24: /* STG */
589 case 0x72: /* STCY */
590 case 0x70: /* STHY */
591 case 0x8e: /* STPQ */
592 case 0x3f: /* STRVH */
593 case 0x3e: /* STRV */
594 case 0x2f: /* STRVG */
595 is_write = 1;
596 }
597 break;
598 }
599 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
600 is_write, &uc->uc_sigmask);
601 }
602
603 #elif defined(__mips__)
604
605 int cpu_signal_handler(int host_signum, void *pinfo,
606 void *puc)
607 {
608 siginfo_t *info = pinfo;
609 struct ucontext *uc = puc;
610 greg_t pc = uc->uc_mcontext.pc;
611 int is_write;
612
613 /* XXX: compute is_write */
614 is_write = 0;
615 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
616 is_write, &uc->uc_sigmask);
617 }
618
619 #elif defined(__hppa__)
620
621 int cpu_signal_handler(int host_signum, void *pinfo,
622 void *puc)
623 {
624 siginfo_t *info = pinfo;
625 struct ucontext *uc = puc;
626 unsigned long pc = uc->uc_mcontext.sc_iaoq[0];
627 uint32_t insn = *(uint32_t *)pc;
628 int is_write = 0;
629
630 /* XXX: need kernel patch to get write flag faster. */
631 switch (insn >> 26) {
632 case 0x1a: /* STW */
633 case 0x19: /* STH */
634 case 0x18: /* STB */
635 case 0x1b: /* STWM */
636 is_write = 1;
637 break;
638
639 case 0x09: /* CSTWX, FSTWX, FSTWS */
640 case 0x0b: /* CSTDX, FSTDX, FSTDS */
641 /* Distinguish from coprocessor load ... */
642 is_write = (insn >> 9) & 1;
643 break;
644
645 case 0x03:
646 switch ((insn >> 6) & 15) {
647 case 0xa: /* STWS */
648 case 0x9: /* STHS */
649 case 0x8: /* STBS */
650 case 0xe: /* STWAS */
651 case 0xc: /* STBYS */
652 is_write = 1;
653 }
654 break;
655 }
656
657 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
658 is_write, &uc->uc_sigmask);
659 }
660
661 #else
662
663 #error host CPU specific signal handler needed
664
665 #endif