ppc/pnv: Add support for POWER8+ LPC Controller
[qemu.git] / user-exec.c
1 /*
2 * User emulator execution
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "qemu/osdep.h"
20 #include "cpu.h"
21 #include "disas/disas.h"
22 #include "exec/exec-all.h"
23 #include "tcg.h"
24 #include "qemu/bitops.h"
25 #include "exec/cpu_ldst.h"
26 #include "translate-all.h"
27
28 #undef EAX
29 #undef ECX
30 #undef EDX
31 #undef EBX
32 #undef ESP
33 #undef EBP
34 #undef ESI
35 #undef EDI
36 #undef EIP
37 #ifdef __linux__
38 #include <sys/ucontext.h>
39 #endif
40
41 //#define DEBUG_SIGNAL
42
43 /* exit the current TB from a signal handler. The host registers are
44 restored in a state compatible with the CPU emulator
45 */
46 static void cpu_exit_tb_from_sighandler(CPUState *cpu, sigset_t *old_set)
47 {
48 /* XXX: use siglongjmp ? */
49 sigprocmask(SIG_SETMASK, old_set, NULL);
50 cpu_loop_exit_noexc(cpu);
51 }
52
53 /* 'pc' is the host PC at which the exception was raised. 'address' is
54 the effective address of the memory exception. 'is_write' is 1 if a
55 write caused the exception and otherwise 0'. 'old_set' is the
56 signal set which should be restored */
57 static inline int handle_cpu_signal(uintptr_t pc, unsigned long address,
58 int is_write, sigset_t *old_set)
59 {
60 CPUState *cpu = current_cpu;
61 CPUClass *cc;
62 int ret;
63
64 /* For synchronous signals we expect to be coming from the vCPU
65 * thread (so current_cpu should be valid) and either from running
66 * code or during translation which can fault as we cross pages.
67 *
68 * If neither is true then something has gone wrong and we should
69 * abort rather than try and restart the vCPU execution.
70 */
71 if (!cpu || !cpu->running) {
72 printf("qemu:%s received signal outside vCPU context @ pc=0x%"
73 PRIxPTR "\n", __func__, pc);
74 abort();
75 }
76
77 #if defined(DEBUG_SIGNAL)
78 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
79 pc, address, is_write, *(unsigned long *)old_set);
80 #endif
81 /* XXX: locking issue */
82 if (is_write && h2g_valid(address)) {
83 switch (page_unprotect(h2g(address), pc)) {
84 case 0:
85 /* Fault not caused by a page marked unwritable to protect
86 * cached translations, must be the guest binary's problem
87 */
88 break;
89 case 1:
90 /* Fault caused by protection of cached translation; TBs
91 * invalidated, so resume execution
92 */
93 return 1;
94 case 2:
95 /* Fault caused by protection of cached translation, and the
96 * currently executing TB was modified and must be exited
97 * immediately.
98 */
99 cpu_exit_tb_from_sighandler(cpu, old_set);
100 g_assert_not_reached();
101 default:
102 g_assert_not_reached();
103 }
104 }
105
106 /* Convert forcefully to guest address space, invalid addresses
107 are still valid segv ones */
108 address = h2g_nocheck(address);
109
110 cc = CPU_GET_CLASS(cpu);
111 /* see if it is an MMU fault */
112 g_assert(cc->handle_mmu_fault);
113 ret = cc->handle_mmu_fault(cpu, address, is_write, MMU_USER_IDX);
114 if (ret < 0) {
115 return 0; /* not an MMU fault */
116 }
117 if (ret == 0) {
118 return 1; /* the MMU fault was handled without causing real CPU fault */
119 }
120
121 /* Now we have a real cpu fault. Since this is the exact location of
122 * the exception, we must undo the adjustment done by cpu_restore_state
123 * for handling call return addresses. */
124 cpu_restore_state(cpu, pc + GETPC_ADJ);
125
126 sigprocmask(SIG_SETMASK, old_set, NULL);
127 cpu_loop_exit(cpu);
128
129 /* never comes here */
130 return 1;
131 }
132
133 #if defined(__i386__)
134
135 #if defined(__NetBSD__)
136 #include <ucontext.h>
137
138 #define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP])
139 #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
140 #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
141 #define MASK_sig(context) ((context)->uc_sigmask)
142 #elif defined(__FreeBSD__) || defined(__DragonFly__)
143 #include <ucontext.h>
144
145 #define EIP_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_eip))
146 #define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
147 #define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
148 #define MASK_sig(context) ((context)->uc_sigmask)
149 #elif defined(__OpenBSD__)
150 #define EIP_sig(context) ((context)->sc_eip)
151 #define TRAP_sig(context) ((context)->sc_trapno)
152 #define ERROR_sig(context) ((context)->sc_err)
153 #define MASK_sig(context) ((context)->sc_mask)
154 #else
155 #define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
156 #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
157 #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
158 #define MASK_sig(context) ((context)->uc_sigmask)
159 #endif
160
161 int cpu_signal_handler(int host_signum, void *pinfo,
162 void *puc)
163 {
164 siginfo_t *info = pinfo;
165 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
166 ucontext_t *uc = puc;
167 #elif defined(__OpenBSD__)
168 struct sigcontext *uc = puc;
169 #else
170 struct ucontext *uc = puc;
171 #endif
172 unsigned long pc;
173 int trapno;
174
175 #ifndef REG_EIP
176 /* for glibc 2.1 */
177 #define REG_EIP EIP
178 #define REG_ERR ERR
179 #define REG_TRAPNO TRAPNO
180 #endif
181 pc = EIP_sig(uc);
182 trapno = TRAP_sig(uc);
183 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
184 trapno == 0xe ?
185 (ERROR_sig(uc) >> 1) & 1 : 0,
186 &MASK_sig(uc));
187 }
188
189 #elif defined(__x86_64__)
190
191 #ifdef __NetBSD__
192 #define PC_sig(context) _UC_MACHINE_PC(context)
193 #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
194 #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
195 #define MASK_sig(context) ((context)->uc_sigmask)
196 #elif defined(__OpenBSD__)
197 #define PC_sig(context) ((context)->sc_rip)
198 #define TRAP_sig(context) ((context)->sc_trapno)
199 #define ERROR_sig(context) ((context)->sc_err)
200 #define MASK_sig(context) ((context)->sc_mask)
201 #elif defined(__FreeBSD__) || defined(__DragonFly__)
202 #include <ucontext.h>
203
204 #define PC_sig(context) (*((unsigned long *)&(context)->uc_mcontext.mc_rip))
205 #define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
206 #define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
207 #define MASK_sig(context) ((context)->uc_sigmask)
208 #else
209 #define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP])
210 #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
211 #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
212 #define MASK_sig(context) ((context)->uc_sigmask)
213 #endif
214
215 int cpu_signal_handler(int host_signum, void *pinfo,
216 void *puc)
217 {
218 siginfo_t *info = pinfo;
219 unsigned long pc;
220 #if defined(__NetBSD__) || defined(__FreeBSD__) || defined(__DragonFly__)
221 ucontext_t *uc = puc;
222 #elif defined(__OpenBSD__)
223 struct sigcontext *uc = puc;
224 #else
225 struct ucontext *uc = puc;
226 #endif
227
228 pc = PC_sig(uc);
229 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
230 TRAP_sig(uc) == 0xe ?
231 (ERROR_sig(uc) >> 1) & 1 : 0,
232 &MASK_sig(uc));
233 }
234
235 #elif defined(_ARCH_PPC)
236
237 /***********************************************************************
238 * signal context platform-specific definitions
239 * From Wine
240 */
241 #ifdef linux
242 /* All Registers access - only for local access */
243 #define REG_sig(reg_name, context) \
244 ((context)->uc_mcontext.regs->reg_name)
245 /* Gpr Registers access */
246 #define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
247 /* Program counter */
248 #define IAR_sig(context) REG_sig(nip, context)
249 /* Machine State Register (Supervisor) */
250 #define MSR_sig(context) REG_sig(msr, context)
251 /* Count register */
252 #define CTR_sig(context) REG_sig(ctr, context)
253 /* User's integer exception register */
254 #define XER_sig(context) REG_sig(xer, context)
255 /* Link register */
256 #define LR_sig(context) REG_sig(link, context)
257 /* Condition register */
258 #define CR_sig(context) REG_sig(ccr, context)
259
260 /* Float Registers access */
261 #define FLOAT_sig(reg_num, context) \
262 (((double *)((char *)((context)->uc_mcontext.regs + 48 * 4)))[reg_num])
263 #define FPSCR_sig(context) \
264 (*(int *)((char *)((context)->uc_mcontext.regs + (48 + 32 * 2) * 4)))
265 /* Exception Registers access */
266 #define DAR_sig(context) REG_sig(dar, context)
267 #define DSISR_sig(context) REG_sig(dsisr, context)
268 #define TRAP_sig(context) REG_sig(trap, context)
269 #endif /* linux */
270
271 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
272 #include <ucontext.h>
273 #define IAR_sig(context) ((context)->uc_mcontext.mc_srr0)
274 #define MSR_sig(context) ((context)->uc_mcontext.mc_srr1)
275 #define CTR_sig(context) ((context)->uc_mcontext.mc_ctr)
276 #define XER_sig(context) ((context)->uc_mcontext.mc_xer)
277 #define LR_sig(context) ((context)->uc_mcontext.mc_lr)
278 #define CR_sig(context) ((context)->uc_mcontext.mc_cr)
279 /* Exception Registers access */
280 #define DAR_sig(context) ((context)->uc_mcontext.mc_dar)
281 #define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr)
282 #define TRAP_sig(context) ((context)->uc_mcontext.mc_exc)
283 #endif /* __FreeBSD__|| __FreeBSD_kernel__ */
284
285 int cpu_signal_handler(int host_signum, void *pinfo,
286 void *puc)
287 {
288 siginfo_t *info = pinfo;
289 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
290 ucontext_t *uc = puc;
291 #else
292 struct ucontext *uc = puc;
293 #endif
294 unsigned long pc;
295 int is_write;
296
297 pc = IAR_sig(uc);
298 is_write = 0;
299 #if 0
300 /* ppc 4xx case */
301 if (DSISR_sig(uc) & 0x00800000) {
302 is_write = 1;
303 }
304 #else
305 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000)) {
306 is_write = 1;
307 }
308 #endif
309 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
310 is_write, &uc->uc_sigmask);
311 }
312
313 #elif defined(__alpha__)
314
315 int cpu_signal_handler(int host_signum, void *pinfo,
316 void *puc)
317 {
318 siginfo_t *info = pinfo;
319 struct ucontext *uc = puc;
320 uint32_t *pc = uc->uc_mcontext.sc_pc;
321 uint32_t insn = *pc;
322 int is_write = 0;
323
324 /* XXX: need kernel patch to get write flag faster */
325 switch (insn >> 26) {
326 case 0x0d: /* stw */
327 case 0x0e: /* stb */
328 case 0x0f: /* stq_u */
329 case 0x24: /* stf */
330 case 0x25: /* stg */
331 case 0x26: /* sts */
332 case 0x27: /* stt */
333 case 0x2c: /* stl */
334 case 0x2d: /* stq */
335 case 0x2e: /* stl_c */
336 case 0x2f: /* stq_c */
337 is_write = 1;
338 }
339
340 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
341 is_write, &uc->uc_sigmask);
342 }
343 #elif defined(__sparc__)
344
345 int cpu_signal_handler(int host_signum, void *pinfo,
346 void *puc)
347 {
348 siginfo_t *info = pinfo;
349 int is_write;
350 uint32_t insn;
351 #if !defined(__arch64__) || defined(CONFIG_SOLARIS)
352 uint32_t *regs = (uint32_t *)(info + 1);
353 void *sigmask = (regs + 20);
354 /* XXX: is there a standard glibc define ? */
355 unsigned long pc = regs[1];
356 #else
357 #ifdef __linux__
358 struct sigcontext *sc = puc;
359 unsigned long pc = sc->sigc_regs.tpc;
360 void *sigmask = (void *)sc->sigc_mask;
361 #elif defined(__OpenBSD__)
362 struct sigcontext *uc = puc;
363 unsigned long pc = uc->sc_pc;
364 void *sigmask = (void *)(long)uc->sc_mask;
365 #elif defined(__NetBSD__)
366 ucontext_t *uc = puc;
367 unsigned long pc = _UC_MACHINE_PC(uc);
368 void *sigmask = (void *)&uc->uc_sigmask;
369 #endif
370 #endif
371
372 /* XXX: need kernel patch to get write flag faster */
373 is_write = 0;
374 insn = *(uint32_t *)pc;
375 if ((insn >> 30) == 3) {
376 switch ((insn >> 19) & 0x3f) {
377 case 0x05: /* stb */
378 case 0x15: /* stba */
379 case 0x06: /* sth */
380 case 0x16: /* stha */
381 case 0x04: /* st */
382 case 0x14: /* sta */
383 case 0x07: /* std */
384 case 0x17: /* stda */
385 case 0x0e: /* stx */
386 case 0x1e: /* stxa */
387 case 0x24: /* stf */
388 case 0x34: /* stfa */
389 case 0x27: /* stdf */
390 case 0x37: /* stdfa */
391 case 0x26: /* stqf */
392 case 0x36: /* stqfa */
393 case 0x25: /* stfsr */
394 case 0x3c: /* casa */
395 case 0x3e: /* casxa */
396 is_write = 1;
397 break;
398 }
399 }
400 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
401 is_write, sigmask);
402 }
403
404 #elif defined(__arm__)
405
406 #if defined(__NetBSD__)
407 #include <ucontext.h>
408 #endif
409
410 int cpu_signal_handler(int host_signum, void *pinfo,
411 void *puc)
412 {
413 siginfo_t *info = pinfo;
414 #if defined(__NetBSD__)
415 ucontext_t *uc = puc;
416 #else
417 struct ucontext *uc = puc;
418 #endif
419 unsigned long pc;
420 int is_write;
421
422 #if defined(__NetBSD__)
423 pc = uc->uc_mcontext.__gregs[_REG_R15];
424 #elif defined(__GLIBC__) && (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
425 pc = uc->uc_mcontext.gregs[R15];
426 #else
427 pc = uc->uc_mcontext.arm_pc;
428 #endif
429
430 /* error_code is the FSR value, in which bit 11 is WnR (assuming a v6 or
431 * later processor; on v5 we will always report this as a read).
432 */
433 is_write = extract32(uc->uc_mcontext.error_code, 11, 1);
434 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
435 is_write,
436 &uc->uc_sigmask);
437 }
438
439 #elif defined(__aarch64__)
440
441 int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
442 {
443 siginfo_t *info = pinfo;
444 struct ucontext *uc = puc;
445 uintptr_t pc = uc->uc_mcontext.pc;
446 uint32_t insn = *(uint32_t *)pc;
447 bool is_write;
448
449 /* XXX: need kernel patch to get write flag faster. */
450 is_write = ( (insn & 0xbfff0000) == 0x0c000000 /* C3.3.1 */
451 || (insn & 0xbfe00000) == 0x0c800000 /* C3.3.2 */
452 || (insn & 0xbfdf0000) == 0x0d000000 /* C3.3.3 */
453 || (insn & 0xbfc00000) == 0x0d800000 /* C3.3.4 */
454 || (insn & 0x3f400000) == 0x08000000 /* C3.3.6 */
455 || (insn & 0x3bc00000) == 0x39000000 /* C3.3.13 */
456 || (insn & 0x3fc00000) == 0x3d800000 /* ... 128bit */
457 /* Ingore bits 10, 11 & 21, controlling indexing. */
458 || (insn & 0x3bc00000) == 0x38000000 /* C3.3.8-12 */
459 || (insn & 0x3fe00000) == 0x3c800000 /* ... 128bit */
460 /* Ignore bits 23 & 24, controlling indexing. */
461 || (insn & 0x3a400000) == 0x28000000); /* C3.3.7,14-16 */
462
463 return handle_cpu_signal(pc, (uintptr_t)info->si_addr,
464 is_write, &uc->uc_sigmask);
465 }
466
467 #elif defined(__ia64)
468
469 #ifndef __ISR_VALID
470 /* This ought to be in <bits/siginfo.h>... */
471 # define __ISR_VALID 1
472 #endif
473
474 int cpu_signal_handler(int host_signum, void *pinfo, void *puc)
475 {
476 siginfo_t *info = pinfo;
477 struct ucontext *uc = puc;
478 unsigned long ip;
479 int is_write = 0;
480
481 ip = uc->uc_mcontext.sc_ip;
482 switch (host_signum) {
483 case SIGILL:
484 case SIGFPE:
485 case SIGSEGV:
486 case SIGBUS:
487 case SIGTRAP:
488 if (info->si_code && (info->si_segvflags & __ISR_VALID)) {
489 /* ISR.W (write-access) is bit 33: */
490 is_write = (info->si_isr >> 33) & 1;
491 }
492 break;
493
494 default:
495 break;
496 }
497 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
498 is_write,
499 (sigset_t *)&uc->uc_sigmask);
500 }
501
502 #elif defined(__s390__)
503
504 int cpu_signal_handler(int host_signum, void *pinfo,
505 void *puc)
506 {
507 siginfo_t *info = pinfo;
508 struct ucontext *uc = puc;
509 unsigned long pc;
510 uint16_t *pinsn;
511 int is_write = 0;
512
513 pc = uc->uc_mcontext.psw.addr;
514
515 /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead
516 of the normal 2 arguments. The 3rd argument contains the "int_code"
517 from the hardware which does in fact contain the is_write value.
518 The rt signal handler, as far as I can tell, does not give this value
519 at all. Not that we could get to it from here even if it were. */
520 /* ??? This is not even close to complete, since it ignores all
521 of the read-modify-write instructions. */
522 pinsn = (uint16_t *)pc;
523 switch (pinsn[0] >> 8) {
524 case 0x50: /* ST */
525 case 0x42: /* STC */
526 case 0x40: /* STH */
527 is_write = 1;
528 break;
529 case 0xc4: /* RIL format insns */
530 switch (pinsn[0] & 0xf) {
531 case 0xf: /* STRL */
532 case 0xb: /* STGRL */
533 case 0x7: /* STHRL */
534 is_write = 1;
535 }
536 break;
537 case 0xe3: /* RXY format insns */
538 switch (pinsn[2] & 0xff) {
539 case 0x50: /* STY */
540 case 0x24: /* STG */
541 case 0x72: /* STCY */
542 case 0x70: /* STHY */
543 case 0x8e: /* STPQ */
544 case 0x3f: /* STRVH */
545 case 0x3e: /* STRV */
546 case 0x2f: /* STRVG */
547 is_write = 1;
548 }
549 break;
550 }
551 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
552 is_write, &uc->uc_sigmask);
553 }
554
555 #elif defined(__mips__)
556
557 int cpu_signal_handler(int host_signum, void *pinfo,
558 void *puc)
559 {
560 siginfo_t *info = pinfo;
561 struct ucontext *uc = puc;
562 greg_t pc = uc->uc_mcontext.pc;
563 int is_write;
564
565 /* XXX: compute is_write */
566 is_write = 0;
567 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
568 is_write, &uc->uc_sigmask);
569 }
570
571 #else
572
573 #error host CPU specific signal handler needed
574
575 #endif