hw/timer/imx_epit: Avoid assertion when CR.SWR is written
authorPeter Maydell <peter.maydell@linaro.org>
Mon, 27 Jul 2020 15:45:50 +0000 (16:45 +0100)
committerPeter Maydell <peter.maydell@linaro.org>
Mon, 3 Aug 2020 16:56:11 +0000 (17:56 +0100)
commit13557fd392890cbd985bceba7f717e01efd674b8
treec4d5d792312b99073390774f2a4dd7e6def1e1f7
parentce4f70e81ed23c93ff39234672aff33114532640
hw/timer/imx_epit: Avoid assertion when CR.SWR is written

The imx_epit device has a software-controllable reset triggered by
setting the SWR bit in the CR register. An error in commit cc2722ec83ad9
means that we will end up assert()ing if the guest does this, because
the code in imx_epit_write() starts ptimer transactions, and then
imx_epit_reset() also starts ptimer transactions, triggering
"ptimer_transaction_begin: Assertion `!s->in_transaction' failed".

The cleanest way to avoid this double-transaction is to move the
start-transaction for the CR write handling down below the check of
the SWR bit.

Fixes: https://bugs.launchpad.net/qemu/+bug/1880424
Fixes: cc2722ec83ad944505fe
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200727154550.3409-1-peter.maydell@linaro.org
hw/timer/imx_epit.c