hw/riscv: Move sifive_plic model to hw/intc
authorBin Meng <bin.meng@windriver.com>
Thu, 3 Sep 2020 10:40:17 +0000 (18:40 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Wed, 9 Sep 2020 22:54:19 +0000 (15:54 -0700)
commit84fcf3c15111de9f0c72efbb6bc0def264555c46
tree57567c453d5ea85f06f0c753aefa4fa0d9709eae
parent406fafd5d0f9a1c6a365ff1733c26a043b1c4877
hw/riscv: Move sifive_plic model to hw/intc

This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_plic model to hw/intc directory.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-7-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
hw/intc/Kconfig
hw/intc/meson.build
hw/intc/sifive_plic.c [moved from hw/riscv/sifive_plic.c with 99% similarity]
hw/intc/sifive_plic.h [moved from include/hw/riscv/sifive_plic.h with 100% similarity]
hw/riscv/Kconfig
hw/riscv/meson.build
hw/riscv/microchip_pfsoc.c
hw/riscv/sifive_e.c
hw/riscv/sifive_u.c
hw/riscv/virt.c