qemu.git
8 years agoqdev: add "hotpluggable" property to Device
Igor Mammedov [Wed, 5 Feb 2014 15:36:46 +0000 (16:36 +0100)] 
qdev: add "hotpluggable" property to Device

Currently it's possible to make PCIDevice not hotpluggable
by using no_hotplug field of PCIDeviceClass. However it
limits this only to PCI devices and prevents from
generalizing hotplug code.

So add similar field to DeviceClass so it could be reused
with other Devices and would allow to replace PCI specific
hotplug callbacks with generic implementation. Following
patches will replace PCIDeviceClass.no_hotplug with this
new property.

In addition expose field as "hotpluggable" readonly property,
to make it possible to read its value via QOM interface.

Make DeviceClass hotpluggable by default as it was assumed
before.

Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
8 years agoqdev: add to BusState "hotplug-handler" link
Igor Mammedov [Wed, 5 Feb 2014 15:36:45 +0000 (16:36 +0100)] 
qdev: add to BusState "hotplug-handler" link

It will allow to reuse field with different BUSes,
reducing code duplication. Field is intended for
replacing 'hotplug_qdev' field in PCIBus and also
will allow to avoid adding equivalent field to
DimmBus with possiblitity to refactor other BUSes
to use it instead of custom field.
In addition once all users of allow_hotplug field
are converted to new API, link could replace
allow_hotplug field in qdev hotplug code.

Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
8 years agodefine hotplug interface
Igor Mammedov [Wed, 5 Feb 2014 15:36:44 +0000 (16:36 +0100)] 
define hotplug interface

Provide a generic hotplug interface for hotplug handlers.
Intended for replacing hotplug mechanism used by
PCI/PCIE/SHPC code and will be used for memory hotplug.

Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
8 years agoloader: document that errno is set
Michael S. Tsirkin [Wed, 5 Feb 2014 19:57:55 +0000 (21:57 +0200)] 
loader: document that errno is set

Document that get_image_size sets errno
on failure.

Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
8 years agopc.c: better error message on initrd sizing failure
Michael S. Tsirkin [Sun, 2 Feb 2014 20:45:28 +0000 (22:45 +0200)] 
pc.c: better error message on initrd sizing failure

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
8 years agopc_piix: enable legacy hotplug for Xen
Michael S. Tsirkin [Tue, 4 Feb 2014 21:29:30 +0000 (23:29 +0200)] 
pc_piix: enable legacy hotplug for Xen

xenfv has no fwcfg and so does not load acpi from QEMU.
as such new acpi features don't work.

Reported-by: Sander Eikelenboom <linux@eikelenboom.it>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
8 years agoqtest: don't report signals if qtest driver enabled
Michael S. Tsirkin [Tue, 4 Feb 2014 18:04:21 +0000 (20:04 +0200)] 
qtest: don't report signals if qtest driver enabled

qtest driver always uses signals to kill qemu
no need to report it, whatever the accelerator state.

Add API to detect qtest driver, and suppress reporting
signals in this case.

Reported-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
8 years agohw:piix4:acpi: reuse pcihp code for legacy PCI hotplug
Igor Mammedov [Mon, 3 Feb 2014 10:45:01 +0000 (11:45 +0100)] 
hw:piix4:acpi: reuse pcihp code for legacy PCI hotplug

reduces acpi PCI hotplug code duplication by ~200LOC

Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
8 years agopcihp: remove unused AcpiPciHpPciStatus.device_present field
Igor Mammedov [Mon, 3 Feb 2014 10:45:00 +0000 (11:45 +0100)] 
pcihp: remove unused AcpiPciHpPciStatus.device_present field

Remove now unused 'device_present' field wich was obsoleted by
patch "pcihp: reduce number of device check events"

Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
8 years agopcihp: make pci_read() mmio calback compatible with legacy ACPI hotplug
Igor Mammedov [Mon, 3 Feb 2014 10:44:59 +0000 (11:44 +0100)] 
pcihp: make pci_read() mmio calback compatible with legacy ACPI hotplug

due to recent change introduced by:
"pcihp: reduce number of device check events"

'up' field is cleared right after it's read.
This is incompatible with legacy BIOS ACPI code
where PCNF ACPI method reads this field 32 times.

To make pci_read mmio callback compatible with legacy
'up' behavior, pcihp code will need to know in which
mode it runs add 'legacy_piix' field to AcpiPciHpState
structure and alter register behavior accordingly.

Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
8 years agopcihp: make PCI hotplug mmio handlers indifferent to PCI_HOTPLUG_ADDR
Igor Mammedov [Mon, 3 Feb 2014 10:44:58 +0000 (11:44 +0100)] 
pcihp: make PCI hotplug mmio handlers indifferent to PCI_HOTPLUG_ADDR

... removes dependency of mmio handler on PCI_HOTPLUG_ADDR.
It will be needed in case of Q35 where base could be different.

Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
8 years agopcihp: replace enable|disable_device() with oneliners
Igor Mammedov [Mon, 3 Feb 2014 10:44:57 +0000 (11:44 +0100)] 
pcihp: replace enable|disable_device() with oneliners

enable_device() and disable_device() functions aren't reused anywere,
so replace them with respective oneliners at call sites.

Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
8 years agopcihp: reduce number of device check events
Michael S. Tsirkin [Sun, 26 Jan 2014 10:31:27 +0000 (12:31 +0200)] 
pcihp: reduce number of device check events

PIIX created a made-up value for the UP register since it was read by
guest 32 times for each interrupt.
There's no reason to do this for the new PCIHP: register is only read
once for each interrupt, so clean up code by making read act as an
interrupt acknowledgement: the new UP register clear on read.

In this way we cut down the number of bus rescans
by a factor of 32, and drop a bunch of code that's
now unused.

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
8 years agoMerge remote-tracking branch 'remotes/borntraeger/tags/kvm-s390-20140131' into staging
Peter Maydell [Tue, 4 Feb 2014 18:46:33 +0000 (18:46 +0000)] 
Merge remote-tracking branch 'remotes/borntraeger/tags/kvm-s390-20140131' into staging

This patch set contains the sclp defines and events for cpu hotplug,
the initial sclp defines (without code yet) for standby memory (some
sort of memory hotplug) as well as a cleanup of the kvm register
synchronization.

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* remotes/borntraeger/tags/kvm-s390-20140131:
  s390x/kvm: cleanup partial register handling
  sclp-s390: Define new SCLP codes and structures
  s390-sclp: SCLP Event integration
  s390-sclp: SCLP CPU Info
  s390-sclp: Define New SCLP Codes

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agoMerge remote-tracking branch 'remotes/mcayland/qemu-openbios' into staging
Peter Maydell [Tue, 4 Feb 2014 16:16:37 +0000 (16:16 +0000)] 
Merge remote-tracking branch 'remotes/mcayland/qemu-openbios' into staging

* remotes/mcayland/qemu-openbios:
  Update OpenBIOS images

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agolinux-user: Fix trampoline code for CRIS
Stefan Weil [Sat, 1 Feb 2014 08:41:09 +0000 (09:41 +0100)] 
linux-user: Fix trampoline code for CRIS

__put_user can write bytes, words (2 bytes) or longwords (4 bytes).
Here obviously words should have been written, but bytes were written,
so values like 0x9c5f were truncated to 0x5f.

Fix this by changing retcode from uint8_t to to uint16_t in
target_signal_frame and also in the unused rt_signal_frame.

This problem was reported by static code analysis (smatch).

Cc: qemu-stable@nongnu.org
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Acked-by: Riku Voipio <riku.voipio@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
8 years agocris: Remove the CRIS PIC glue
Edgar E. Iglesias [Tue, 21 Jan 2014 13:49:44 +0000 (23:49 +1000)] 
cris: Remove the CRIS PIC glue

Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
8 years agoaxis-dev88: Connect the PIC upstream IRQs directly to the CPU
Edgar E. Iglesias [Tue, 21 Jan 2014 12:45:54 +0000 (22:45 +1000)] 
axis-dev88: Connect the PIC upstream IRQs directly to the CPU

Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
8 years agocris: Add interrupt signals to the CPU device
Edgar E. Iglesias [Tue, 21 Jan 2014 12:44:23 +0000 (22:44 +1000)] 
cris: Add interrupt signals to the CPU device

Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
8 years agocris: Abort when a v10 takes interrupts while in a delayslot
Edgar E. Iglesias [Sat, 18 Jan 2014 04:07:48 +0000 (04:07 +0000)] 
cris: Abort when a v10 takes interrupts while in a delayslot

This is an internal error as the CRISv10 should mask interrupts
while executing delay slots. Bail out sooner rather than later.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
8 years agocris: Add "any" as alias for "crisv32" in user emulation
Edgar E. Iglesias [Sat, 18 Jan 2014 03:42:23 +0000 (03:42 +0000)] 
cris: Add "any" as alias for "crisv32" in user emulation

Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
8 years agoMerge remote-tracking branch 'qmp-unstable/queue/qmp' into staging
Peter Maydell [Sat, 1 Feb 2014 23:32:23 +0000 (23:32 +0000)] 
Merge remote-tracking branch 'qmp-unstable/queue/qmp' into staging

* qmp-unstable/queue/qmp:
  monitor: Cleanup mon->outbuf on write error
  virtio_rng: replace custom backend API with UserCreatable.complete() callback
  add optional 2nd stage initialization to -object/object-add commands
  vl.c: -object: don't ignore duplicate 'id'
  object_add: consolidate error handling

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agoMerge remote-tracking branch 'pmaydell/tags/pull-target-arm-20140131' into staging
Peter Maydell [Sat, 1 Feb 2014 23:06:11 +0000 (23:06 +0000)] 
Merge remote-tracking branch 'pmaydell/tags/pull-target-arm-20140131' into staging

target-arm queue:
 * implementation of first part of the A64 Neon instruction set
 * v8 AArch32 rounding and 16<->64 fp conversion instructions
 * fix MIDR value on Zynq boards
 * some minor bugfixes/code cleanups

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* pmaydell/tags/pull-target-arm-20140131: (34 commits)
  arm_gic: Fix GICD_ICPENDR and GICD_ISPENDR writes
  arm_gic: Introduce define for GIC_NR_SGIS
  target-arm: A64: Add SIMD shift by immediate
  target-arm: A64: Add simple SIMD 3-same floating point ops
  target-arm: A64: Add integer ops from SIMD 3-same group
  target-arm: A64: Add logic ops from SIMD 3 same group
  target-arm: A64: Add top level decode for SIMD 3-same group
  target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops
  target-arm: A64: Add SIMD three-different ABDL instructions
  target-arm: A64: Add SIMD three-different multiply accumulate insns
  target-arm: Add AArch32 SIMD VCVTA, VCVTN, VCVTP and VCVTM
  target-arm: Add AArch32 FP VCVTA, VCVTN, VCVTP and VCVTM
  target-arm: Add AArch32 SIMD VRINTA, VRINTN, VRINTP, VRINTM, VRINTZ
  target-arm: Add set_neon_rmode helper
  target-arm: Add support for AArch32 SIMD VRINTX
  target-arm: Add support for AArch32 FP VRINTX
  target-arm: Add support for AArch32 FP VRINTZ
  target-arm: Add support for AArch32 FP VRINTR
  target-arm: Add AArch32 FP VRINTA, VRINTN, VRINTP and VRINTM
  target-arm: Move arm_rmode_to_sf to a shared location.
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agoMerge remote-tracking branch 'remotes/awilliam/tags/vfio-pci-for-qemu-20140128.0...
Peter Maydell [Sat, 1 Feb 2014 21:07:59 +0000 (21:07 +0000)] 
Merge remote-tracking branch 'remotes/awilliam/tags/vfio-pci-for-qemu-20140128.0' into staging

vfio-pci updates include:
 - Destroy MemoryRegions on device teardown
 - Print warnings around PCI option ROM failures
 - Skip bogus mappings from 64bit BAR sizing
 - Act on DMA mapping failures
 - Fix alignment to avoid MSI-X table mapping
 - Fix debug macro typo

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* remotes/awilliam/tags/vfio-pci-for-qemu-20140128.0:
  vfio: correct debug macro typo
  vfio: fix mapping of MSIX bar
  kvm: initialize qemu_host_page_size
  vfio-pci: Fail initfn on DMA mapping errors
  vfio: Filter out bogus mappings
  vfio: Do not reattempt a failed rom read
  vfio: warn if host device rom can't be read
  vfio: Destroy memory regions

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agoMerge remote-tracking branch 'remotes/sstabellini/xen-140130' into staging
Peter Maydell [Sat, 1 Feb 2014 20:43:07 +0000 (20:43 +0000)] 
Merge remote-tracking branch 'remotes/sstabellini/xen-140130' into staging

* remotes/sstabellini/xen-140130:
  address_space_translate: do not cross page boundaries

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agoarm_gic: Fix GICD_ICPENDR and GICD_ISPENDR writes
Christoffer Dall [Fri, 31 Jan 2014 14:47:38 +0000 (14:47 +0000)] 
arm_gic: Fix GICD_ICPENDR and GICD_ISPENDR writes

Fix two bugs that would allow changing the state of SGIs through the
ICPENDR and ISPENDRs.

Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agoarm_gic: Introduce define for GIC_NR_SGIS
Christoffer Dall [Fri, 31 Jan 2014 14:47:38 +0000 (14:47 +0000)] 
arm_gic: Introduce define for GIC_NR_SGIS

Instead of hardcoding 16 various places in the code, use a define to
make it more clear what is going on.

Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agotarget-arm: A64: Add SIMD shift by immediate
Alex Bennée [Fri, 31 Jan 2014 14:47:37 +0000 (14:47 +0000)] 
target-arm: A64: Add SIMD shift by immediate

This implements a subset of the AdvSIMD shift operations (namely all the
none saturating or narrowing ones). The actual shift generation code
itself is common for both the scalar and vector cases but wrapped with
either vector element iteration or the fp reg access.

The rounding operations need to take special care to correctly reflect
the result of adding rounding bits on high bits as the intermediates do
not truncate.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agotarget-arm: A64: Add simple SIMD 3-same floating point ops
Peter Maydell [Fri, 31 Jan 2014 14:47:37 +0000 (14:47 +0000)] 
target-arm: A64: Add simple SIMD 3-same floating point ops

Implement a simple subset of the SIMD 3-same floating point
operations. This includes a common helper function used for both
scalar and vector ops; FABD is the only currently implemented
shared op.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
8 years agotarget-arm: A64: Add integer ops from SIMD 3-same group
Peter Maydell [Fri, 31 Jan 2014 14:47:37 +0000 (14:47 +0000)] 
target-arm: A64: Add integer ops from SIMD 3-same group

Add some of the integer operations in the SIMD 3-same group:
specifically, the comparisons, addition and subtraction.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
8 years agotarget-arm: A64: Add logic ops from SIMD 3 same group
Peter Maydell [Fri, 31 Jan 2014 14:47:37 +0000 (14:47 +0000)] 
target-arm: A64: Add logic ops from SIMD 3 same group

Add support for the logical operations (ORR, AND, BIC, ORN, EOR, BSL,
BIT and BIF) from the SIMD 3 register same group (C3.6.16).

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
8 years agotarget-arm: A64: Add top level decode for SIMD 3-same group
Peter Maydell [Fri, 31 Jan 2014 14:47:37 +0000 (14:47 +0000)] 
target-arm: A64: Add top level decode for SIMD 3-same group

Add top level decode for the A64 SIMD three regs same group
(C3.6.16), splitting it into the pairwise, logical, float and
integer subgroups.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
8 years agotarget-arm: A64: Add SIMD scalar 3 same add, sub and compare ops
Peter Maydell [Fri, 31 Jan 2014 14:47:36 +0000 (14:47 +0000)] 
target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops

Implement the add, sub and compare ops from the SIMD "scalar three same"
group.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
8 years agotarget-arm: A64: Add SIMD three-different ABDL instructions
Peter Maydell [Fri, 31 Jan 2014 14:47:36 +0000 (14:47 +0000)] 
target-arm: A64: Add SIMD three-different ABDL instructions

Implement the absolute-difference instructions in the SIMD
three-different group: SABAL, SABAL2, UABAL, UABAL2, SABDL,
SABDL2, UABDL, UABDL2.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
8 years agotarget-arm: A64: Add SIMD three-different multiply accumulate insns
Peter Maydell [Fri, 31 Jan 2014 14:47:36 +0000 (14:47 +0000)] 
target-arm: A64: Add SIMD three-different multiply accumulate insns

Add support for the multiply-accumulate instructions from the
SIMD three-different instructions group (C3.6.15):
 * skeleton decode of unallocated encodings and split of
   the group into its three sub-parts
 * framework for handling the 64x64->128 widening subpart
 * implementation of the multiply-accumulate instructions
   SMLAL, SMLAL2, UMLAL, UMLAL2, SMLSL, SMLSL2, UMLSL, UMLSL2,
   UMULL, UMULL2, SMULL, SMULL2

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
8 years agotarget-arm: Add AArch32 SIMD VCVTA, VCVTN, VCVTP and VCVTM
Will Newton [Fri, 31 Jan 2014 14:47:35 +0000 (14:47 +0000)] 
target-arm: Add AArch32 SIMD VCVTA, VCVTN, VCVTP and VCVTM

Add support for the AArch32 Advanced SIMD VCVTA, VCVTN, VCVTP
and VCVTM instructions.

Signed-off-by: Will Newton <will.newton@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agotarget-arm: Add AArch32 FP VCVTA, VCVTN, VCVTP and VCVTM
Will Newton [Fri, 31 Jan 2014 14:47:35 +0000 (14:47 +0000)] 
target-arm: Add AArch32 FP VCVTA, VCVTN, VCVTP and VCVTM

Add support for the AArch32 floating-point VCVTA, VCVTN, VCVTP
and VCVTM instructions.

Signed-off-by: Will Newton <will.newton@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agotarget-arm: Add AArch32 SIMD VRINTA, VRINTN, VRINTP, VRINTM, VRINTZ
Will Newton [Fri, 31 Jan 2014 14:47:35 +0000 (14:47 +0000)] 
target-arm: Add AArch32 SIMD VRINTA, VRINTN, VRINTP, VRINTM, VRINTZ

Add support for the AArch32 Advanced SIMD VRINTA, VRINTN, VRINTP
VRINTM and VRINTZ instructions.

Signed-off-by: Will Newton <will.newton@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agotarget-arm: Add set_neon_rmode helper
Will Newton [Fri, 31 Jan 2014 14:47:35 +0000 (14:47 +0000)] 
target-arm: Add set_neon_rmode helper

This helper sets the rounding mode in the standard_fp_status word to
allow NEON instructions to modify the rounding mode whilst using the
standard FPSCR values for everything else.

Signed-off-by: Will Newton <will.newton@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agotarget-arm: Add support for AArch32 SIMD VRINTX
Will Newton [Fri, 31 Jan 2014 14:47:34 +0000 (14:47 +0000)] 
target-arm: Add support for AArch32 SIMD VRINTX

Add support for the AArch32 Advanced SIMD VRINTX instruction.

Signed-off-by: Will Newton <will.newton@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agotarget-arm: Add support for AArch32 FP VRINTX
Will Newton [Fri, 31 Jan 2014 14:47:34 +0000 (14:47 +0000)] 
target-arm: Add support for AArch32 FP VRINTX

Add support for the AArch32 floating-point VRINTX instruction.

Signed-off-by: Will Newton <will.newton@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agotarget-arm: Add support for AArch32 FP VRINTZ
Will Newton [Fri, 31 Jan 2014 14:47:34 +0000 (14:47 +0000)] 
target-arm: Add support for AArch32 FP VRINTZ

Add support for the AArch32 floating-point VRINTZ instruction.

Signed-off-by: Will Newton <will.newton@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agotarget-arm: Add support for AArch32 FP VRINTR
Will Newton [Fri, 31 Jan 2014 14:47:34 +0000 (14:47 +0000)] 
target-arm: Add support for AArch32 FP VRINTR

Add support for the AArch32 floating-point VRINTR instruction.

Signed-off-by: Will Newton <will.newton@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agotarget-arm: Add AArch32 FP VRINTA, VRINTN, VRINTP and VRINTM
Will Newton [Fri, 31 Jan 2014 14:47:33 +0000 (14:47 +0000)] 
target-arm: Add AArch32 FP VRINTA, VRINTN, VRINTP and VRINTM

Add support for AArch32 ARMv8 FP VRINTA, VRINTN, VRINTP and VRINTM
instructions.

Signed-off-by: Will Newton <will.newton@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agotarget-arm: Move arm_rmode_to_sf to a shared location.
Will Newton [Fri, 31 Jan 2014 14:47:33 +0000 (14:47 +0000)] 
target-arm: Move arm_rmode_to_sf to a shared location.

This function will be needed for AArch32 ARMv8 support, so move it to
helper.c where it can be used by both targets. Also moves the code out
of line, but as it is quite a large function I don't believe this
should be a significant performance impact.

Signed-off-by: Will Newton <will.newton@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agodisplay: avoid multi-statement macro
Paolo Bonzini [Fri, 31 Jan 2014 14:47:33 +0000 (14:47 +0000)] 
display: avoid multi-statement macro

For blizzard, pl110 and tc6393xb this is harmless, but for pxa2xx
Coverity noticed that it is used inside an "if" statement.
Fix it because it's the file with the highest number of defects
in the whole QEMU tree!  Use "do...while (0)", or just remove the
semicolon if there's a single statement in the macro.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agoZYNQ: Implement board MIDR control for Zynq
Alistair Francis [Fri, 31 Jan 2014 14:47:33 +0000 (14:47 +0000)] 
ZYNQ: Implement board MIDR control for Zynq

This patch uses the fact that the midr variable is now a property
This patch sets the midr variable to the boards custom midr

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Message-id: a3754b10d150af72e4688a993e484fa2b9b8fa21.1390176489.git.alistair.francis@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agoARM: Convert MIDR to a property
Alistair Francis [Fri, 31 Jan 2014 14:47:32 +0000 (14:47 +0000)] 
ARM: Convert MIDR to a property

Convert the MIDR register to a property. This allows boards to later set
a custom MIDR value. This has been done in such a way to maintain
compatibility with all existing CPUs and boards

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 878613f2f12d4162f12629522fd99de8df904856.1390176489.git.alistair.francis@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agohw/arm/boot: Don't set up ATAGS for autogenerated dtb booting
Peter Maydell [Fri, 31 Jan 2014 14:47:32 +0000 (14:47 +0000)] 
hw/arm/boot: Don't set up ATAGS for autogenerated dtb booting

The code which decides whether to set up the ATAGS data structure on
reset was using the wrong conditional, which meant we were creating
an ATAGS structure when doing a device-tree boot if the dtb was
autogenerated by the board. This is harmless, but unnecessary, so
bring it in to line with user-provided-dtb boots.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 1388326833-656-1-git-send-email-peter.maydell@linaro.org

8 years agotarget-arm: A64: Add SIMD scalar copy instructions
Peter Maydell [Fri, 31 Jan 2014 14:47:32 +0000 (14:47 +0000)] 
target-arm: A64: Add SIMD scalar copy instructions

Add support for the SIMD scalar copy instruction group (C3.6.7),
which consists of the single instruction DUP (element, scalar).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
8 years agotarget-arm: A64: Add SIMD modified immediate group
Alex Bennée [Fri, 31 Jan 2014 14:47:32 +0000 (14:47 +0000)] 
target-arm: A64: Add SIMD modified immediate group

This patch adds support for the AdvSIMD modified immediate group
(C3.6.6) with all its suboperations (movi, orr, fmov, mvni, bic).

Signed-off-by: Alexander Graf <agraf@suse.de>
[AJB: new decode struct, minor bug fixes, optimisation]
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
8 years agotarget-arm: A64: Add SIMD copy operations
Alex Bennée [Fri, 31 Jan 2014 14:47:31 +0000 (14:47 +0000)] 
target-arm: A64: Add SIMD copy operations

This adds support for the all the AdvSIMD vector copy operations
(ARM ARM 3.6.5).

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
8 years agotarget-arm: A64: Add SIMD across-lanes instructions
Michael Matz [Fri, 31 Jan 2014 14:47:31 +0000 (14:47 +0000)] 
target-arm: A64: Add SIMD across-lanes instructions

Add support for the SIMD "across lanes" instruction group (C3.6.4).

Signed-off-by: Michael Matz <matz@suse.de>
[PMM: Updated to current codebase, added fp min/max ops,
 added unallocated encoding checks]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
8 years agotarget-arm: A64: Add SIMD ZIP/UZP/TRN
Michael Matz [Fri, 31 Jan 2014 14:47:31 +0000 (14:47 +0000)] 
target-arm: A64: Add SIMD ZIP/UZP/TRN

Add support for the SIMD ZIP/UZIP/TRN instruction group
(C3.6.3).

Signed-off-by: Michael Matz <matz@suse.de>
[PMM: use new do_vec_get/set etc functions and generally update to new
 codebase standards; refactor to pull per-element loop outside switch]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
8 years agotarget-arm: A64: Add SIMD TBL/TBLX
Michael Matz [Fri, 31 Jan 2014 14:47:31 +0000 (14:47 +0000)] 
target-arm: A64: Add SIMD TBL/TBLX

Add support for the SIMD TBL/TBLX instructions (group C3.6.2).

Signed-off-by: Michael Matz <matz@suse.de>
[PMM: rewritten to do more of the decode in translate-a64.c,
 and to do only one 64 bit pass at a time in the helper]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
8 years agotarget-arm: A64: Add SIMD EXT
Peter Maydell [Fri, 31 Jan 2014 14:47:30 +0000 (14:47 +0000)] 
target-arm: A64: Add SIMD EXT

Add support for the SIMD EXT instruction (the only one in its
group, C3.6.1).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
8 years agotarget-arm: A64: Add decode skeleton for SIMD data processing insns
Alex Bennée [Fri, 31 Jan 2014 14:47:30 +0000 (14:47 +0000)] 
target-arm: A64: Add decode skeleton for SIMD data processing insns

Add decode skeleton and function placeholders for all the SIMD data
processing instructions. Due to the complexity of this part of the
table the normal extract and switch approach gets very messy very
quickly, so we use a simple data-driven pattern-and-mask approach.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
8 years agotarget-arm: A64: Add SIMD ld/st single
Peter Maydell [Fri, 31 Jan 2014 14:47:30 +0000 (14:47 +0000)] 
target-arm: A64: Add SIMD ld/st single

Implement the SIMD ld/st single structure instructions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
8 years agotarget-arm: A64: Add SIMD ld/st multiple
Alex Bennée [Fri, 31 Jan 2014 14:47:30 +0000 (14:47 +0000)] 
target-arm: A64: Add SIMD ld/st multiple

This adds support support for the SIMD load/store
multiple category of instructions.

This also brings in a couple of helper functions for manipulating
sections of the SIMD registers:

  * do_vec_get - fetch value from a slice of a vector register
  * do_vec_set - set a slice of a vector register

which use vec_reg_offset for consistent processing of offsets in an
endian aware manner. There are also additional helpers:

  * do_vec_ld - load value into SIMD
  * do_vec_st - store value from SIMD

which load or store a slice of a vector register to memory.
These don't zero extend like the fp variants.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
8 years agoMerge remote-tracking branch 'stefanha/tags/tracing-pull-request' into staging
Peter Maydell [Fri, 31 Jan 2014 11:13:08 +0000 (11:13 +0000)] 
Merge remote-tracking branch 'stefanha/tags/tracing-pull-request' into staging

Tracing pull request

# gpg: Signature made Mon 27 Jan 2014 14:51:09 GMT using RSA key ID 81AB73C8
# gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>"
# gpg:                 aka "Stefan Hajnoczi <stefanha@gmail.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35  775A 9CA4 ABB3 81AB 73C8

* stefanha/tags/tracing-pull-request:
  trace: fix simple trace "disable" keyword
  trace: add glib 2.32+ static GMutex support
  trace: [simple] Do not include "trace/simple.h" in generated tracer headers
  tracing: start trace processing thread in final child process

Message-id: 1390834386-23139-1-git-send-email-stefanha@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agos390x/kvm: cleanup partial register handling
Dominik Dingel [Tue, 1 Oct 2013 14:28:23 +0000 (16:28 +0200)] 
s390x/kvm: cleanup partial register handling

The partial register handling (introduced with commits
420840e58b85f7f4e5493dca3f273566f261090a and
3474b679486caa8f6448bae974e131370f360c13 ) aimed to improve intercept
handling performance.

It made the code more complicated though. During development for life
migration/init/reset etc it turned out that this might cause several
hard to debug programming errors. With the introduction of ioeventfd
(and future irqfd patches) the qemu intercept handlers are no longer
hot-path. And therefore the partial register handling can be
removed to simplify the code.

Signed-off-by: Dominik Dingel <dingel@linux.vnet.ibm.com>
CC: Jason J. Herne <jjherne@us.ibm.com>
Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
Acked-by: Alexander Graf <agraf@suse.de>
8 years agoMerge remote-tracking branch 'mst/tags/for_anthony' into staging
Peter Maydell [Fri, 31 Jan 2014 00:23:27 +0000 (00:23 +0000)] 
Merge remote-tracking branch 'mst/tags/for_anthony' into staging

acpi,pci,pc,virtio fixes and enhancements

This includes new unit-tests for acpi by Marcel,
hotplug for pci bridges by myself (piix only so far)
and cpu hotplug for q35.
And a bunch of fixes all over the place as usual.

I included the patch to fix memory alignment for q35
as well - even though it limits 32 bit guests to 3G (they
previously could address more memory with PAE).
To remove the limit, this will have to be fixed in seabios.

I also added self as virtio co-maintainer so I don't need
to troll the list for patches to review.

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
# gpg: Signature made Sun 26 Jan 2014 11:12:09 GMT using RSA key ID D28D5469
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>"
# gpg:                 aka "Michael S. Tsirkin <mst@redhat.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17  0970 C350 3912 AFBE 8E67
#      Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA  8A0D 281F 0DB8 D28D 5469

* mst/tags/for_anthony: (35 commits)
  MAINTAINERS: add self as virtio co-maintainer
  q35: document gigabyte_align
  q35: gigabyte alignment for ram
  acpi: Fix PCI hole handling on build_srat()
  pc: Save size of RAM below 4GB
  hw/pci: fix error flow in pci multifunction init
  acpi-test: update expected AML since recent changes
  pc: ACPI: update acpi-dsdt.hex.generated q35-acpi-dsdt.hex.generated
  pc: ACPI: unify source of CPU hotplug IO base/len
  pc: ACPI: expose PRST IO range via _CRS
  pc: Q35 DSDT: exclude CPU hotplug IO range from PCI bus resources
  pc: PIIX DSDT: exclude CPU/PCI hotplug & GPE0 IO range from PCI bus resources
  pc: set PRST base in DSDT depending on chipset
  acpi: ich9: add CPU hotplug handling to Q35 machine
  acpi: factor out common cpu hotplug code for PIIX4/Q35
  acpi-build: enable hotplug for PCI bridges
  piix4: add acpi pci hotplug support
  pcihp: generalization of piix4 acpi
  pci: add pci_for_each_bus_depth_first
  pc: make: fix dependencies: rebuild when included file is changed
  ...

Message-id: 1390735289-15563-1-git-send-email-mst@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agoMerge remote-tracking branch 'sstabellini/xen-170114' into staging
Peter Maydell [Fri, 31 Jan 2014 00:13:02 +0000 (00:13 +0000)] 
Merge remote-tracking branch 'sstabellini/xen-170114' into staging

* sstabellini/xen-170114:
  xen_pt: Fix passthrough of device with ROM.
  xen_pt: Fix debug output.
  xenfb: map framebuffer read-only and handle unmap errors

Message-id: alpine.DEB.2.02.1401171537140.21510@kaball.uk.xensource.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agoMerge remote-tracking branch 'stefanha/tags/net-pull-request' into staging
Peter Maydell [Thu, 30 Jan 2014 22:25:39 +0000 (22:25 +0000)] 
Merge remote-tracking branch 'stefanha/tags/net-pull-request' into staging

Net patches

# gpg: Signature made Mon 27 Jan 2014 14:45:35 GMT using RSA key ID 81AB73C8
# gpg: Can't check signature: public key not found

* stefanha/tags/net-pull-request:
  tap-linux: Get features once and use it many times
  Fix lan9118 buffer length handling
  Fix lan9118 TX "CMD A" handling
  net: Use g_strdup_printf instead of snprintf.

Message-id: 1390834129-19625-1-git-send-email-stefanha@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agoMerge remote-tracking branch 'rth/tcg-movbe' into staging
Peter Maydell [Thu, 30 Jan 2014 19:02:16 +0000 (19:02 +0000)] 
Merge remote-tracking branch 'rth/tcg-movbe' into staging

* rth/tcg-movbe:
  tcg/i386: cleanup useless #ifdef
  tcg/i386: use movbe instruction in qemu_ldst routines
  tcg/i386: add support for three-byte opcodes
  tcg/i386: remove hardcoded P_REXW value
  disas/i386.c: disassemble movbe instruction

Message-id: 1390692772-15282-1-git-send-email-rth@twiddle.net
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agoaddress_space_translate: do not cross page boundaries
Stefano Stabellini [Thu, 30 Jan 2014 12:46:05 +0000 (12:46 +0000)] 
address_space_translate: do not cross page boundaries

The following commit:

commit 149f54b53b7666a3facd45e86eece60ce7d3b114
Author: Paolo Bonzini <pbonzini@redhat.com>
Date:   Fri May 24 12:59:37 2013 +0200

    memory: add address_space_translate

breaks Xen support in QEMU, in particular the Xen mapcache. The effect
is that one Windows XP installation out of ten would end up with BSOD.

The reason is that after this commit l in address_space_rw can span a
page boundary, however qemu_get_ram_ptr still calls xen_map_cache asking
to map a single page (if block->offset == 0).

Fix the issue by reverting to the previous behaviour: do not return a
length from address_space_translate_internal that can span a page
boundary.

Also in address_space_translate do not ignore the length returned by
address_space_translate_internal.

This patch should be backported to QEMU 1.6.x.

Signed-off-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Signed-off-by: Anthony Perard <anthony.perard@citrix.com>
Tested-by: Paolo Bonzini <pbonzini@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Cc: qemu-stable@nongnu.org
8 years agoMerge remote-tracking branch 'mjt/tags/trivial-patches-2014-01-16' into staging
Peter Maydell [Thu, 30 Jan 2014 13:56:00 +0000 (13:56 +0000)] 
Merge remote-tracking branch 'mjt/tags/trivial-patches-2014-01-16' into staging

trivial-patches for 2014-01-16

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Message-id: 1389893719-16336-1-git-send-email-mjt@msgid.tls.msk.ru
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agoTCG: Fix I64-on-32bit-host temporaries
Alexander Graf [Sun, 19 Jan 2014 15:53:31 +0000 (16:53 +0100)] 
TCG: Fix I64-on-32bit-host temporaries

We have cache pools of temporaries that we can reuse later when they've
already been allocated before.

These cache pools differenciate between the target TCG variable type they
contain. So we have one pool for I32 and one pool for I64 variables.

On a 32bit system, we can't work with 64bit registers though. So instead we
spawn two I32 temporaries for every I64 temporary we create. All caching
works the same way as on a real 64-bit system though: We create a cache entry
in the 64bit array for the first i32 index.

However, when we free such a temporary we free it to the pool of its type
(which is always i32 on 32bit systems) rather than its base_type (which is
i64 or i32 depending on the variable). This means we put a temporary that
is of base_type == i64 into the i32 preallocated temporary pool.

Eventually, this results in failures like this on 32bit hosts:

  qemu-system-ppc64: tcg/tcg.c:515: tcg_temp_new_internal: Assertion `ts->base_type == type' failed.

This patch makes the free routine use the base_type instead for the free case,
so it's consistent with the temporary allocation. It fixes the above failure
for me.

Signed-off-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1390146811-59936-1-git-send-email-agraf@suse.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
8 years agomonitor: Cleanup mon->outbuf on write error
Stratos Psomadakis [Mon, 27 Jan 2014 10:30:15 +0000 (12:30 +0200)] 
monitor: Cleanup mon->outbuf on write error

In case monitor_flush() fails to write the contents of mon->outbuf to
the output device, mon->outbuf is not cleaned up properly. Check the
return code of the qemu_chr_fe_write() function and cleanup the outbuf
if it fails.

References: http://lists.nongnu.org/archive/html/qemu-devel/2014-01/msg02890.html

Signed-off-by: Stratos Psomadakis <psomas@grnet.gr>
Signed-off-by: Dimitris Aragiorgis <dimara@grnet.gr>
Signed-off-by: Luiz Capitulino <lcapitulino@redhat.com>
8 years agovirtio_rng: replace custom backend API with UserCreatable.complete() callback
Igor Mammedov [Thu, 16 Jan 2014 16:34:39 +0000 (17:34 +0100)] 
virtio_rng: replace custom backend API with UserCreatable.complete() callback

in addition fix default backend leak by releasing it if its
initialization failed.

Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Luiz Capitulino <lcapitulino@redhat.com>
8 years agoadd optional 2nd stage initialization to -object/object-add commands
Igor Mammedov [Thu, 16 Jan 2014 16:34:38 +0000 (17:34 +0100)] 
add optional 2nd stage initialization to -object/object-add commands

Introduces USER_CREATABLE interface that must be implemented by
objects which are designed to created with -object CLI option or
object-add QMP command.

Interface provides an ability to do an optional second stage
initialization of the object created with -object/object-add
commands. By providing complete() callback, which is called
after the object properties were set.

It allows to:
 * prevents misusing of -object/object-add by filtering out
   objects that are not designed for it.
 * generalize second stage backend initialization instead of
   adding custom APIs to perform it
 * early error detection of backend initialization at -object/
   object-add time rather than through a proxy DEVICE object
   that tries to use backend.

Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Luiz Capitulino <lcapitulino@redhat.com>
8 years agovl.c: -object: don't ignore duplicate 'id'
Igor Mammedov [Thu, 16 Jan 2014 16:34:37 +0000 (17:34 +0100)] 
vl.c: -object: don't ignore duplicate 'id'

object_property_add_child() may fail if 'id' matches
an already existing object. Which means an incorrect
command line.
So instead of silently ignoring error, report it and
terminate QEMU.

Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Luiz Capitulino <lcapitulino@redhat.com>
8 years agoobject_add: consolidate error handling
Igor Mammedov [Thu, 16 Jan 2014 16:34:36 +0000 (17:34 +0100)] 
object_add: consolidate error handling

Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Luiz Capitulino <lcapitulino@redhat.com>
8 years agovfio: correct debug macro typo
Bandan Das [Tue, 28 Jan 2014 15:23:19 +0000 (08:23 -0700)] 
vfio: correct debug macro typo

Change to DEBUG_VFIO in vfio_msi_interrupt() for debug
messages to get printed

Signed-off-by: Bandan Das <bsd@redhat.com>
Signed-off-by: Alex Williamson <alex.williamson@redhat.com>
8 years agosclp-s390: Define new SCLP codes and structures
Matthew Rosato [Mon, 27 Jan 2014 15:57:50 +0000 (10:57 -0500)] 
sclp-s390: Define new SCLP codes and structures

Define new SCLP codes and structures that will be needed for
s390 memory hotplug.

Signed-off-by: Matthew Rosato <mjrosato@linux.vnet.ibm.com>
Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
8 years agotrace: fix simple trace "disable" keyword
Stefan Hajnoczi [Wed, 15 Jan 2014 03:10:30 +0000 (11:10 +0800)] 
trace: fix simple trace "disable" keyword

The trace-events "disable" keyword turns an event into a nop at
compile-time.  This is important for high-frequency events that can
impact performance.

The "disable" keyword is currently broken in the simple trace backend.
This patch fixes the problem as follows:

Trace events are identified by their TraceEventID number.  When events
are disabled there are two options for assigning TraceEventID numbers:
1. Skip disabled events and don't assign them a number.
2. Assign numbers for all events regardless of the disabled keyword.

The simple trace backend and its binary file format uses approach #1.

The tracetool infrastructure has been using approach #2 for a while.

The result is that the numbers used in simple trace files do not
correspond with TraceEventIDs.  In trace/simple.c we assumed that they
are identical and therefore emitted bogus numbers.

This patch fixes the bug by using TraceEventID for trace_event_id()
while sticking to approach #1 for simple trace file numbers.  This
preserves simple trace file format compatibility.

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
8 years agotrace: add glib 2.32+ static GMutex support
Stefan Hajnoczi [Thu, 12 Dec 2013 14:50:11 +0000 (15:50 +0100)] 
trace: add glib 2.32+ static GMutex support

The GStaticMutex API was deprecated in glib 2.32.  We cannot switch over
to GMutex unconditionally since we would drop support for older glib
versions.  But the deprecated API warnings during build are annoying so
use static GMutex when possible.

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
8 years agotrace: [simple] Do not include "trace/simple.h" in generated tracer headers
Lluís Vilanova [Tue, 14 Jan 2014 15:52:55 +0000 (16:52 +0100)] 
trace: [simple] Do not include "trace/simple.h" in generated tracer headers

The header is not necessary, given that the simple backend does not define any
inlined tracing routines.

Signed-off-by: Lluís Vilanova <vilanova@ac.upc.edu>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
8 years agotracing: start trace processing thread in final child process
Michael Mueller [Mon, 23 Sep 2013 14:36:54 +0000 (16:36 +0200)] 
tracing: start trace processing thread in final child process

When running with trace backend e.g. "simple" the writer thread needs to be
implemented in the same process context as the trace points that will be
processed. Under libvirtd control, qemu gets first started in daemonized
mode to privide its capabilities. Creating the writer thread in the initial
process context then leads to a dead lock because the thread gets termined
together with the initial parent. (-daemonize)

Signed-off-by: Michael Mueller <mimu@linux.vnet.ibm.com>
Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
[minor whitespace fixes]
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
8 years agotap-linux: Get features once and use it many times
Kusanagi Kouichi [Sat, 18 Jan 2014 05:38:45 +0000 (14:38 +0900)] 
tap-linux: Get features once and use it many times

Signed-off-by: Kusanagi Kouichi <slash@ac.auone-net.jp>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
8 years agoFix lan9118 buffer length handling
Roy Franz [Wed, 8 Jan 2014 04:19:52 +0000 (20:19 -0800)] 
Fix lan9118 buffer length handling

The 9118 ethernet controller supports transmission of multi-buffer packets
with arbitrary byte alignment of the start and end bytes.  All writes to
the packet fifo are 32 bits, so the controller discards bytes at the beginning
and end of each buffer based on the 'Data start offset' and 'Buffer size'
of the TX command 'A' format.

This patch uses the provided buffer length to limit the bytes transmitted.
Previously all the bytes of the last 32-bit word written to the TX fifo
were added to the internal transmit buffer structure resulting in more bytes
being transmitted than were submitted to the hardware in the command.  This
resulted in extra bytes being inserted into the middle of multi-buffer
packets when the non-final buffers had non-32bit aligned ending addresses.

Signed-off-by: Roy Franz <roy.franz@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
8 years agoFix lan9118 TX "CMD A" handling
Roy Franz [Wed, 8 Jan 2014 04:19:51 +0000 (20:19 -0800)] 
Fix lan9118 TX "CMD A" handling

The 9118 ethernet controller supports transmission of multi-buffer packets
with arbitrary byte alignment of the start and end bytes.  All writes to
the packet fifo are 32 bits, so the controller discards bytes at the beginning
and end of each buffer based on the 'Data start offset' and 'Buffer size'
of the TX command 'A' format.

This patch changes the buffer size and offset internal state variables to be
updated on every "TX command A" write.  Previously they were only updated for
the first segment, which resulted incorrect behavior for packets with more
than one segment. Each segment of the packet has its own CMD A command, with
its own buffer size and start offset.

Also update extraction of fields from the CMD A word to use extract32().

Signed-off-by: Roy Franz <roy.franz@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
8 years agonet: Use g_strdup_printf instead of snprintf.
Hani Benhabiles [Thu, 9 Jan 2014 18:34:27 +0000 (19:34 +0100)] 
net: Use g_strdup_printf instead of snprintf.

assign_name() in net/net.c is using snprintf + g_strdup to get the same
result as g_strdup_printf.

Signed-off-by: Hani Benhabiles <kroosec@gmail.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
8 years agoMAINTAINERS: add self as virtio co-maintainer
Michael S. Tsirkin [Sun, 26 Jan 2014 10:39:55 +0000 (12:39 +0200)] 
MAINTAINERS: add self as virtio co-maintainer

This will help make sure I get Cc'd on patches.

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
8 years agoq35: document gigabyte_align
Michael S. Tsirkin [Mon, 16 Dec 2013 11:55:06 +0000 (13:55 +0200)] 
q35: document gigabyte_align

Document the logic behind the below/above 4G split.

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
8 years agoq35: gigabyte alignment for ram
Gerd Hoffmann [Mon, 16 Dec 2013 09:11:28 +0000 (10:11 +0100)] 
q35: gigabyte alignment for ram

Map 2G (q35) of memory below 4G, so the RAM pieces
are nicely aligned to gigabyte borders.

Keep old memory layout for (a) old machine types and (b) in case all
memory fits below 4G and thus we don't have to split RAM into pieces
in the first place.  The later makes sure this change doesn't take
away memory from 32bit guests.

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
8 years agoacpi: Fix PCI hole handling on build_srat()
Eduardo Habkost [Thu, 9 Jan 2014 19:12:43 +0000 (17:12 -0200)] 
acpi: Fix PCI hole handling on build_srat()

The original SeaBIOS code used the RamSize variable, that was used by
SeaBIOS for the size of RAM below 4GB, not for all RAM. When copied to
QEMU, the code was changed to use the full RAM size, and this broke the
build_srat() code that handles the PCI hole.

Change build_srat() to use ram_size_below_4g instead of ram_size, to
restore the original behavior from SeaBIOS.

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
8 years agopc: Save size of RAM below 4GB
Eduardo Habkost [Thu, 9 Jan 2014 19:12:42 +0000 (17:12 -0200)] 
pc: Save size of RAM below 4GB

The ram_below_4g value will be useful in other places, such as the ACPI
table code, and other code that currently requires passing
below_4g_mem_size around in function arguments.

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
8 years agohw/pci: fix error flow in pci multifunction init
Marcel Apfelbaum [Tue, 21 Jan 2014 16:37:51 +0000 (18:37 +0200)] 
hw/pci: fix error flow in pci multifunction init

Scenario:
  - There is a non multifunction pci device A on 00:0X.0.
  - Hot-plug another multifunction pci device B at 00:0X.1.
  - The operation will fail of course.
  - Try to hot-plug the B device 2-3 more times, qemu will crash.

Reason: The error flow leaves the B's address space into global address spaces
list, but the device object is freed. Fixed that.

Signed-off-by: Marcel Apfelbaum <marcel.a@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
8 years agoacpi-test: update expected AML since recent changes
Michael S. Tsirkin [Mon, 20 Jan 2014 12:00:12 +0000 (14:00 +0200)] 
acpi-test: update expected AML since recent changes

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
8 years agopc: ACPI: update acpi-dsdt.hex.generated q35-acpi-dsdt.hex.generated
Igor Mammedov [Thu, 9 Jan 2014 16:36:39 +0000 (17:36 +0100)] 
pc: ACPI: update acpi-dsdt.hex.generated q35-acpi-dsdt.hex.generated

Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
8 years agopc: ACPI: unify source of CPU hotplug IO base/len
Igor Mammedov [Thu, 9 Jan 2014 16:36:38 +0000 (17:36 +0100)] 
pc: ACPI: unify source of CPU hotplug IO base/len

use C headers defines as source of IO base/len for respective
values in ASL code.

Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
8 years agopc: ACPI: expose PRST IO range via _CRS
Igor Mammedov [Thu, 9 Jan 2014 16:36:37 +0000 (17:36 +0100)] 
pc: ACPI: expose PRST IO range via _CRS

.. so OSPM could notice resource conflict if there is any.

Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
8 years agopc: Q35 DSDT: exclude CPU hotplug IO range from PCI bus resources
Igor Mammedov [Thu, 9 Jan 2014 16:36:36 +0000 (17:36 +0100)] 
pc: Q35 DSDT: exclude CPU hotplug IO range from PCI bus resources

... for range defined at hw/acpi/ich9.c:ICH9_PROC_BASE

Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
8 years agopc: PIIX DSDT: exclude CPU/PCI hotplug & GPE0 IO range from PCI bus resources
Igor Mammedov [Thu, 9 Jan 2014 16:36:35 +0000 (17:36 +0100)] 
pc: PIIX DSDT: exclude CPU/PCI hotplug & GPE0 IO range from PCI bus resources

.. so that they might not be used by PCI devices.

Note:
Resort to concatenating templates with preprocessor help,
because 1.0b spec isn't supporting ConcatenateResTemplate,
as result Windows XP fails to execute PCI0._CRS method if
ConcatenateResTemplate() is used.

Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
8 years agopc: set PRST base in DSDT depending on chipset
Igor Mammedov [Thu, 9 Jan 2014 16:36:34 +0000 (17:36 +0100)] 
pc: set PRST base in DSDT depending on chipset

Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
8 years agoacpi: ich9: add CPU hotplug handling to Q35 machine
Igor Mammedov [Thu, 9 Jan 2014 16:36:32 +0000 (17:36 +0100)] 
acpi: ich9: add CPU hotplug handling to Q35 machine

.. use IO port 0cd8-0xcf7 range for CPU present bitmap

Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
8 years agoacpi: factor out common cpu hotplug code for PIIX4/Q35
Igor Mammedov [Thu, 9 Jan 2014 16:36:31 +0000 (17:36 +0100)] 
acpi: factor out common cpu hotplug code for PIIX4/Q35

.. so it could be used for adding CPU hotplug to Q35 machine

Add an additional header with that will be shared between
C and ASL code: include/hw/acpi/cpu_hotplug_defs.h

Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
8 years agoacpi-build: enable hotplug for PCI bridges
Michael S. Tsirkin [Mon, 14 Oct 2013 15:01:29 +0000 (18:01 +0300)] 
acpi-build: enable hotplug for PCI bridges

This enables support for device hotplug behind
pci bridges. Bridge devices themselves need
to be pre-configured on qemu command line.

Design:
    - at machine init time, assign "bsel" property to bridges with
      hotplug support
    - dynamically (At ACPI table read) generate ACPI code to handle
      hotplug events for each bridge with "bsel" property

Note: ACPI doesn't support adding or removing bridges by hotplug.
We detect and prevent removal of bridges by hotplug,
unless they were added by hotplug previously
(and so, are not described by ACPI).

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
8 years agopiix4: add acpi pci hotplug support
Michael S. Tsirkin [Mon, 14 Oct 2013 15:01:20 +0000 (18:01 +0300)] 
piix4: add acpi pci hotplug support

Add support for acpi pci hotplug using the
new infrastructure.
PIIX4 legacy interface is maintained as is for
machine types 1.7 and older.

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>