qemu.git
6 months agoqcow2: Add subcluster support to zero_in_l2_slice()
Alberto Garcia [Fri, 10 Jul 2020 16:13:04 +0000 (18:13 +0200)] 
qcow2: Add subcluster support to zero_in_l2_slice()

The QCOW_OFLAG_ZERO bit that indicates that a cluster reads as
zeroes is only used in standard L2 entries. Extended L2 entries use
individual 'all zeroes' bits for each subcluster.

This must be taken into account when updating the L2 entry and also
when deciding that an existing entry does not need to be updated.

Signed-off-by: Alberto Garcia <berto@igalia.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Message-Id: <b61d61606d8c9b367bd641ab37351ddb9172799a.1594396418.git.berto@igalia.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
6 months agoqcow2: Add subcluster support to qcow2_get_host_offset()
Alberto Garcia [Fri, 10 Jul 2020 16:13:03 +0000 (18:13 +0200)] 
qcow2: Add subcluster support to qcow2_get_host_offset()

The logic of this function remains pretty much the same, except that
it uses count_contiguous_subclusters(), which combines the logic of
count_contiguous_clusters() / count_contiguous_clusters_unallocated()
and checks individual subclusters.

qcow2_cluster_to_subcluster_type() is not necessary as a separate
function anymore so it's inlined into its caller.

Signed-off-by: Alberto Garcia <berto@igalia.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Message-Id: <d2193fd48653a350d80f0eca1c67b1d9053fb2f3.1594396418.git.berto@igalia.com>
[mreitz: Initialize expected_type to anything]
Signed-off-by: Max Reitz <mreitz@redhat.com>
6 months agoqcow2: Add subcluster support to calculate_l2_meta()
Alberto Garcia [Fri, 10 Jul 2020 16:13:02 +0000 (18:13 +0200)] 
qcow2: Add subcluster support to calculate_l2_meta()

If an image has subclusters then there are more copy-on-write
scenarios that we need to consider. Let's say we have a write request
from the middle of subcluster #3 until the end of the cluster:

1) If we are writing to a newly allocated cluster then we need
   copy-on-write. The previous contents of subclusters #0 to #3 must
   be copied to the new cluster. We can optimize this process by
   skipping all leading unallocated or zero subclusters (the status of
   those skipped subclusters will be reflected in the new L2 bitmap).

2) If we are overwriting an existing cluster:

   2.1) If subcluster #3 is unallocated or has the all-zeroes bit set
        then we need copy-on-write (on subcluster #3 only).

   2.2) If subcluster #3 was already allocated then there is no need
        for any copy-on-write. However we still need to update the L2
        bitmap to reflect possible changes in the allocation status of
        subclusters #4 to #31. Because of this, this function checks
        if all the overwritten subclusters are already allocated and
        in this case it returns without creating a new QCowL2Meta
        structure.

After all these changes l2meta_cow_start() and l2meta_cow_end()
are not necessarily cluster-aligned anymore. We need to update the
calculation of old_start and old_end in handle_dependencies() to
guarantee that no two requests try to write on the same cluster.

Signed-off-by: Alberto Garcia <berto@igalia.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Message-Id: <4292dd56e4446d386a2fe307311737a711c00708.1594396418.git.berto@igalia.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
6 months agoqcow2: Handle QCOW2_SUBCLUSTER_UNALLOCATED_ALLOC
Alberto Garcia [Fri, 10 Jul 2020 16:13:01 +0000 (18:13 +0200)] 
qcow2: Handle QCOW2_SUBCLUSTER_UNALLOCATED_ALLOC

When dealing with subcluster types there is a new value called
QCOW2_SUBCLUSTER_UNALLOCATED_ALLOC that has no equivalent in
QCow2ClusterType.

This patch handles that value in all places where subcluster types
are processed.

Signed-off-by: Alberto Garcia <berto@igalia.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-Id: <bf09e2e2439a468a901bb96ace411eed9ee50295.1594396418.git.berto@igalia.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
6 months agoqcow2: Replace QCOW2_CLUSTER_* with QCOW2_SUBCLUSTER_*
Alberto Garcia [Fri, 10 Jul 2020 16:13:00 +0000 (18:13 +0200)] 
qcow2: Replace QCOW2_CLUSTER_* with QCOW2_SUBCLUSTER_*

In order to support extended L2 entries some functions of the qcow2
driver need to start dealing with subclusters instead of clusters.

qcow2_get_host_offset() is modified to return the subcluster type
instead of the cluster type, and all callers are updated to replace
all values of QCow2ClusterType with their QCow2SubclusterType
equivalents.

This patch only changes the data types, there are no semantic changes.

Signed-off-by: Alberto Garcia <berto@igalia.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-Id: <f6c29737c295f32cbee74c903c30b01820363b34.1594396418.git.berto@igalia.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
6 months agoqcow2: Add cluster type parameter to qcow2_get_host_offset()
Alberto Garcia [Fri, 10 Jul 2020 16:12:59 +0000 (18:12 +0200)] 
qcow2: Add cluster type parameter to qcow2_get_host_offset()

This function returns an integer that can be either an error code or a
cluster type (a value from the QCow2ClusterType enum).

We are going to start using subcluster types instead of cluster types
in some functions so it's better to use the exact data types instead
of integers for clarity and in order to detect errors more easily.

This patch makes qcow2_get_host_offset() return 0 on success and
puts the returned cluster type in a separate parameter. There are no
semantic changes.

Signed-off-by: Alberto Garcia <berto@igalia.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-Id: <396b6eab1859a271551dcd7dcba77f8934aa3c3f.1594396418.git.berto@igalia.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
6 months agoqcow2: Add qcow2_cluster_is_allocated()
Alberto Garcia [Fri, 10 Jul 2020 16:12:58 +0000 (18:12 +0200)] 
qcow2: Add qcow2_cluster_is_allocated()

This helper function tells us if a cluster is allocated (that is,
there is an associated host offset for it).

Signed-off-by: Alberto Garcia <berto@igalia.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Message-Id: <6d8771c5c79cbdc6c519875a5078e1cc85856d63.1594396418.git.berto@igalia.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
6 months agoqcow2: Add qcow2_get_subcluster_range_type()
Alberto Garcia [Fri, 10 Jul 2020 16:12:57 +0000 (18:12 +0200)] 
qcow2: Add qcow2_get_subcluster_range_type()

There are situations in which we want to know how many contiguous
subclusters of the same type there are in a given cluster. This can be
done by simply iterating over the subclusters and repeatedly calling
qcow2_get_subcluster_type() for each one of them.

However once we determined the type of a subcluster we can check the
rest efficiently by counting the number of adjacent ones (or zeroes)
in the bitmap. This is what this function does.

Signed-off-by: Alberto Garcia <berto@igalia.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Message-Id: <db917263d568ec6ffb4a41cac3c9100f96bf6c18.1594396418.git.berto@igalia.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
6 months agoqcow2: Add QCow2SubclusterType and qcow2_get_subcluster_type()
Alberto Garcia [Fri, 10 Jul 2020 16:12:56 +0000 (18:12 +0200)] 
qcow2: Add QCow2SubclusterType and qcow2_get_subcluster_type()

This patch adds QCow2SubclusterType, which is the subcluster-level
version of QCow2ClusterType. All QCOW2_SUBCLUSTER_* values have the
the same meaning as their QCOW2_CLUSTER_* equivalents (when they
exist). See below for details and caveats.

In images without extended L2 entries clusters are treated as having
exactly one subcluster so it is possible to replace one data type with
the other while keeping the exact same semantics.

With extended L2 entries there are new possible values, and every
subcluster in the same cluster can obviously have a different
QCow2SubclusterType so functions need to be adapted to work on the
subcluster level.

There are several things that have to be taken into account:

  a) QCOW2_SUBCLUSTER_COMPRESSED means that the whole cluster is
     compressed. We do not support compression at the subcluster
     level.

  b) There are two different values for unallocated subclusters:
     QCOW2_SUBCLUSTER_UNALLOCATED_PLAIN which means that the whole
     cluster is unallocated, and QCOW2_SUBCLUSTER_UNALLOCATED_ALLOC
     which means that the cluster is allocated but the subcluster is
     not. The latter can only happen in images with extended L2
     entries.

  c) QCOW2_SUBCLUSTER_INVALID is used to detect the cases where an L2
     entry has a value that violates the specification. The caller is
     responsible for handling these situations.

     To prevent compatibility problems with images that have invalid
     values but are currently being read by QEMU without causing side
     effects, QCOW2_SUBCLUSTER_INVALID is only returned for images
     with extended L2 entries.

qcow2_cluster_to_subcluster_type() is added as a separate function
from qcow2_get_subcluster_type(), but this is only temporary and both
will be merged in a subsequent patch.

Signed-off-by: Alberto Garcia <berto@igalia.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Message-Id: <26ef38e270f25851c98b51278852b4c4a7f97e69.1594396418.git.berto@igalia.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
6 months agoqcow2: Update get/set_l2_entry() and add get/set_l2_bitmap()
Alberto Garcia [Fri, 10 Jul 2020 16:12:55 +0000 (18:12 +0200)] 
qcow2: Update get/set_l2_entry() and add get/set_l2_bitmap()

Extended L2 entries are 128-bit wide: 64 bits for the entry itself and
64 bits for the subcluster allocation bitmap.

In order to support them correctly get/set_l2_entry() need to be
updated so they take the entry width into account in order to
calculate the correct offset.

This patch also adds the get/set_l2_bitmap() functions that are
used to access the bitmaps. For convenience we allow calling
get_l2_bitmap() on images without subclusters. In this case the
returned value is always 0 and has no meaning.

Signed-off-by: Alberto Garcia <berto@igalia.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Message-Id: <6ee0f81ae3329c991de125618b3675e1e46acdbb.1594396418.git.berto@igalia.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
6 months agoqcow2: Add l2_entry_size()
Alberto Garcia [Fri, 10 Jul 2020 16:12:54 +0000 (18:12 +0200)] 
qcow2: Add l2_entry_size()

qcow2 images with subclusters have 128-bit L2 entries. The first 64
bits contain the same information as traditional images and the last
64 bits form a bitmap with the status of each individual subcluster.

Because of that we cannot assume that L2 entries are sizeof(uint64_t)
anymore. This function returns the proper value for the image.

Signed-off-by: Alberto Garcia <berto@igalia.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Message-Id: <d34d578bd0380e739e2dde3e8dd6187d3d249fa9.1594396418.git.berto@igalia.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
6 months agoqcow2: Add offset_into_subcluster() and size_to_subclusters()
Alberto Garcia [Fri, 10 Jul 2020 16:12:53 +0000 (18:12 +0200)] 
qcow2: Add offset_into_subcluster() and size_to_subclusters()

Like offset_into_cluster() and size_to_clusters(), but for
subclusters.

Signed-off-by: Alberto Garcia <berto@igalia.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Message-Id: <3cc2390dcdef3d234d47c741b708bd8734490862.1594396418.git.berto@igalia.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
6 months agoqcow2: Add offset_to_sc_index()
Alberto Garcia [Fri, 10 Jul 2020 16:12:52 +0000 (18:12 +0200)] 
qcow2: Add offset_to_sc_index()

For a given offset, return the subcluster number within its cluster
(i.e. with 32 subclusters per cluster it returns a number between 0
and 31).

Signed-off-by: Alberto Garcia <berto@igalia.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-Id: <56e3e4ac0d827c6a2f5f259106c5ddb7c4ca2653.1594396418.git.berto@igalia.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
6 months agoqcow2: Add subcluster-related fields to BDRVQcow2State
Alberto Garcia [Fri, 10 Jul 2020 16:12:51 +0000 (18:12 +0200)] 
qcow2: Add subcluster-related fields to BDRVQcow2State

This patch adds the following new fields to BDRVQcow2State:

- subclusters_per_cluster: Number of subclusters in a cluster
- subcluster_size: The size of each subcluster, in bytes
- subcluster_bits: No. of bits so 1 << subcluster_bits = subcluster_size

Images without subclusters are treated as if they had exactly one
subcluster per cluster (i.e. subcluster_size = cluster_size).

Signed-off-by: Alberto Garcia <berto@igalia.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-Id: <55bfeac86b092fa2c9d182a95cbeb479ff7eca4f.1594396418.git.berto@igalia.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
6 months agoqcow2: Add dummy has_subclusters() function
Alberto Garcia [Fri, 10 Jul 2020 16:12:50 +0000 (18:12 +0200)] 
qcow2: Add dummy has_subclusters() function

This function will be used by the qcow2 code to check if an image has
subclusters or not.

At the moment this simply returns false. Once all patches needed for
subcluster support are ready then QEMU will be able to create and
read images with subclusters and this function will return the actual
value.

Signed-off-by: Alberto Garcia <berto@igalia.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-Id: <905526221083581a1b7057bca1585487661c5c13.1594396418.git.berto@igalia.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
6 months agoqcow2: Document the Extended L2 Entries feature
Alberto Garcia [Fri, 10 Jul 2020 16:12:49 +0000 (18:12 +0200)] 
qcow2: Document the Extended L2 Entries feature

Subcluster allocation in qcow2 is implemented by extending the
existing L2 table entries and adding additional information to
indicate the allocation status of each subcluster.

This patch documents the changes to the qcow2 format and how they
affect the calculation of the L2 cache size.

Signed-off-by: Alberto Garcia <berto@igalia.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-Id: <5199f2e1c717bcaa58b48142c9062b803145ff7f.1594396418.git.berto@igalia.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
6 months agoqcow2: Add get_l2_entry() and set_l2_entry()
Alberto Garcia [Fri, 10 Jul 2020 16:12:48 +0000 (18:12 +0200)] 
qcow2: Add get_l2_entry() and set_l2_entry()

The size of an L2 entry is 64 bits, but if we want to have subclusters
we need extended L2 entries. This means that we have to access L2
tables and slices differently depending on whether an image has
extended L2 entries or not.

This patch replaces all l2_slice[] accesses with calls to
get_l2_entry() and set_l2_entry().

Signed-off-by: Alberto Garcia <berto@igalia.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-Id: <9586363531fec125ba1386e561762d3e4224e9fc.1594396418.git.berto@igalia.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
6 months agoqcow2: Process QCOW2_CLUSTER_ZERO_ALLOC clusters in handle_copied()
Alberto Garcia [Fri, 10 Jul 2020 16:12:47 +0000 (18:12 +0200)] 
qcow2: Process QCOW2_CLUSTER_ZERO_ALLOC clusters in handle_copied()

When writing to a qcow2 file there are two functions that take a
virtual offset and return a host offset, possibly allocating new
clusters if necessary:

   - handle_copied() looks for normal data clusters that are already
     allocated and have a reference count of 1. In those clusters we
     can simply write the data and there is no need to perform any
     copy-on-write.

   - handle_alloc() looks for clusters that do need copy-on-write,
     either because they haven't been allocated yet, because their
     reference count is != 1 or because they are ZERO_ALLOC clusters.

The ZERO_ALLOC case is a bit special because those are clusters that
are already allocated and they could perfectly be dealt with in
handle_copied() (as long as copy-on-write is performed when required).

In fact, there is extra code specifically for them in handle_alloc()
that tries to reuse the existing allocation if possible and frees them
otherwise.

This patch changes the handling of ZERO_ALLOC clusters so the
semantics of these two functions are now like this:

   - handle_copied() looks for clusters that are already allocated and
     which we can overwrite (NORMAL and ZERO_ALLOC clusters with a
     reference count of 1).

   - handle_alloc() looks for clusters for which we need a new
     allocation (all other cases).

One important difference after this change is that clusters found
in handle_copied() may now require copy-on-write, but this will be
necessary anyway once we add support for subclusters.

Signed-off-by: Alberto Garcia <berto@igalia.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Message-Id: <eb17fc938f6be7be2e8d8ff42763d2c19241f866.1594396418.git.berto@igalia.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
6 months agoqcow2: Split cluster_needs_cow() out of count_cow_clusters()
Alberto Garcia [Fri, 10 Jul 2020 16:12:46 +0000 (18:12 +0200)] 
qcow2: Split cluster_needs_cow() out of count_cow_clusters()

We are going to need it in other places.

Signed-off-by: Alberto Garcia <berto@igalia.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Message-Id: <65e5d9627ca2ebe7e62deaeddf60949c33067d9d.1594396418.git.berto@igalia.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
6 months agoqcow2: Add calculate_l2_meta()
Alberto Garcia [Fri, 10 Jul 2020 16:12:45 +0000 (18:12 +0200)] 
qcow2: Add calculate_l2_meta()

handle_alloc() creates a QCowL2Meta structure in order to update the
image metadata and perform the necessary copy-on-write operations.

This patch moves that code to a separate function so it can be used
from other places.

Signed-off-by: Alberto Garcia <berto@igalia.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Message-Id: <e5bc4a648dac31972bfa7a0e554be8064be78799.1594396418.git.berto@igalia.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
6 months agoqcow2: Convert qcow2_get_cluster_offset() into qcow2_get_host_offset()
Alberto Garcia [Fri, 10 Jul 2020 16:12:44 +0000 (18:12 +0200)] 
qcow2: Convert qcow2_get_cluster_offset() into qcow2_get_host_offset()

qcow2_get_cluster_offset() takes an (unaligned) guest offset and
returns the (aligned) offset of the corresponding cluster in the qcow2
image.

In practice none of the callers need to know where the cluster starts
so this patch makes the function calculate and return the final host
offset directly. The function is also renamed accordingly.

There is a pre-existing exception with compressed clusters: in this
case the function returns the complete cluster descriptor (containing
the offset and size of the compressed data). This does not change with
this patch but it is now documented.

Signed-off-by: Alberto Garcia <berto@igalia.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Message-Id: <ffae6cdc5ca8950e8280ac0f696dcc376cb07095.1594396418.git.berto@igalia.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
6 months agoqcow2: Make Qcow2AioTask store the full host offset
Alberto Garcia [Fri, 10 Jul 2020 16:12:43 +0000 (18:12 +0200)] 
qcow2: Make Qcow2AioTask store the full host offset

The file_cluster_offset field of Qcow2AioTask stores a cluster-aligned
host offset. In practice this is not very useful because all users(*)
of this structure need the final host offset into the cluster, which
they calculate using

   host_offset = file_cluster_offset + offset_into_cluster(s, offset)

There is no reason why Qcow2AioTask cannot store host_offset directly
and that is what this patch does.

(*) compressed clusters are the exception: in this case what
    file_cluster_offset was storing was the full compressed cluster
    descriptor (offset + size). This does not change with this patch
    but it is documented now.

Signed-off-by: Alberto Garcia <berto@igalia.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-Id: <07c4b15c644dcf06c9459f98846ac1c4ea96e26f.1594396418.git.berto@igalia.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
6 months agoMerge remote-tracking branch 'remotes/cschoenebeck/tags/pull-9p-20200812' into staging
Peter Maydell [Mon, 24 Aug 2020 15:39:52 +0000 (16:39 +0100)] 
Merge remote-tracking branch 'remotes/cschoenebeck/tags/pull-9p-20200812' into staging

9pfs: Fix severe performance issue of Treaddir requests.

# gpg: Signature made Wed 12 Aug 2020 11:06:21 BST
# gpg:                using RSA key 96D8D110CF7AF8084F88590134C2B58765A47395
# gpg:                issuer "qemu_oss@crudebyte.com"
# gpg: Good signature from "Christian Schoenebeck <qemu_oss@crudebyte.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: ECAB 1A45 4014 1413 BA38  4926 30DB 47C3 A012 D5F4
#      Subkey fingerprint: 96D8 D110 CF7A F808 4F88  5901 34C2 B587 65A4 7395

* remotes/cschoenebeck/tags/pull-9p-20200812:
  9pfs: clarify latency of v9fs_co_run_in_worker()
  9pfs: differentiate readdir lock between 9P2000.u vs. 9P2000.L
  9pfs: T_readdir latency optimization
  9pfs: add new function v9fs_co_readdir_many()
  9pfs: split out fs driver core of v9fs_co_readdir()
  9pfs: make v9fs_readdir_response_size() public
  tests/virtio-9p: added split readdir tests

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agoMerge remote-tracking branch 'remotes/edgar/tags/edgar/xilinx-next-2020-08-24.for...
Peter Maydell [Mon, 24 Aug 2020 13:54:17 +0000 (14:54 +0100)] 
Merge remote-tracking branch 'remotes/edgar/tags/edgar/xilinx-next-2020-08-24.for-upstream' into staging

For upstream.

# gpg: Signature made Mon 24 Aug 2020 10:53:42 BST
# gpg:                using RSA key AC44FEDC14F7F1EBEDBF415129C596780F6BCA83
# gpg: Good signature from "Edgar E. Iglesias (Xilinx key) <edgar.iglesias@xilinx.com>" [unknown]
# gpg:                 aka "Edgar E. Iglesias <edgar.iglesias@gmail.com>" [full]
# Primary key fingerprint: AC44 FEDC 14F7 F1EB EDBF  4151 29C5 9678 0F6B CA83

* remotes/edgar/tags/edgar/xilinx-next-2020-08-24.for-upstream:
  microblaze: petalogix-s3adsp1800: Add device-tree source
  microblaze: petalogix-ml605: Add device-tree source
  target/microblaze: mbar: Trap sleeps from user-space
  configure: microblaze: Enable mttcg
  target/microblaze: swx: Use atomic_cmpxchg
  target/microblaze: mbar: Add support for data-access barriers
  target/microblaze: mbar: Move LOG_DIS to before sleep
  target/microblaze: mbar: Transfer dc->rd to mbar_imm

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agoMerge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200824' into...
Peter Maydell [Mon, 24 Aug 2020 11:13:09 +0000 (12:13 +0100)] 
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200824' into staging

target-arm queue:
 * hw/cpu/a9mpcore: Verify the machine use Cortex-A9 cores
 * hw/arm/smmuv3: Implement SMMUv3.2 range-invalidation
 * docs/system/arm: Document the Xilinx Versal Virt board
 * target/arm: Make M-profile NOCP take precedence over UNDEF
 * target/arm: Use correct FPST for VCMLA, VCADD on fp16
 * target/arm: Various cleanups preparing for fp16 support

# gpg: Signature made Mon 24 Aug 2020 10:47:14 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20200824: (27 commits)
  target/arm: Use correct FPST for VCMLA, VCADD on fp16
  target/arm: Implement FPST_STD_F16 fpstatus
  target/arm: Make A32/T32 use new fpstatus_ptr() API
  target/arm: Replace A64 get_fpstatus_ptr() with generic fpstatus_ptr()
  target/arm: Delete unused ARM_FEATURE_CRC
  target/arm/translate.c: Delete/amend incorrect comments
  target/arm: Delete unused VFP_DREG macros
  target/arm: Remove ARCH macro
  target/arm: Convert T32 coprocessor insns to decodetree
  target/arm: Do M-profile NOCP checks early and via decodetree
  target/arm: Tidy up disas_arm_insn()
  target/arm: Convert A32 coprocessor insns to decodetree
  target/arm: Separate decode from handling of coproc insns
  target/arm: Pull handling of XScale insns out of disas_coproc_insn()
  docs/system/arm: Document the Xilinx Versal Virt board
  hw/arm/smmuv3: Advertise SMMUv3.2 range invalidation
  hw/arm/smmuv3: Support HAD and advertise SMMUv3.1 support
  hw/arm/smmuv3: Let AIDR advertise SMMUv3.0 support
  hw/arm/smmuv3: Fix IIDR offset
  hw/arm/smmuv3: Get prepared for range invalidation
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Use correct FPST for VCMLA, VCADD on fp16
Peter Maydell [Thu, 6 Aug 2020 10:44:53 +0000 (11:44 +0100)] 
target/arm: Use correct FPST for VCMLA, VCADD on fp16

When we implemented the VCMLA and VCADD insns we put in the
code to handle fp16, but left it using the standard fp status
flags. Correct them to use FPST_STD_F16 for fp16 operations.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20200806104453.30393-5-peter.maydell@linaro.org

6 months agotarget/arm: Implement FPST_STD_F16 fpstatus
Peter Maydell [Thu, 6 Aug 2020 10:44:52 +0000 (11:44 +0100)] 
target/arm: Implement FPST_STD_F16 fpstatus

Architecturally, Neon FP16 operations use the "standard FPSCR" like
all other Neon operations.  However, this is defined in the Arm ARM
pseudocode as "a fixed value, except that FZ16 (and AHP) follow the
FPSCR bits". In QEMU, the softfloat float_status doesn't include
separate flush-to-zero for FP16 operations, so we must keep separate
fp_status for "Neon non-FP16" and "Neon fp16" operations, in the
same way we do already for the non-Neon "fp_status" vs "fp_status_f16".

Add the extra float_status field to the CPU state structure,
ensure it is correctly initialized and updated on FPSCR writes,
and make fpstatus_ptr(FPST_STD_F16) return a pointer to it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20200806104453.30393-4-peter.maydell@linaro.org

6 months agotarget/arm: Make A32/T32 use new fpstatus_ptr() API
Peter Maydell [Thu, 6 Aug 2020 10:44:51 +0000 (11:44 +0100)] 
target/arm: Make A32/T32 use new fpstatus_ptr() API

Make A32/T32 code use the new fpstatus_ptr() API:
 get_fpstatus_ptr(0) -> fpstatus_ptr(FPST_FPCR)
 get_fpstatus_ptr(1) -> fpstatus_ptr(FPST_STD)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20200806104453.30393-3-peter.maydell@linaro.org

6 months agotarget/arm: Replace A64 get_fpstatus_ptr() with generic fpstatus_ptr()
Peter Maydell [Thu, 6 Aug 2020 10:44:50 +0000 (11:44 +0100)] 
target/arm: Replace A64 get_fpstatus_ptr() with generic fpstatus_ptr()

We currently have two versions of get_fpstatus_ptr(), which both take
an effectively boolean argument:
 * the one for A64 takes "bool is_f16" to distinguish fp16 from other ops
 * the one for A32/T32 takes "int neon" to distinguish Neon from other ops

This is confusing, and to implement ARMv8.2-FP16 the A32/T32 one will
need to make a four-way distinction between "non-Neon, FP16",
"non-Neon, single/double", "Neon, FP16" and "Neon, single/double".
The A64 version will then be a strict subset of the A32/T32 version.

To clean this all up, we want to go to a single implementation which
takes an enum argument with values FPST_FPCR, FPST_STD,
FPST_FPCR_F16, and FPST_STD_F16.  We rename the function to
fpstatus_ptr() so that unconverted code gets a compilation error
rather than silently passing the wrong thing to the new function.

This commit implements that new API, and converts A64 to use it:
 get_fpstatus_ptr(false) -> fpstatus_ptr(FPST_FPCR)
 get_fpstatus_ptr(true) -> fpstatus_ptr(FPST_FPCR_F16)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20200806104453.30393-2-peter.maydell@linaro.org

6 months agotarget/arm: Delete unused ARM_FEATURE_CRC
Peter Maydell [Wed, 5 Aug 2020 21:08:48 +0000 (22:08 +0100)] 
target/arm: Delete unused ARM_FEATURE_CRC

In commit 962fcbf2efe57231a9f5df we converted the uses of the
ARM_FEATURE_CRC bit to use the aa32_crc32 isar_feature test
instead. However we forgot to remove the now-unused definition
of the feature name in the enum. Delete it now.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200805210848.6688-1-peter.maydell@linaro.org

6 months agotarget/arm/translate.c: Delete/amend incorrect comments
Peter Maydell [Mon, 3 Aug 2020 13:28:15 +0000 (14:28 +0100)] 
target/arm/translate.c: Delete/amend incorrect comments

In arm_tr_init_disas_context() we have a FIXME comment that suggests
"cpu_M0 can probably be the same as cpu_V0".  This isn't in fact
possible: cpu_V0 is used as a temporary inside gen_iwmmxt_shift(),
and that function is called in various places where cpu_M0 contains a
live value (i.e.  between gen_op_iwmmxt_movq_M0_wRn() and
gen_op_iwmmxt_movq_wRn_M0() calls).  Remove the comment.

We also have a comment on the declarations of cpu_V0/V1/M0 which
claims they're "for efficiency".  This isn't true with modern TCG, so
replace this comment with one which notes that they're only used with
the iwmmxt decode.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200803132815.3861-1-peter.maydell@linaro.org

6 months agotarget/arm: Delete unused VFP_DREG macros
Peter Maydell [Mon, 3 Aug 2020 12:48:48 +0000 (13:48 +0100)] 
target/arm: Delete unused VFP_DREG macros

As part of the Neon decodetree conversion we removed all
the uses of the VFP_DREG macros, but forgot to remove the
macro definitions. Do so now.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20200803124848.18295-1-peter.maydell@linaro.org

6 months agotarget/arm: Remove ARCH macro
Peter Maydell [Mon, 3 Aug 2020 11:18:49 +0000 (12:18 +0100)] 
target/arm: Remove ARCH macro

The ARCH() macro was used a lot in the legacy decoder, but
there are now just two uses of it left. Since a macro which
expands out to a goto is liable to be confusing when reading
code, replace the last two uses with a simple open-coded
qeuivalent.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200803111849.13368-8-peter.maydell@linaro.org

6 months agotarget/arm: Convert T32 coprocessor insns to decodetree
Peter Maydell [Mon, 3 Aug 2020 11:18:48 +0000 (12:18 +0100)] 
target/arm: Convert T32 coprocessor insns to decodetree

Convert the T32 coprocessor instructions to decodetree.
As with the A32 conversion, this corrects an underdecoding
where we did not check that MRRC/MCRR [24:21] were 0b0010
and so treated some kinds of LDC/STC and MRRC/MCRR rather
than UNDEFing them.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200803111849.13368-7-peter.maydell@linaro.org

6 months agotarget/arm: Do M-profile NOCP checks early and via decodetree
Peter Maydell [Mon, 3 Aug 2020 11:18:47 +0000 (12:18 +0100)] 
target/arm: Do M-profile NOCP checks early and via decodetree

For M-profile CPUs, the architecture specifies that the NOCP
exception when a coprocessor is not present or disabled should cover
the entire wide range of coprocessor-space encodings, and should take
precedence over UNDEF exceptions.  (This is the opposite of
A-profile, where checking for a disabled FPU has to happen last.)

Implement this with decodetree patterns that cover the specified
ranges of the encoding space.  There are a few instructions (VLLDM,
VLSTM, and in v8.1 also VSCCLRM) which are in copro-space but must
not be NOCP'd: these must be handled also in the new m-nocp.decode so
they take precedence.

This is a minor behaviour change: for unallocated insn patterns in
the VFP area (cp=10,11) we will now NOCP rather than UNDEF when the
FPU is disabled.

As well as giving us the correct architectural behaviour for v8.1M
and the recommended behaviour for v8.0M, this refactoring also
removes the old NOCP handling from the remains of the 'legacy
decoder' in disas_thumb2_insn(), paving the way for cleaning that up.

Since we don't currently have a v8.1M feature bit or any v8.1M CPUs,
the minor changes to this logic that we'll need for v8.1M are marked
up with TODO comments.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200803111849.13368-6-peter.maydell@linaro.org

6 months agotarget/arm: Tidy up disas_arm_insn()
Peter Maydell [Mon, 3 Aug 2020 11:18:46 +0000 (12:18 +0100)] 
target/arm: Tidy up disas_arm_insn()

The only thing left in the "legacy decoder" is the handling
of disas_xscale_insn(), and we can simplify the code.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200803111849.13368-5-peter.maydell@linaro.org

6 months agotarget/arm: Convert A32 coprocessor insns to decodetree
Peter Maydell [Mon, 3 Aug 2020 11:18:45 +0000 (12:18 +0100)] 
target/arm: Convert A32 coprocessor insns to decodetree

Convert the A32 coprocessor instructions to decodetree.

Note that this corrects an underdecoding: for the 64-bit access case
(MRRC/MCRR) we did not check that bits [24:21] were 0b0010, so we
would incorrectly treat LDC/STC as MRRC/MCRR rather than UNDEFing
them.

The decodetree versions of these insns assume the coprocessor
is in the range 0..7 or 14..15. This is architecturally sensible
(as per the comments) and OK in practice for QEMU because the only
uses of the ARMCPRegInfo infrastructure we have that aren't
for coprocessors 14 or 15 are the pxa2xx use of coprocessor 6.
We add an assertion to the define_one_arm_cp_reg_with_opaque()
function to catch any accidental future attempts to use it to
define coprocessor registers for invalid coprocessors.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200803111849.13368-4-peter.maydell@linaro.org

6 months agotarget/arm: Separate decode from handling of coproc insns
Peter Maydell [Mon, 3 Aug 2020 11:18:44 +0000 (12:18 +0100)] 
target/arm: Separate decode from handling of coproc insns

As a prelude to making coproc insns use decodetree, split out the
part of disas_coproc_insn() which does instruction decoding from the
part which does the actual work, and make do_coproc_insn() handle the
UNDEF-on-bad-permissions and similar cases itself rather than
returning 1 to eventually percolate up to a callsite that calls
unallocated_encoding() for it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200803111849.13368-3-peter.maydell@linaro.org

6 months agotarget/arm: Pull handling of XScale insns out of disas_coproc_insn()
Peter Maydell [Mon, 3 Aug 2020 11:18:43 +0000 (12:18 +0100)] 
target/arm: Pull handling of XScale insns out of disas_coproc_insn()

At the moment we check for XScale/iwMMXt insns inside
disas_coproc_insn(): for CPUs with ARM_FEATURE_XSCALE all copro insns
with cp 0 or 1 are handled specially.  This works, but is an odd
place for this check, because disas_coproc_insn() is called from both
the Arm and Thumb decoders but the XScale case never applies for
Thumb (all the XScale CPUs were ARMv5, which has only Thumb1, not
Thumb2 with the 32-bit coprocessor insn encodings).  It also makes it
awkward to convert the real copro access insns to decodetree.

Move the identification of XScale out to its own function
which is only called from disas_arm_insn().

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200803111849.13368-2-peter.maydell@linaro.org

6 months agodocs/system/arm: Document the Xilinx Versal Virt board
Edgar E. Iglesias [Mon, 3 Aug 2020 16:47:49 +0000 (18:47 +0200)] 
docs/system/arm: Document the Xilinx Versal Virt board

Document the Xilinx Versal Virt board.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 20200803164749.301971-2-edgar.iglesias@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agohw/arm/smmuv3: Advertise SMMUv3.2 range invalidation
Eric Auger [Tue, 28 Jul 2020 15:08:15 +0000 (17:08 +0200)] 
hw/arm/smmuv3: Advertise SMMUv3.2 range invalidation

Expose the RIL bit so that the guest driver uses range
invalidation. Although RIL is a 3.2 features, We let
the AIDR advertise SMMUv3.1 support as v3.x implementation
is allowed to implement features from v3.(x+1).

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200728150815.11446-12-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agohw/arm/smmuv3: Support HAD and advertise SMMUv3.1 support
Eric Auger [Tue, 28 Jul 2020 15:08:14 +0000 (17:08 +0200)] 
hw/arm/smmuv3: Support HAD and advertise SMMUv3.1 support

HAD is a mandatory features with SMMUv3.1 if S1P is set, which is
our case. Other 3.1 mandatory features come with S2P which we don't
have.

So let's support HAD and advertise SMMUv3.1 support in AIDR.

HAD support allows the CD to disable hierarchical attributes, ie.
if the HAD0/1 bit is set, the APTable field of table descriptors
walked through TTB0/1 is ignored.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200728150815.11446-11-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agohw/arm/smmuv3: Let AIDR advertise SMMUv3.0 support
Eric Auger [Tue, 28 Jul 2020 15:08:13 +0000 (17:08 +0200)] 
hw/arm/smmuv3: Let AIDR advertise SMMUv3.0 support

Add the support for AIDR register. It currently advertises
SMMU V3.0 spec.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200728150815.11446-10-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agohw/arm/smmuv3: Fix IIDR offset
Eric Auger [Tue, 28 Jul 2020 15:08:12 +0000 (17:08 +0200)] 
hw/arm/smmuv3: Fix IIDR offset

The SMMU IIDR register is at 0x018 offset.

Fixes: 10a83cb9887 ("hw/arm/smmuv3: Skeleton")
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200728150815.11446-9-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agohw/arm/smmuv3: Get prepared for range invalidation
Eric Auger [Tue, 28 Jul 2020 15:08:11 +0000 (17:08 +0200)] 
hw/arm/smmuv3: Get prepared for range invalidation

Enhance the smmu_iotlb_inv_iova() helper with range invalidation.
This uses the new fields passed in the NH_VA and NH_VAA commands:
the size of the range, the level and the granule.

As NH_VA and NH_VAA both use those fields, their decoding and
handling is factorized in a new smmuv3_s1_range_inval() helper.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200728150815.11446-8-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agohw/arm/smmuv3: Introduce smmuv3_s1_range_inval() helper
Eric Auger [Tue, 28 Jul 2020 15:08:10 +0000 (17:08 +0200)] 
hw/arm/smmuv3: Introduce smmuv3_s1_range_inval() helper

Let's introduce an helper for S1 IOVA range invalidation.
This will be used for NH_VA and NH_VAA commands. It decodes
the same fields, trace, calls the UNMAP notifiers and
invalidate the corresponding IOTLB entries.

At the moment, we do not support 3.2 range invalidation yet.
So it reduces to a single IOVA invalidation.

Note the leaf bit now is also decoded for the CMD_TLBI_NH_VAA
command. At the moment it is only used for tracing.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200728150815.11446-7-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agohw/arm/smmu-common: Manage IOTLB block entries
Eric Auger [Tue, 28 Jul 2020 15:08:09 +0000 (17:08 +0200)] 
hw/arm/smmu-common: Manage IOTLB block entries

At the moment each entry in the IOTLB corresponds to a page sized
mapping (4K, 16K or 64K), even if the page belongs to a mapped
block. In case of block mapping this unefficiently consumes IOTLB
entries.

Change the value of the entry so that it reflects the actual
mapping it belongs to (block or page start address and size).

Also the level/tg of the entry is encoded in the key. In subsequent
patches we will enable range invalidation. This latter is able
to provide the level/tg of the entry.

Encoding the level/tg directly in the key will allow to invalidate
using g_hash_table_remove() when num_pages equals to 1.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200728150815.11446-6-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agohw/arm/smmu: Introduce SMMUTLBEntry for PTW and IOTLB value
Eric Auger [Tue, 28 Jul 2020 15:08:08 +0000 (17:08 +0200)] 
hw/arm/smmu: Introduce SMMUTLBEntry for PTW and IOTLB value

Introduce a specialized SMMUTLBEntry to store the result of
the PTW and cache in the IOTLB. This structure extends the
generic IOMMUTLBEntry struct with the level of the entry and
the granule size.

Those latter will be useful when implementing range invalidation.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200728150815.11446-5-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agohw/arm/smmu: Introduce smmu_get_iotlb_key()
Eric Auger [Tue, 28 Jul 2020 15:08:07 +0000 (17:08 +0200)] 
hw/arm/smmu: Introduce smmu_get_iotlb_key()

Introduce the smmu_get_iotlb_key() helper and the
SMMU_IOTLB_ASID() macro. Also move smmu_get_iotlb_key and
smmu_iotlb_key_hash in the IOTLB related code section.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200728150815.11446-4-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agohw/arm/smmu-common: Add IOTLB helpers
Eric Auger [Tue, 28 Jul 2020 15:08:06 +0000 (17:08 +0200)] 
hw/arm/smmu-common: Add IOTLB helpers

Add two helpers: one to lookup for a given IOTLB entry and
one to insert a new entry. We also move the tracing there.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200728150815.11446-3-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agohw/arm/smmu-common: Factorize some code in smmu_ptw_64()
Eric Auger [Tue, 28 Jul 2020 15:08:05 +0000 (17:08 +0200)] 
hw/arm/smmu-common: Factorize some code in smmu_ptw_64()

Page and block PTE decoding can share some code. Let's
first handle table PTE and factorize some code shared by
page and block PTEs.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200728150815.11446-2-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agohw/cpu/a9mpcore: Verify the machine use Cortex-A9 cores
Philippe Mathieu-Daudé [Thu, 9 Jul 2020 15:23:37 +0000 (17:23 +0200)] 
hw/cpu/a9mpcore: Verify the machine use Cortex-A9 cores

The 'Cortex-A9MPCore internal peripheral' block can only be
used with Cortex A5 and A9 cores. As we don't model the A5
yet, simply check the machine cpu core is a Cortex A9. If
not return an error.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200709152337.15533-1-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agomicroblaze: petalogix-s3adsp1800: Add device-tree source
Edgar E. Iglesias [Thu, 20 Aug 2020 19:19:26 +0000 (21:19 +0200)] 
microblaze: petalogix-s3adsp1800: Add device-tree source

Add a device-tree source for petalogix-s3adsp1800 and
recompile the DTB.

This also removes the unused mpmc node which causes
compilation warnings.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
6 months agomicroblaze: petalogix-ml605: Add device-tree source
Edgar E. Iglesias [Thu, 20 Aug 2020 19:17:45 +0000 (21:17 +0200)] 
microblaze: petalogix-ml605: Add device-tree source

Add a device-tree source for petalogix-ml605 and recompile
the DTB.

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
6 months agotarget/microblaze: mbar: Trap sleeps from user-space
Edgar E. Iglesias [Mon, 17 Aug 2020 17:07:19 +0000 (19:07 +0200)] 
target/microblaze: mbar: Trap sleeps from user-space

Trap mbar-sleeps from user-space.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reported-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
6 months agoconfigure: microblaze: Enable mttcg
Edgar E. Iglesias [Mon, 17 Aug 2020 09:42:48 +0000 (11:42 +0200)] 
configure: microblaze: Enable mttcg

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
6 months agotarget/microblaze: swx: Use atomic_cmpxchg
Edgar E. Iglesias [Fri, 14 Aug 2020 12:39:35 +0000 (14:39 +0200)] 
target/microblaze: swx: Use atomic_cmpxchg

Use atomic_cmpxchg to implement the atomic cmpxchg sequence.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
6 months agotarget/microblaze: mbar: Add support for data-access barriers
Edgar E. Iglesias [Thu, 13 Aug 2020 15:41:33 +0000 (17:41 +0200)] 
target/microblaze: mbar: Add support for data-access barriers

Add support for data-access barriers.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
6 months agotarget/microblaze: mbar: Move LOG_DIS to before sleep
Edgar E. Iglesias [Thu, 13 Aug 2020 15:28:35 +0000 (17:28 +0200)] 
target/microblaze: mbar: Move LOG_DIS to before sleep

Move LOG_DIS log to before sleeping handling so that it logs
for sleep instructions aswell.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
6 months agotarget/microblaze: mbar: Transfer dc->rd to mbar_imm
Edgar E. Iglesias [Thu, 13 Aug 2020 15:27:09 +0000 (17:27 +0200)] 
target/microblaze: mbar: Transfer dc->rd to mbar_imm

Transfer dc->rd to mbar_imm to improve the readability when
comparing to the specs.

No functional change.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
6 months agoMerge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.2-20200818' into staging
Peter Maydell [Mon, 24 Aug 2020 08:35:21 +0000 (09:35 +0100)] 
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-5.2-20200818' into staging

ppc patch queue 2020-08-18

Here's my first pull request for qemu-5.2, which has quite a few
accumulated things.  Highlights are:

 * Preliminary support for POWER10 (Power ISA 3.1) instruction emulation
 * Add documentation on the (very confusing) pseries NUMA configuration
 * Fix some bugs handling edge cases with XICS, XIVE and kernel_irqchip
 * Fix icount for a number of POWER registers
 * Many cleanups to error handling in XIVE code
 * Validate size of -prom-env data

# gpg: Signature made Tue 18 Aug 2020 05:18:36 BST
# gpg:                using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392
# gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full]
# gpg:                 aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full]
# gpg:                 aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full]
# gpg:                 aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown]
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-5.2-20200818: (40 commits)
  spapr/xive: Use xive_source_esb_len()
  nvram: Exit QEMU if NVRAM cannot contain all -prom-env data
  spapr/xive: Simplify error handling of kvmppc_xive_cpu_synchronize_state()
  ppc/xive: Simplify error handling in xive_tctx_realize()
  spapr/xive: Simplify error handling in kvmppc_xive_connect()
  ppc/xive: Fix error handling in vmstate_xive_tctx_*() callbacks
  spapr/xive: Fix error handling in kvmppc_xive_post_load()
  spapr/kvm: Fix error handling in kvmppc_xive_pre_save()
  spapr/xive: Rework error handling of kvmppc_xive_set_source_config()
  spapr/xive: Rework error handling in kvmppc_xive_get_queues()
  spapr/xive: Rework error handling of kvmppc_xive_[gs]et_queue_config()
  spapr/xive: Rework error handling of kvmppc_xive_cpu_[gs]et_state()
  spapr/xive: Rework error handling of kvmppc_xive_mmap()
  spapr/xive: Rework error handling of kvmppc_xive_source_reset()
  spapr/xive: Rework error handling of kvmppc_xive_cpu_connect()
  spapr: Simplify error handling in spapr_phb_realize()
  spapr/xive: Convert KVM device fd checks to assert()
  ppc/xive: Introduce dedicated kvm_irqchip_in_kernel() wrappers
  ppc/xive: Rework setup of XiveSource::esb_mmio
  target/ppc: Integrate icount to purr, vtb, and tbu40
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agoMerge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-5.2-pull-request...
Peter Maydell [Sun, 23 Aug 2020 15:34:43 +0000 (16:34 +0100)] 
Merge remote-tracking branch 'remotes/vivier2/tags/linux-user-for-5.2-pull-request' into staging

Add clock_getres_time64, timer_gettime64, timer_settime64,
    timerfd_gettime64, timerfd_settime64
Some fixes (page protection, print_fdset, timerspec, itimerspec)

# gpg: Signature made Sun 23 Aug 2020 15:58:53 BST
# gpg:                using RSA key CD2F75DDC8E3A4DC2E4F5173F30C38BD3F2FBE3C
# gpg:                issuer "laurent@vivier.eu"
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full]
# gpg:                 aka "Laurent Vivier <laurent@vivier.eu>" [full]
# gpg:                 aka "Laurent Vivier (Red Hat) <lvivier@redhat.com>" [full]
# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F  5173 F30C 38BD 3F2F BE3C

* remotes/vivier2/tags/linux-user-for-5.2-pull-request:
  linux-user: Fix 'utimensat()' implementation
  linux-user: Add support for a group of 2038 safe syscalls
  linux-user: Modify 'target_to_host/host_to_target_itimerspec()'
  linux-user: Adjust guest page protection for the host
  linux-user: Validate mmap/mprotect prot value
  linux-user: Fix "print_fdset()" in "strace.c" to not print ", " after last value

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agolinux-user: Fix 'utimensat()' implementation
Filip Bozuta [Tue, 11 Aug 2020 11:31:01 +0000 (13:31 +0200)] 
linux-user: Fix 'utimensat()' implementation

Implementation of syscall 'utimensat()' in 'syscall.c' uses functions
target_to_host/host_to_target_timespec() to convert values of
'struct timespec' between host and target. However, the implementation
doesn't check whether the conversion succeeds and thus can cause an
inappropriate error or succeed unappropriately instead of setting errno
EFAULT ('Bad address') which is supposed to be set in these cases.

This was confirmed with the LTP test for utimensat ('testcases/utimensat')
which fails for test cases when the errno EFAULT is expected. After changes
from this patch, the test passes for all test cases.

Signed-off-by: Filip Bozuta <Filip.Bozuta@syrmia.com>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Message-Id: <20200811113101.6636-1-Filip.Bozuta@syrmia.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
6 months agolinux-user: Add support for a group of 2038 safe syscalls
Filip Bozuta [Wed, 22 Jul 2020 15:34:21 +0000 (17:34 +0200)] 
linux-user: Add support for a group of 2038 safe syscalls

This patch implements functionality for following time64 syscalls:

*clock_getres_time64

     This a year 2038 safe variant of syscall:

     int clock_getres(clockid_t clockid, struct timespec *res)
     --finding the resoultion of a specified clock--
     man page: https://man7.org/linux/man-pages/man2/clock_getres.2.html

*timer_gettime64
*timer_settime64

     These are year 2038 safe variants of syscalls:

     int timer_settime(timer_t timerid, int flags,
                       const struct itimerspec *new_value,
                       struct itimerspec *old_value)
     int timer_gettime(timer_t timerid, struct itimerspec *curr_value)
     --arming/dissarming and fetching state of POSIX per-process timer--
     man page: https://man7.org/linux/man-pages/man2/timer_settime.2.html

*timerfd_gettime64
*timerfd_settime64

     These are year 2038 safe variants of syscalls:

     int timerfd_settime(int fd, int flags,
                         const struct itimerspec *new_value,
                         struct itimerspec *old_value)
     int timerfd_gettime(int fd, struct itimerspec *curr_value)
     --timers that notify via file descriptor--
     man page: https://man7.org/linux/man-pages/man2/timerfd_settime.2.html

Implementation notes:

     Syscall 'clock_getres_time64' was implemented similarly to 'clock_getres()'.
     The only difference was that for the conversion of 'struct timespec' from
     host to target, function 'host_to_target_timespec64()' was used instead of
     'host_to_target_timespec()'.

     For other syscalls, new functions 'host_to_target_itimerspec64()' and
     'target_to_host_itimerspec64()' were added to convert the value of the
     'struct itimerspec' from host to target and vice versa. A new type
     'struct target__kernel_itimerspec' was added in 'syscall_defs.h'. This
     type was defined with fields which are of the already defined type
     'struct target_timespec'. This new 'struct target__kernel_itimerspec'
     type is used in these new converting functions. These new functions were
     defined similarly to 'host_to_target_itimerspec()' and 'target_to_host_itimerspec()'
     the only difference being that 'target_to_host_timespec64()' and
     'host_to_target_timespec64()' were used.

Signed-off-by: Filip Bozuta <Filip.Bozuta@syrmia.com>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Message-Id: <20200722153421.295411-3-Filip.Bozuta@syrmia.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
6 months agolinux-user: Modify 'target_to_host/host_to_target_itimerspec()'
Filip Bozuta [Wed, 22 Jul 2020 15:34:20 +0000 (17:34 +0200)] 
linux-user: Modify 'target_to_host/host_to_target_itimerspec()'

Functions 'target_to_host_itimerspec()' and 'host_to_target_itimerspec()'
are used to convert values of type 'struct itimerspec' between target and
host. This type has 'struct timespec' as its fields. That is the reason
why this patch introduces a little modification to the converting functions
to be implemented using already existing functions that convert 'struct timespec':
'target_to_host_timespec()' and 'host_to_target_timespec()'. This makes the
code of 'target_to_host_itimerspec()' and 'host_to_target_itimerspec()' more
clean and readable.

Signed-off-by: Filip Bozuta <Filip.Bozuta@syrmia.com>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Message-Id: <20200722153421.295411-2-Filip.Bozuta@syrmia.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
6 months agolinux-user: Adjust guest page protection for the host
Richard Henderson [Tue, 19 May 2020 18:56:45 +0000 (11:56 -0700)] 
linux-user: Adjust guest page protection for the host

Executable guest pages are never directly executed by
the host, but do need to be readable for translation.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20200519185645.3915-3-richard.henderson@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
6 months agolinux-user: Validate mmap/mprotect prot value
Richard Henderson [Tue, 19 May 2020 18:56:44 +0000 (11:56 -0700)] 
linux-user: Validate mmap/mprotect prot value

The kernel will return -EINVAL for bits set in the prot argument
that are unknown or invalid.  Previously we were simply cropping
out the bits that we care about.

Introduce validate_prot_to_pageflags to perform this check in a
single place between the two syscalls.  Differentiate between
the target and host versions of prot.  Compute the qemu internal
page_flags value at the same time.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20200519185645.3915-2-richard.henderson@linaro.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
6 months agolinux-user: Fix "print_fdset()" in "strace.c" to not print ", " after last value
Filip Bozuta [Thu, 2 Jul 2020 16:09:15 +0000 (18:09 +0200)] 
linux-user: Fix "print_fdset()" in "strace.c" to not print ", " after last value

Function "print_fdset()" in "strace.c" is used to print the file descriptor
values in "print__newselect()" which prints arguments of syscall _newselect().
Until changes from this patch, this function was printing "," even after the
last value of the fd_set argument. This was changed in this patch by removing
this unnecessary "," after the last fd value and thus improving the estetics of
the _newselect() "-strace" print.

Implementation notes:

   The printing fix was made possible by using an existing function "get_comma()"
   which returns a "," or an empty string "" based on its argument (0 for "," and
   other for "").

Signed-off-by: Filip Bozuta <Filip.Bozuta@syrmia.com>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Message-Id: <20200702160915.9517-1-Filip.Bozuta@syrmia.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
6 months agoMerge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200821...
Peter Maydell [Sun, 23 Aug 2020 10:38:52 +0000 (11:38 +0100)] 
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20200821-1' into staging

The first RISC-V PR for the 5.2 window.

This includes:
 - NaNBox fixes
 - Vector extension improvements
 - a L2 cache controller
 - PMP fixes
 - Upgrade to OpenSBI v0.8 and the generic platform
 - Fixes for the Ibex PLIC

# gpg: Signature made Sat 22 Aug 2020 06:38:18 BST
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* remotes/alistair/tags/pull-riscv-to-apply-20200821-1:
  hw/intc: ibex_plic: Honour source priorities
  hw/intc: ibex_plic: Don't allow repeat interrupts on claimed lines
  hw/intc: ibex_plic: Update the pending irqs
  target/riscv: Change the TLB page size depends on PMP entries.
  target/riscv: Fix the translation of physical address
  gitlab-ci/opensbi: Update GitLab CI to build generic platform
  hw/riscv: spike: Change the default bios to use generic platform image
  hw/riscv: Use pre-built bios image of generic platform for virt & sifive_u
  roms/Makefile: Build the generic platform for RISC-V OpenSBI firmware
  roms/opensbi: Upgrade from v0.7 to v0.8
  configure: Create symbolic links for pc-bios/*.elf files
  riscv: Fix bug in setting pmpcfg CSR for RISCV64
  hw/riscv: sifive_u: Add a dummy L2 cache controller device
  target/riscv: check before allocating TCG temps
  target/riscv: Clean up fmv.w.x
  target/riscv: Check nanboxed inputs in trans_rvf.inc.c
  target/riscv: Check nanboxed inputs to fp helpers
  target/riscv: Generate nanboxed results from trans_rvf.inc.c
  target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s
  target/riscv: Generate nanboxed results from fp helpers

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agoMerge remote-tracking branch 'remotes/philmd-gitlab/tags/sd-next-20200821' into staging
Peter Maydell [Sat, 22 Aug 2020 22:53:08 +0000 (23:53 +0100)] 
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/sd-next-20200821' into staging

SD/MMC patches

- Convert legacy SD host controller to the SDBus API
- Move legacy API to a separate "sdcard_legacy.h" header
- Introduce methods to access multiple bytes on SDBus data lines
- Fix 'switch function' group location
- Fix SDSC maximum card size (2GB)

CI jobs result:
  https://gitlab.com/philmd/qemu/-/pipelines/180605963

# gpg: Signature made Fri 21 Aug 2020 18:27:50 BST
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* remotes/philmd-gitlab/tags/sd-next-20200821: (23 commits)
  hw/sd: Correct the maximum size of a Standard Capacity SD Memory Card
  hw/sd: Fix incorrect populated function switch status data structure
  hw/sd: Use sdbus_read_data() instead of sdbus_read_byte() when possible
  hw/sd: Add sdbus_read_data() to read multiples bytes on the data line
  hw/sd: Use sdbus_write_data() instead of sdbus_write_byte when possible
  hw/sd: Add sdbus_write_data() to write multiples bytes on the data line
  hw/sd: Rename sdbus_read_data() as sdbus_read_byte()
  hw/sd: Rename sdbus_write_data() as sdbus_write_byte()
  hw/sd: Rename read/write_data() as read/write_byte()
  hw/sd: Move sdcard legacy API to 'hw/sd/sdcard_legacy.h'
  hw/sd/sdcard: Make sd_data_ready() static
  hw/sd/pl181: Replace disabled fprintf()s by trace events
  hw/sd/pl181: Do not create SD card within the SD host controller
  hw/sd/pl181: Expose a SDBus and connect the SDCard to it
  hw/sd/pl181: Use named GPIOs
  hw/sd/pl181: Add TODO to use Fifo32 API
  hw/sd/pl181: Rename pl181_send_command() as pl181_do_command()
  hw/sd/pl181: Replace fprintf(stderr, "*\n") with error_report()
  hw/sd/milkymist: Do not create SD card within the SD host controller
  hw/sd/milkymist: Create the SDBus at init()
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agoMerge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging
Peter Maydell [Sat, 22 Aug 2020 20:59:08 +0000 (21:59 +0100)] 
Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging

meson fixes:

* --disable-tools --enable-system build
* s390 no-TCG build
* fdmon-io_uring
* 'shift' error message in version_ge()

# gpg: Signature made Fri 21 Aug 2020 22:12:29 BST
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# gpg:                issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg:                 aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4  E2F7 7E15 100C CD36 69B1
#      Subkey fingerprint: F133 3857 4B66 2389 866C  7682 BFFB D25F 78C7 AE83

* remotes/bonzini-gitlab/tags/for-upstream:
  keymaps: update
  meson: Fix --disable-tools --enable-system builds
  meson: convert pc-bios/keymaps/Makefile
  configure: silence 'shift' error message in version_ge()
  util/meson.build: fix fdmon-io_uring build
  target/s390x: fix meson.build issue

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agoMerge remote-tracking branch 'remotes/ericb/tags/pull-bitmaps-2020-08-21' into staging
Peter Maydell [Sat, 22 Aug 2020 18:57:23 +0000 (19:57 +0100)] 
Merge remote-tracking branch 'remotes/ericb/tags/pull-bitmaps-2020-08-21' into staging

bitmaps patches for 2020-08-21

- Andrey Shinkevich: Enhance qcow2.py for iotest inspection of qcow2 images
- Max Reitz: Add block-bitmap-mapping migration parameter

# gpg: Signature made Fri 21 Aug 2020 15:05:07 BST
# gpg:                using RSA key 71C2CC22B1C4602927D2F3AAA7A16B4A2527436A
# gpg: Good signature from "Eric Blake <eblake@redhat.com>" [full]
# gpg:                 aka "Eric Blake (Free Software Programmer) <ebb9@byu.net>" [full]
# gpg:                 aka "[jpeg image of size 6874]" [full]
# Primary key fingerprint: 71C2 CC22 B1C4 6029 27D2  F3AA A7A1 6B4A 2527 436A

* remotes/ericb/tags/pull-bitmaps-2020-08-21:
  iotests: Test node/bitmap aliases during migration
  iotests.py: Let wait_migration() return on failure
  migration: Add block-bitmap-mapping parameter
  iotests: dump QCOW2 header in JSON in #303
  qcow2_format.py: support dumping metadata in JSON format
  qcow2_format.py: collect fields to dump in JSON format
  qcow2.py: Introduce '-j' key to dump in JSON format
  qcow2_format.py: Dump bitmap table serialized entries
  qcow2_format.py: pass cluster size to substructures
  qcow2_format.py: Dump bitmap directory information
  qcow2_format.py: dump bitmap flags in human readable way.
  qcow2_format.py: change Qcow2BitmapExt initialization method
  qcow2_format.py: make printable data an extension class member
  iotests: add test for QCOW2 header dump

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agoMerge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request' into...
Peter Maydell [Sat, 22 Aug 2020 13:37:31 +0000 (14:37 +0100)] 
Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request' into staging

Machine queue 2020-08-19

Regular post-release changes:
* hw: add compat machines for 5.2 (Cornelia Huck)

Features:
* qmp: Expose MachineClass::default_ram_id
  (Michal Privoznik)

Cleanups:
* qdev: Document qdev_prop_set_drive_err() return value
  (Philippe Mathieu-Daudé)

# gpg: Signature made Wed 19 Aug 2020 16:21:55 BST
# gpg:                using RSA key 5A322FD5ABC4D3DBACCFD1AA2807936F984DC5A6
# gpg:                issuer "ehabkost@redhat.com"
# gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full]
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* remotes/ehabkost/tags/machine-next-pull-request:
  hw: add compat machines for 5.2
  qmp: Expose MachineClass::default_ram_id
  qdev: Document qdev_prop_set_drive_err() return value

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agohw/intc: ibex_plic: Honour source priorities
Alistair Francis [Sat, 25 Jul 2020 05:34:45 +0000 (22:34 -0700)] 
hw/intc: ibex_plic: Honour source priorities

This patch follows what commit aa4d30f6618dc "riscv: plic: Honour source
priorities" does and ensures that the highest priority interrupt will be
serviced first.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Cc: Jessica Clarke <jrtc27@jrtc27.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <a697ca8a31eff8eb18a88e09a28206063cf85d48.1595655188.git.alistair.francis@wdc.com>

6 months agohw/intc: ibex_plic: Don't allow repeat interrupts on claimed lines
Alistair Francis [Sat, 25 Jul 2020 05:34:43 +0000 (22:34 -0700)] 
hw/intc: ibex_plic: Don't allow repeat interrupts on claimed lines

Once an interrupt has been claimed, but before it has been compelted we
shouldn't receive any more pending interrupts. This patche keeps track
of this to ensure that we don't see any more interrupts until it is
completed.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <394c3f070615ff2b4fab61a1cf9cb48c122913b7.1595655188.git.alistair.francis@wdc.com>

6 months agohw/intc: ibex_plic: Update the pending irqs
Alistair Francis [Sat, 25 Jul 2020 05:34:40 +0000 (22:34 -0700)] 
hw/intc: ibex_plic: Update the pending irqs

After a claim or a priority change we need to update the pending
interrupts. This is based on the same patch for the SiFive PLIC:
55765822804f5a58594e "riscv: plic: Add a couple of mising
sifive_plic_update calls"

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Cc: Jessica Clarke <jrtc27@jrtc27.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <0693aa700a4c67c49b3f1c973a82b257fdb7198d.1595655188.git.alistair.francis@wdc.com>

6 months agotarget/riscv: Change the TLB page size depends on PMP entries.
Zong Li [Tue, 28 Jul 2020 08:26:17 +0000 (16:26 +0800)] 
target/riscv: Change the TLB page size depends on PMP entries.

The minimum granularity of PMP is 4 bytes, it is small than 4KB page
size, therefore, the pmp checking would be ignored if its range doesn't
start from the alignment of one page. This patch detects the pmp entries
and sets the small page size to TLB if there is a PMP entry which cover
the page size.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <6b0bf48662ef26ab4c15381a08e78a74ebd7ca79.1595924470.git.zong.li@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 months agotarget/riscv: Fix the translation of physical address
Zong Li [Tue, 28 Jul 2020 08:26:16 +0000 (16:26 +0800)] 
target/riscv: Fix the translation of physical address

The real physical address should add the 12 bits page offset. It also
causes the PMP wrong checking due to the minimum granularity of PMP is
4 byte, but we always get the physical address which is 4KB alignment,
that means, we always use the start address of the page to check PMP for
all addresses which in the same page.

Signed-off-by: Zong Li <zong.li@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <370a983d0f9e8a9a927b9bb8af5e7bc84b1bf9b1.1595924470.git.zong.li@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 months agogitlab-ci/opensbi: Update GitLab CI to build generic platform
Bin Meng [Fri, 1 May 2020 13:30:54 +0000 (21:30 +0800)] 
gitlab-ci/opensbi: Update GitLab CI to build generic platform

This updates the GitLab CI opensbi job to build opensbi bios images
for the generic platform.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1596439832-29238-7-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 months agohw/riscv: spike: Change the default bios to use generic platform image
Bin Meng [Fri, 1 May 2020 12:26:49 +0000 (20:26 +0800)] 
hw/riscv: spike: Change the default bios to use generic platform image

To keep sync with other RISC-V machines, change the default bios to
use generic platform fw_dynamic.elf image.

While we are here, add some comments to mention that using ELF files
for the Spike machine was intentional.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1596439832-29238-6-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 months agohw/riscv: Use pre-built bios image of generic platform for virt & sifive_u
Bin Meng [Fri, 1 May 2020 13:45:55 +0000 (21:45 +0800)] 
hw/riscv: Use pre-built bios image of generic platform for virt & sifive_u

Update virt and sifive_u machines to use the opensbi fw_dynamic bios
image built for the generic FDT platform.

Remove the out-of-date no longer used bios images.

Note:

1. To test 32-bit Linux kernel on QEMU 'sifive_u' 32-bit machine,
   the following patch is needed:
   http://lists.infradead.org/pipermail/linux-riscv/2020-July/001213.html

2. To test 64-bit Linux 5.3 kernel on QEMU 'virt' or 'sifive_u' 64-bit
   machines, the following commit should be cherry-picked to 5.3:

   commit 922b0375fc93fb1a20c5617e37c389c26bbccb70
   Author: Albert Ou <aou@eecs.berkeley.edu>
   Date:   Fri Sep 27 16:14:18 2019 -0700

       riscv: Fix memblock reservation for device tree blob

   Linux 5.4 or above already contains this commit/fix.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1596439832-29238-5-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 months agoroms/Makefile: Build the generic platform for RISC-V OpenSBI firmware
Bin Meng [Mon, 22 Jun 2020 02:03:17 +0000 (10:03 +0800)] 
roms/Makefile: Build the generic platform for RISC-V OpenSBI firmware

The RISC-V generic platform is a flattened device tree (FDT) based
platform where all platform specific functionality is provided based
on FDT passed by previous booting stage. The support was added in
the upstream OpenSBI v0.8 release recently.

Update our Makefile to build the generic platform instead of building
virt and sifive_u separately for RISC-V OpenSBI firmware, and change
to use fw_dynamic type images as well.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1596439832-29238-4-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 months agoroms/opensbi: Upgrade from v0.7 to v0.8
Bin Meng [Fri, 1 May 2020 13:23:02 +0000 (21:23 +0800)] 
roms/opensbi: Upgrade from v0.7 to v0.8

Upgrade OpenSBI from v0.7 to v0.8.

The v0.8 release includes the following commits:

1bb00ab lib: No need to provide default PMP region using platform callbacks
a9eac67 include: sbi_platform: Combine reboot and shutdown into one callback
6585fab lib: utils: Add SiFive test device
4781545 platform: Add Nuclei UX600 platform
3a326af scripts: adapt binary archive script for Nuclei UX600
5bdf022 firmware: fw_base: Remove CSR_MTVEC update check
e6c1345 lib: utils/serial: Skip baudrate config if input frequency is zero
01a8c8e lib: utils: Improve fdt_parse_uart8250() API
0a0093b lib: utils: Add fdt_parse_uart8250_node() function
243b0d0 lib: utils: Remove redundant clint_ipi_sync() declaration
e3ad7c1 lib: utils: Rename fdt_parse_clint() to fdt_parse_compat_addr()
a39cd6f lib: utils: Add FDT match table based node lookup
dd33b9e lib: utils: Make fdt_get_node_addr_size() public function
66185b3 lib: utils: Add fdt_parse_sifive_uart_node() function
19e966b lib: utils: Add fdt_parse_hart_id() function
44dd7be lib: utils: Add fdt_parse_max_hart_id() API
f0eb503 lib: utils: Add fdt_parse_plic_node() function
1ac794c include: Add array_size() macro
8ff2b94 lib: utils: Add simple FDT timer framework
76f0f81 lib: utils: Add simple FDT ipi framework
75322a6 lib: utils: Add simple FDT irqchip framework
76a8940 lib: utils: Add simple FDT serial framework
7cc6fa4 lib: utils: Add simple FDT reset framework
4d06353 firmware: fw_base: Introduce optional fw_platform_init()
f1aa9e5 platform: Add generic FDT based platform support
1f21b99 lib: sbi: Print platform hart count at boot time
2ba7087 scripts: Add generic platform to create-binary-archive.sh
4f18c6e platform: generic: Add Sifive FU540 TLB flush range limit override
13717a8 platform: Remove qemu/virt directory
65c06b0 platform: Remove spike directory
d626037 docs: Add missing links in platform.md
7993ca2 include: sbi: Remove redundant page table related defines
5338679 lib: sbi_tlb: Fix remote TLB HFENCE VVMA implementation
dc38929 lib: sbi: Improve misa_string() implementation
433bac7 docs: platform/generic: Add details about stdout-path DT property
b4efa70 docs: platform/generic: Add details about IPI and timer expectations
dfd9dd6 docs: Add platform requirements document
c2286b6 docs: Fix ordering of pages in table of contents
7be75f5 docs: Don't use italic text in page title
63a513e lib: Rename unprivileged trap handler
aef9a60 lib: Add csr detect support
13ca20d lib: Create a separate math helper function file
79d0fad lib: utils: Update reserved memory fdt node even if PMP is not present
6a053f6 lib: Add support for hart specific features
b2df751 platform: Move platform features to hart
4938024 platform: fpga: Remove redundant platform specific features
ec0d2a7 lib: timer: Provide a hart based timer feature
1f235ec lib: Add platform features in boot time print
22c4334 lib: Add hart features in boot time print
36833ab lib: Optimize inline assembly for unprivilege access functions
38a4b54 firmware: Correct spelling mistakes
28b4052 lib: sbi: detect features before everything else in sbi_hart_init()
4984183 lib: sbi: Improve get_feature_str() implementation and usage
3aa1036 lib: sbi: Remove extra spaces from boot time prints
3a8fc81 lib: sbi: Print platform HART count just before boot HART id
63b0f5f include: sbi: Use scratch pointer as parmeter in HART feature APIs
2966510 lib: sbi: Few cosmetic improvements to HART feature detection
a38bea9 lib: sbi_hart: Detect number of supported PMP regions
89ba634 include: sbi: Add firmware extension constants
73d6ef3 lib: utils: Remove redundant parameters from PLIC init functions
446a9c6 lib: utils: Allow PLIC functions to be used for multiple PLICs
2c685c2 lib: utils: Extend fdt_find_match() Implementation
d30bb68 lib: utils/irqchip: Initialize all matching irqchip DT nodes
a9a9751 lib: utils: Allow CLINT functions to be used for multiple CLINTs
569dd64 lib: utils: Add fdt_parse_clint_node() function
6956e83 lib: utils/ipi: Initialize all matching ipi DT nodes
a63f05f lib: utils/timer: Initialize all matching timer DT nodes
30b6040 Makefile: Fix builtin DTB compilation for out-of-tree platforms
64f1408 firmware: fw_base: Make builtin DTB available to fw_platform_init()
4ce6b7a firmware: fw_base: Don't OR forced FW_OPTIONS
86ec534 firmware: Allow fw_platform_init() to return updated FDT location
c6c65ee Makefile: Preprocess builtin DTS
4e3876d Makefile: Add mechanism for platforms to have multiple builtin DTBs
72019ee platform: kendryte/k210: Use new mechanism of builtin DTB
51f0e4a firmware: Remove FW_PAYLOAD_FDT and related documentation
1b8c012 lib: Add RISC-V hypervisor v0.6.1 support
79bfd67 docs: Use doxygen config to mark the main page
106b888 docs: Remove redundant documentation about combined payload use case
9802906 platform: Add AE350 platform specific SBI handler
32f87e5 platform: Add AE350 cache control SBIs
e2c3f01 lib: Fix __sbi_hfence_gvma_vmid_gpa() and __sbi_hfence_vvma_asid_va()
6966ad0 platform/lib: Allow the OS to map the regions that are protected by PMP
518e85c platform: Update Nuclei ux600 platform support
d5725c2 lib: Don't print delegation CSRs if there is no S-Mode
637b348 lib: Fix the SBI_HART_HAS_MCOUNTEREN feature check
db56ef3 platform: Add support for Shakti C-class SoC from IIT-M
9bd5f8f lib: sbi: Fix 32/64 bits variable compatibility
2314101 lib: Don't return any invalid error from SBI ecall
a98258d include: Bump-up version to 0.8

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Anup Patel <anup@brainfault.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1596439832-29238-3-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 months agoconfigure: Create symbolic links for pc-bios/*.elf files
Bin Meng [Mon, 22 Jun 2020 05:09:32 +0000 (13:09 +0800)] 
configure: Create symbolic links for pc-bios/*.elf files

Now we need to ship the OpenSBI fw_dynamic.elf image for the
RISC-V Spike machine, it requires us to create symbolic links
for pc-bios/*.elf files.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1596439832-29238-2-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 months agoriscv: Fix bug in setting pmpcfg CSR for RISCV64
Hou Weiying [Sat, 8 Aug 2020 08:56:40 +0000 (16:56 +0800)] 
riscv: Fix bug in setting pmpcfg CSR for RISCV64

First, sizeof(target_ulong) equals to 4 on riscv32, so this change
does not change the function on riscv32. Second, sizeof(target_ulong)
equals to 8 on riscv64, and 'reg_index * 8 + i' is not a legal
pmp_index (we will explain later), which should be 'reg_index * 4 + i'.

If the parameter reg_index equals to 2 (means that we will change the
value of pmpcfg2, or the second pmpcfg on riscv64), then
pmpcfg_csr_write(env, 2, val) will map write tasks to
pmp_write_cfg(env, 2 * 8 + [0...7], val). However, no cfg csr is indexed
by value 16 or 23 on riscv64, so we consider it as a bug.

We are looking for constant (e.g., define a new constant named
RISCV_WORD_SIZE) in QEMU to help others understand code better,
but none was found. A possible good explanation of this literal is it is
the minimum word length on riscv is 4 bytes (32 bit).

Signed-off-by: Hongzheng-Li <Ethan.Lee.QNL@gmail.com>
Signed-off-by: Hou Weiying <weiying_hou@outlook.com>
Signed-off-by: Myriad-Dreamin <camiyoru@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <SG2PR02MB263420036254AC8841F66CE393460@SG2PR02MB2634.apcprd02.prod.outlook.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 months agohw/riscv: sifive_u: Add a dummy L2 cache controller device
Bin Meng [Mon, 20 Jul 2020 06:49:08 +0000 (23:49 -0700)] 
hw/riscv: sifive_u: Add a dummy L2 cache controller device

It is enough to simply map the SiFive FU540 L2 cache controller
into the MMIO space using create_unimplemented_device(), with an
FDT fragment generated, to make the latest upstream U-Boot happy.

Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1595227748-24720-1-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 months agotarget/riscv: check before allocating TCG temps
LIU Zhiwei [Fri, 24 Jul 2020 00:28:07 +0000 (17:28 -0700)] 
target/riscv: check before allocating TCG temps

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200626205917.4545-5-zhiwei_liu@c-sky.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200724002807.441147-8-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 months agotarget/riscv: Clean up fmv.w.x
LIU Zhiwei [Fri, 24 Jul 2020 00:28:06 +0000 (17:28 -0700)] 
target/riscv: Clean up fmv.w.x

Use tcg_gen_extu_tl_i64 to avoid the ifdef.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200626205917.4545-7-zhiwei_liu@c-sky.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200724002807.441147-7-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 months agotarget/riscv: Check nanboxed inputs in trans_rvf.inc.c
Richard Henderson [Fri, 24 Jul 2020 00:28:05 +0000 (17:28 -0700)] 
target/riscv: Check nanboxed inputs in trans_rvf.inc.c

If a 32-bit input is not properly nanboxed, then the input is replaced
with the default qnan.  The only inline expansion is for the sign-changing
set of instructions: FSGNJ.S, FSGNJX.S, FSGNJN.S.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Message-Id: <20200724002807.441147-6-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 months agotarget/riscv: Check nanboxed inputs to fp helpers
Richard Henderson [Fri, 24 Jul 2020 00:28:04 +0000 (17:28 -0700)] 
target/riscv: Check nanboxed inputs to fp helpers

If a 32-bit input is not properly nanboxed, then the input is
replaced with the default qnan.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Message-Id: <20200724002807.441147-5-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 months agotarget/riscv: Generate nanboxed results from trans_rvf.inc.c
Richard Henderson [Fri, 24 Jul 2020 00:28:03 +0000 (17:28 -0700)] 
target/riscv: Generate nanboxed results from trans_rvf.inc.c

Make sure that all results from inline single-precision scalar
operations are properly nan-boxed to 64-bits.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Message-Id: <20200724002807.441147-4-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 months agotarget/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s
Richard Henderson [Fri, 24 Jul 2020 00:28:02 +0000 (17:28 -0700)] 
target/riscv: Generalize gen_nanbox_fpr to gen_nanbox_s

Do not depend on the RVD extension, take input and output via
TCGv_i64 instead of fpu regno.  Move the function to translate.c
so that it can be used in multiple trans_*.inc.c files.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Message-Id: <20200724002807.441147-3-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 months agotarget/riscv: Generate nanboxed results from fp helpers
Richard Henderson [Fri, 24 Jul 2020 00:28:01 +0000 (17:28 -0700)] 
target/riscv: Generate nanboxed results from fp helpers

Make sure that all results from single-precision scalar helpers
are properly nan-boxed to 64-bits.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Message-Id: <20200724002807.441147-2-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
6 months agoMerge remote-tracking branch 'remotes/kraxel/tags/seabios-20200819-pull-request'...
Peter Maydell [Fri, 21 Aug 2020 21:45:15 +0000 (22:45 +0100)] 
Merge remote-tracking branch 'remotes/kraxel/tags/seabios-20200819-pull-request' into staging

seabios: update to 1.14-final

# gpg: Signature made Wed 19 Aug 2020 07:36:36 BST
# gpg:                using RSA key 4CB6D8EED3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full]
# gpg:                 aka "Gerd Hoffmann <gerd@kraxel.org>" [full]
# gpg:                 aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full]
# Primary key fingerprint: A032 8CFF B93A 17A7 9901  FE7D 4CB6 D8EE D3E8 7138

* remotes/kraxel/tags/seabios-20200819-pull-request:
  seabios: update to 1.14-final

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agokeymaps: update
Paolo Bonzini [Fri, 21 Aug 2020 16:09:29 +0000 (12:09 -0400)] 
keymaps: update

Looks like update-keymaps has not been run in a while.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
6 months agomeson: Fix --disable-tools --enable-system builds
Philippe Mathieu-Daudé [Fri, 21 Aug 2020 15:05:56 +0000 (17:05 +0200)] 
meson: Fix --disable-tools --enable-system builds

Fixes:

 $ ../configure --disable-tools --disable-user
 ../tests/qemu-iotests/meson.build:7:0: ERROR: Unknown variable "qemu_block_tools".

Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Message-Id: <20200821150556.1235625-1-philmd@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
6 months agomeson: convert pc-bios/keymaps/Makefile
Marc-André Lureau [Thu, 19 Sep 2019 16:24:43 +0000 (20:24 +0400)] 
meson: convert pc-bios/keymaps/Makefile

Note that sl and sv keymaps were not created by qemu-keymap.

Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
6 months agoconfigure: silence 'shift' error message in version_ge()
Stefano Garzarella [Fri, 21 Aug 2020 20:35:58 +0000 (22:35 +0200)] 
configure: silence 'shift' error message in version_ge()

If there are less than 2 arguments in version_ge(), the second
'shift' prints this error:
    ../configure: line 232: shift: shift count out of range

As Eric suggested, we can use 'shift ${2:+2}' which works out to
'shift 2' if $2 is set, or 'shift' (implicitly shift 1) if $2
is not set.

This patch replaces both 'shift; shift' occurrences in version_ge()
with 'shift ${2:+2}'.

Suggested-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Stefano Garzarella <sgarzare@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-Id: <20200821203558.10338-1-sgarzare@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
6 months agoMerge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging
Peter Maydell [Fri, 21 Aug 2020 16:26:52 +0000 (17:26 +0100)] 
Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging

Pull request

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* remotes/stefanha/tags/block-pull-request:
  aio-posix: keep aio_notify_me disabled during polling
  async: always set ctx->notified in aio_notify()
  async: rename event_notifier_dummy_cb/poll()

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agoutil/meson.build: fix fdmon-io_uring build
Stefano Garzarella [Fri, 21 Aug 2020 15:48:53 +0000 (17:48 +0200)] 
util/meson.build: fix fdmon-io_uring build

libqemuutil.a build fails with this error:

  /usr/bin/ld: libqemuutil.a(util_fdmon-io_uring.c.o): in function `get_sqe':
  qemu/build/../util/fdmon-io_uring.c:83: undefined reference to `io_uring_get_sqe'
  /usr/bin/ld: qemu/build/../util/fdmon-io_uring.c:92: undefined reference to `io_uring_submit'
  /usr/bin/ld: qemu/build/../util/fdmon-io_uring.c:96: undefined reference to `io_uring_get_sqe'
  /usr/bin/ld: libqemuutil.a(util_fdmon-io_uring.c.o): in function `fdmon_io_uring_wait':
  qemu/build/../util/fdmon-io_uring.c:289: undefined reference to `io_uring_submit_and_wait'
  /usr/bin/ld: libqemuutil.a(util_fdmon-io_uring.c.o): in function `fdmon_io_uring_setup':
  qemu/build/../util/fdmon-io_uring.c:328: undefined reference to `io_uring_queue_init'
  /usr/bin/ld: libqemuutil.a(util_fdmon-io_uring.c.o): in function `fdmon_io_uring_destroy':
  qemu/build/../util/fdmon-io_uring.c:343: undefined reference to `io_uring_queue_exit'
  collect2: error: ld returned 1 exit status

This patch fix the issue adding 'linux_io_uring' dependency for
fdmon-io_uring.c

Fixes: a81df1b68b ("libqemuutil, qapi, trace: convert to meson")
Cc: pbonzini@redhat.com
Signed-off-by: Stefano Garzarella <sgarzare@redhat.com>
Message-Id: <20200821154853.94379-1-sgarzare@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>