qemu.git
2 years agodocs/system: convert Texinfo documentation to rST
Paolo Bonzini [Fri, 28 Feb 2020 15:36:05 +0000 (15:36 +0000)] 
docs/system: convert Texinfo documentation to rST

Apart from targets.rst, which was written by hand, this is an automated
conversion obtained with the following command:

  makeinfo --force -o - --docbook \
    -D 'qemu_system_x86 QEMU_SYSTEM_X86_MACRO' \
    -D 'qemu_system     QEMU_SYSTEM_MACRO' \
    $texi | pandoc -f docbook -t rst+smart | perl -e '
      $/=undef;
      $_ = <>;
      s/^-  − /-  /gm;
      s/QEMU_SYSTEM_MACRO/|qemu_system|/g;
      s/QEMU_SYSTEM_X86_MACRO/|qemu_system_x86|/g;
      s/(?=::\n\n +\|qemu)/.. parsed-literal/g;
      s/:\n\n::$/::/gm;
      print' > $rst

In addition, the following changes were made manually:

- target-i386.rst and target-mips.rst: replace CPU model documentation with
  an include directive

- monitor.rst: replace the command section with a comment

- images.rst: add toctree

- target-arm.rst: Replace use of :math: (which Sphinx complains
  about) with :sup:, and hide it behind |I2C| and |I2C| substitutions.

Content that is not @included remains exclusive to qemu-doc.texi.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200228153619.9906-20-peter.maydell@linaro.org
Message-id: 20200226113034.6741-19-pbonzini@redhat.com
[PMM: Fixed target-arm.rst use of :math:; remove out of date
 note about images.rst from commit message; fixed expansion
 of |qemu_system_x86|; use parsed-literal in invocation.rst
 when we want to use |qemu_system_x86|; fix incorrect subsection
 level for "OS requirements" in target-i386.rst; fix incorrect
 syntax for making links to other sections of the manual]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agodocs/system: convert the documentation of deprecated features to rST.
Peter Maydell [Fri, 28 Feb 2020 15:36:04 +0000 (15:36 +0000)] 
docs/system: convert the documentation of deprecated features to rST.

We put the whole of this document into the system manual, though
technically a few parts of it apply to qemu-img or qemu-nbd which are
otherwise documented in tools/.

We only make formatting fixes, except for one use of 'appendix' which
we change to 'section' because this isn't an appendix in the Sphinx
manual.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20200228153619.9906-19-peter.maydell@linaro.org
Message-id: 20200226113034.6741-18-pbonzini@redhat.com

2 years agodocs/system: convert managed startup to rST.
Peter Maydell [Fri, 28 Feb 2020 15:36:03 +0000 (15:36 +0000)] 
docs/system: convert managed startup to rST.

Fix one typo in the process and format more option and
command names as literal text, but make no significant
changes to the content.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20200228153619.9906-18-peter.maydell@linaro.org
Message-id: 20200226113034.6741-17-pbonzini@redhat.com

2 years agodocs/system: Convert security.texi to rST format
Peter Maydell [Fri, 28 Feb 2020 15:36:02 +0000 (15:36 +0000)] 
docs/system: Convert security.texi to rST format

security.texi is included from qemu-doc.texi but is not used
in the qemu.1 manpage. So we can do a straightforward conversion
of the contents, which go into the system manual.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20200228153619.9906-17-peter.maydell@linaro.org
Message-id: 20200226113034.6741-16-pbonzini@redhat.com

2 years agodocs/system: Convert qemu-cpu-models.texi to rST
Kashyap Chamarthy [Fri, 28 Feb 2020 15:36:01 +0000 (15:36 +0000)] 
docs/system: Convert qemu-cpu-models.texi to rST

This doc was originally written by Daniel P. Berrangé
<berrange@redhat.com>, introduced via commit[1]: 2544e9e4aa (docs: add
guidance on configuring CPU models for x86, 2018-06-27).

In this patch:

  - 1-1 conversion of Texinfo to rST, besides a couple of minor
    tweaks that are too trivial to mention.   (Thanks to Stephen
    Finucane on IRC for the suggestion to use rST "definition lists"
    instead of bullets in some places.)

    Further modifications will be done via a separate patch.

  - rST and related infra changes: manual page generation, Makefile
    fixes, clean up references to qemu-cpu-models.texi, update year in
    the copyright notice, etc.

[1] https://git.qemu.org/?p=qemu.git;a=commit;h=2544e9e4aa

As part of the conversion, we use a more generic 'author' attribution
for the manpage than we previously had, as agreed with the original
author Dan Berrange.

Signed-off-by: Kashyap Chamarthy <kchamart@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200228153619.9906-16-peter.maydell@linaro.org
Message-id: 20200226113034.6741-15-pbonzini@redhat.com
[Move macros to defs.rst.inc, split in x86 and MIPS parts,
 make qemu-cpu-models.rst a standalone document. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
[PMM: Move defs.rst.inc setup to its own commit;
 fix minor issues with MAINTAINERS file updates;
 drop copyright date change; keep capitalization of
 "QEMU Project developers" consistent with other uses;
 minor Makefile fixups]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agodocs: Create defs.rst.inc as a place to define substitutions
Peter Maydell [Fri, 28 Feb 2020 15:36:00 +0000 (15:36 +0000)] 
docs: Create defs.rst.inc as a place to define substitutions

Rather than accumulating generally useful rST substitution
definitions in individual rST files, create a defs.rst.inc where we
can define these.  To start with it has the |qemu_system| definition
from qemu-block-drivers.rst.

Add a comment noting a pitfall where putting literal markup in the
definition of |qemu_system| makes it misrender manpage output; this
means the point-of-use must handle the literal markup (which is
almost always done by having it inside a parsed-literal block).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Kashyap Chamarthy <kchamart@redhat.com>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20200228153619.9906-15-peter.maydell@linaro.org

2 years agodocs/system: put qemu-block-drivers body in an included file
Paolo Bonzini [Fri, 28 Feb 2020 15:35:59 +0000 (15:35 +0000)] 
docs/system: put qemu-block-drivers body in an included file

This removes the "only" directives, and lets us use the conventional
"DESCRIPTION" section in the manpage.

This temporarily drops the qemu-block-drivers documentation
from the system manual, but it will be put back (in the
right place in the toctree) in a later commit.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200228153619.9906-14-peter.maydell@linaro.org
Message-id: 20200226113034.6741-14-pbonzini@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: Added commit message note about temporarily losing
qemu-block-drivers from the system manual]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoqemu-doc: remove indices other than findex
Paolo Bonzini [Fri, 28 Feb 2020 15:35:58 +0000 (15:35 +0000)] 
qemu-doc: remove indices other than findex

These indices are not well-maintained, and pandoc also chokes on the
directives.  Just nuke them.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200228153619.9906-13-peter.maydell@linaro.org
Message-id: 20200226113034.6741-13-pbonzini@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoqemu-doc: move included files to docs/system
Paolo Bonzini [Fri, 28 Feb 2020 15:35:57 +0000 (15:35 +0000)] 
qemu-doc: move included files to docs/system

Since qemu-doc.texi is mostly including files from docs/system,
move the existing include files there for consistency.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200228153619.9906-12-peter.maydell@linaro.org
Message-id: 20200226113034.6741-12-pbonzini@redhat.com
[PMM: update MAINTAINERS line for qemu-option-trace.texi]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoqemu-doc: move qemu-tech.texi into main section
Paolo Bonzini [Fri, 28 Feb 2020 15:35:56 +0000 (15:35 +0000)] 
qemu-doc: move qemu-tech.texi into main section

The only remaining content in qemu-tech.texi is a few paragraphs
about managed start up options.  Move them in the main section
about full system emulation.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200228153619.9906-11-peter.maydell@linaro.org
Message-id: 20200226113034.6741-11-pbonzini@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoqemu-doc: Remove the "CPU emulation" part of the "Implementation notes"
Peter Maydell [Fri, 28 Feb 2020 15:35:55 +0000 (15:35 +0000)] 
qemu-doc: Remove the "CPU emulation" part of the "Implementation notes"

The "CPU emulation" part of the "Implementation notes" in
qemu-tech.texi looks like it is documenting what features of various
CPUs we do or don't emulate.  However:
 * it covers only six of our 21 guest architectures
 * the last time anybody updated it for actual content was in
   2011/2012 for Xtensa; the content for the other five
   architectures is even older, being from 2008 or before!

What we have is out of date, misleading and incomplete.
Just delete this part of the document rather than trying to
convert it to rST.

(It would be nice eventually to have documentation of the
scope and limitations of our emulation; but we will want to
separate out the generic "system emulation" information from
the parts that are specific to linux-user anyway, as they will
be in different manuals.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Message-id: 20200228153619.9906-10-peter.maydell@linaro.org
Message-id: 20200226113034.6741-10-pbonzini@redhat.com
Message-Id: <20200225154121.21116-3-peter.maydell@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2 years agoqemu-doc: split target sections to separate files
Paolo Bonzini [Fri, 28 Feb 2020 15:35:54 +0000 (15:35 +0000)] 
qemu-doc: split target sections to separate files

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200228153619.9906-9-peter.maydell@linaro.org
Message-id: 20200226113034.6741-9-pbonzini@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoqemu-doc: move system requirements chapter inside PC section
Paolo Bonzini [Fri, 28 Feb 2020 15:35:53 +0000 (15:35 +0000)] 
qemu-doc: move system requirements chapter inside PC section

The system requirements documented in this chapter are limited to x86 KVM targets.
Clean them up and move them to the target section.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200228153619.9906-8-peter.maydell@linaro.org
Message-id: 20200226113034.6741-8-pbonzini@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoqemu-doc: extract common system emulator documentation from the PC section
Paolo Bonzini [Fri, 28 Feb 2020 15:35:52 +0000 (15:35 +0000)] 
qemu-doc: extract common system emulator documentation from the PC section

Move the section on PC peripherals together with other targets.
While some x86-specific information remains in the main system
emulation chapter, it can be tackled more easily a section at a
time.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200228153619.9906-7-peter.maydell@linaro.org
Message-id: 20200226113034.6741-7-pbonzini@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoqemu-doc: split qemu-doc.texi in multiple files
Paolo Bonzini [Fri, 28 Feb 2020 15:35:51 +0000 (15:35 +0000)] 
qemu-doc: split qemu-doc.texi in multiple files

In order to facilitate the reorganization of qemu-doc.texi content,
as well as the conversion to rST/Sphinx, split it in multiple .texi
files that are included from docs/system.

The "other devices" section is renamed to ivshmem and placed last.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200228153619.9906-6-peter.maydell@linaro.org
Message-id: 20200226113034.6741-6-pbonzini@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoqemu-doc: split CPU models doc between MIPS and x86 parts
Paolo Bonzini [Fri, 28 Feb 2020 15:35:50 +0000 (15:35 +0000)] 
qemu-doc: split CPU models doc between MIPS and x86 parts

The MIPS CPU models end up in the middle of the PC documentation.  Move
them to a separate file so that they can be placed in the right section.

The man page still includes both x86 and MIPS content.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200228153619.9906-5-peter.maydell@linaro.org
Message-id: 20200226113034.6741-5-pbonzini@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agotexi2pod: parse @include directives outside "@c man" blocks
Paolo Bonzini [Fri, 28 Feb 2020 15:35:49 +0000 (15:35 +0000)] 
texi2pod: parse @include directives outside "@c man" blocks

This enables splitting the huge qemu-doc.texi file and keeping parallel
Texinfo and rST versions of the documentation.  texi2pod is not going to
live much longer and hardly anyone cares about its upstream status,
so the temporary fork should be acceptable.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200228153619.9906-4-peter.maydell@linaro.org
Message-id: 20200226113034.6741-4-pbonzini@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoqemu-doc: remove target OS documentation
Paolo Bonzini [Fri, 28 Feb 2020 15:35:48 +0000 (15:35 +0000)] 
qemu-doc: remove target OS documentation

This section covers OSes up to Windows 2000, and as such it is mostly
obsolete.  Zap it.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200228153619.9906-3-peter.maydell@linaro.org
Message-id: 20200226113034.6741-3-pbonzini@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoqemu-doc: convert user-mode emulation to a separate Sphinx manual
Paolo Bonzini [Fri, 28 Feb 2020 15:35:47 +0000 (15:35 +0000)] 
qemu-doc: convert user-mode emulation to a separate Sphinx manual

The final addition to the set of QEMU manuals is the user-mode emulation
manual, which right now is included in qemu-doc.texi.  Extract it and
convert it to rST, so that qemu-doc.texi covers only full system emulation.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200228153619.9906-2-peter.maydell@linaro.org
Message-id: 20200226113034.6741-2-pbonzini@redhat.com
[PMM: Fix makefile conflicts; add user manual to
 index.rst and index.html.in; don't specify empty man_pages
 list; fixed a few comments to say 'user' rather than 'system']
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoMerge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf4' into...
Peter Maydell [Thu, 5 Mar 2020 20:53:53 +0000 (20:53 +0000)] 
Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf4' into staging

A single RISC-V fixup

This is just a single patch, which fixes a bug found by Coverity.

# gpg: Signature made Thu 05 Mar 2020 20:05:03 GMT
# gpg:                using RSA key 2B3C3747446843B24A943A7A2E1319F35FBB1889
# gpg:                issuer "palmer@dabbelt.com"
# gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown]
# gpg:                 aka "Palmer Dabbelt <palmer@sifive.com>" [unknown]
# gpg:                 aka "Palmer Dabbelt <palmerdabbelt@google.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88  6DF8 EF4C A150 2CCB AB41
#      Subkey fingerprint: 2B3C 3747 4468 43B2 4A94  3A7A 2E13 19F3 5FBB 1889

* remotes/palmer/tags/riscv-for-master-5.0-sf4:
  RISC-V: Add a missing "," in riscv_excp_names

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoRISC-V: Add a missing "," in riscv_excp_names
Palmer Dabbelt [Thu, 5 Mar 2020 16:46:20 +0000 (08:46 -0800)] 
RISC-V: Add a missing "," in riscv_excp_names

This would almost certainly cause the exception names to be reported
incorrectly.  Coverity found the issue (CID 1420223).  As per Peter's
suggestion, I've also added a comma at the end of the list to avoid the issue
reappearing in the future.

Fixes: ab67a1d07a ("target/riscv: Add support for the new execption numbers")
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
2 years agoMerge remote-tracking branch 'remotes/stefanberger/tags/pull-tpm-2020-03-04-2' into...
Peter Maydell [Thu, 5 Mar 2020 19:39:47 +0000 (19:39 +0000)] 
Merge remote-tracking branch 'remotes/stefanberger/tags/pull-tpm-2020-03-04-2' into staging

Merge tpm 2020/03/04 v2

# gpg: Signature made Thu 05 Mar 2020 17:21:05 GMT
# gpg:                using RSA key B818B9CADF9089C2D5CEC66B75AD65802A0B4211
# gpg: Good signature from "Stefan Berger <stefanb@linux.vnet.ibm.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: B818 B9CA DF90 89C2 D5CE  C66B 75AD 6580 2A0B 4211

* remotes/stefanberger/tags/pull-tpm-2020-03-04-2:
  test: tpm-tis: Add Sysbus TPM-TIS device test
  test: tpm-tis: Get prepared to share tests between ISA and sysbus devices
  test: tpm: pass optional machine options to swtpm test functions
  docs/specs/tpm: Document TPM_TIS sysbus device for ARM
  hw/arm/virt: vTPM support
  tpm: Add the SysBus TPM TIS device
  tpm: Separate TPM_TIS and TPM_TIS_ISA configs
  tpm: Separate tpm_tis common functions from isa code
  tpm: Use TPMState as a common struct
  tpm: rename TPM_TIS into TPM_TIS_ISA

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agotest: tpm-tis: Add Sysbus TPM-TIS device test
Eric Auger [Thu, 5 Mar 2020 16:51:49 +0000 (17:51 +0100)] 
test: tpm-tis: Add Sysbus TPM-TIS device test

The tests themselves are the same as the ISA device ones.
Only the main() changes as the "tpm-tis-device" device gets
instantiated. Also the base address of the device is not
0xFED40000 anymore but matches the base address of the
ARM virt platform bus.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>
Message-id: 20200305165149.618-11-eric.auger@redhat.com
Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
2 years agotest: tpm-tis: Get prepared to share tests between ISA and sysbus devices
Eric Auger [Thu, 5 Mar 2020 16:51:48 +0000 (17:51 +0100)] 
test: tpm-tis: Get prepared to share tests between ISA and sysbus devices

ISA and sysbus TPM-TIS devices will share their tests. Only
the main() will change (instantiation option is different).
Also the base address of the TPM-TIS device is going to be
different. on x86 it is located at 0xFED40000 while on ARM
it can be located at any location, discovered through the
device tree description.

So we put shared test functions in a new object module.
Each test needs to set tpm_tis_base_addr global variable.

Also take benefit of this move to fix "block comments using
a leading */ on a separate line" checkpatch warnings.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>
Message-id: 20200305165149.618-10-eric.auger@redhat.com
Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
2 years agotest: tpm: pass optional machine options to swtpm test functions
Eric Auger [Thu, 5 Mar 2020 16:51:47 +0000 (17:51 +0100)] 
test: tpm: pass optional machine options to swtpm test functions

We plan to use swtpm test functions on ARM for testing the
sysbus TPM-TIS device. However on ARM there is no default machine
type. So we need to explictly pass some machine options on startup.
Let's allow this by adding a new parameter to both swtpm test
functions and update all call sites.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>
Message-id: 20200305165149.618-9-eric.auger@redhat.com
Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
2 years agodocs/specs/tpm: Document TPM_TIS sysbus device for ARM
Eric Auger [Thu, 5 Mar 2020 16:51:46 +0000 (17:51 +0100)] 
docs/specs/tpm: Document TPM_TIS sysbus device for ARM

Update the documentation with recent changes related to the
sysbus TPM_TIS device addition and add the command line
to be used with arm VIRT.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>
Message-id: 20200305165149.618-8-eric.auger@redhat.com
Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
2 years agohw/arm/virt: vTPM support
Eric Auger [Thu, 5 Mar 2020 16:51:45 +0000 (17:51 +0100)] 
hw/arm/virt: vTPM support

Let the TPM TIS SYSBUS device be dynamically instantiable
in ARM virt.  A device tree node is dynamically created
(TPM via MMIO).

The TPM Physical Presence interface (PPI) is not supported.

To run with the swtmp TPM emulator, the qemu command line must
be augmented with:

        -chardev socket,id=chrtpm,path=swtpm-sock \
        -tpmdev emulator,id=tpm0,chardev=chrtpm \
        -device tpm-tis-device,tpmdev=tpm0 \

swtpm/libtpms command line example:

swtpm socket --tpm2 -t -d --tpmstate dir=/tmp/tpm \
--ctrl type=unixio,path=swtpm-sock

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Message-id: 20200305165149.618-7-eric.auger@redhat.com
Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
2 years agotpm: Add the SysBus TPM TIS device
Eric Auger [Thu, 5 Mar 2020 16:51:44 +0000 (17:51 +0100)] 
tpm: Add the SysBus TPM TIS device

Introduce the tpm-tis-device which is a sysbus device
and is bound to be used on ARM.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Message-id: 20200305165149.618-6-eric.auger@redhat.com
Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
2 years agotpm: Separate TPM_TIS and TPM_TIS_ISA configs
Eric Auger [Thu, 5 Mar 2020 16:51:43 +0000 (17:51 +0100)] 
tpm: Separate TPM_TIS and TPM_TIS_ISA configs

Let's separate the compilation of tpm_tis_common.c from
the compilation of tpm_tis_isa.c

The common part will be also compiled along with the
tpm_tis_sysbus device.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Message-id: 20200305165149.618-5-eric.auger@redhat.com
Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
2 years agotpm: Separate tpm_tis common functions from isa code
Eric Auger [Thu, 5 Mar 2020 16:51:42 +0000 (17:51 +0100)] 
tpm: Separate tpm_tis common functions from isa code

Move the device agnostic code into tpm_tis_common.c and
put the ISA device specific code into tpm_tis_isa.c

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Message-id: 20200305165149.618-4-eric.auger@redhat.com
Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
2 years agotpm: Use TPMState as a common struct
Eric Auger [Thu, 5 Mar 2020 16:51:41 +0000 (17:51 +0100)] 
tpm: Use TPMState as a common struct

As we plan to introduce a SysBus TPM TIS device, let's
make the TPMState a common struct usable by both the
ISADevice and the SysBusDevice. TPMStateISA embeds the
struct and inherits from the ISADevice.

The prototype of functions bound to be used by both
the ISA and SysBus devices is changed to take TPMState
handle.

A bunch of structs also are renamed to be specialized
for the ISA device. Besides those transformations, no
functional change is expected.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Message-id: 20200305165149.618-3-eric.auger@redhat.com
Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
2 years agotpm: rename TPM_TIS into TPM_TIS_ISA
Eric Auger [Thu, 5 Mar 2020 16:51:40 +0000 (17:51 +0100)] 
tpm: rename TPM_TIS into TPM_TIS_ISA

As we plan to introduce a sysbus TPM_TIS, let's rename
TPM_TIS into TPM_TIS_ISA.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Message-id: 20200305165149.618-2-eric.auger@redhat.com
Signed-off-by: Stefan Berger <stefanb@linux.ibm.com>
2 years agoMerge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200305' into...
Peter Maydell [Thu, 5 Mar 2020 16:47:37 +0000 (16:47 +0000)] 
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20200305' into staging

 * versal: Implement ADMA
 * Implement (trivially) ARMv8.2-TTCNP
 * hw/arm/smmu-common: a fix to smmu_find_smmu_pcibus
 * Remove unnecessary endianness-handling on some boards
 * Avoid minor memory leaks from timer_new in some devices
 * Honour more of the HCR_EL2 trap bits
 * Complain rather than ignoring bad command line options for cubieboard
 * Honour TBI for DC ZVA and exception return

# gpg: Signature made Thu 05 Mar 2020 16:30:17 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20200305: (37 commits)
  target/arm: Clean address for DC ZVA
  target/arm: Use DEF_HELPER_FLAGS for helper_dc_zva
  target/arm: Move helper_dc_zva to helper-a64.c
  target/arm: Apply TBI to ESR_ELx in helper_exception_return
  target/arm: Introduce core_to_aa64_mmu_idx
  target/arm: Optimize cpu_mmu_index
  target/arm: Replicate TBI/TBID bits for single range regimes
  hw/arm/cubieboard: report error when using unsupported -bios argument
  hw/arm/cubieboard: restrict allowed RAM size to 512MiB and 1GiB
  hw/arm/cubieboard: restrict allowed CPU type to ARM Cortex-A8
  hw/arm/cubieboard: use ARM Cortex-A8 as the default CPU in machine definition
  tests/tcg/aarch64: Add newline in pauth-1 printf
  target/arm: Honor the HCR_EL2.TTLB bit
  target/arm: Honor the HCR_EL2.TPU bit
  target/arm: Honor the HCR_EL2.TPCP bit
  target/arm: Honor the HCR_EL2.TACR bit
  target/arm: Honor the HCR_EL2.TSW bit
  target/arm: Honor the HCR_EL2.{TVM,TRVM} bits
  target/arm: Improve masking in arm_hcr_el2_eff
  target/arm: Remove EL2 and EL3 setup from user-only
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agotarget/arm: Clean address for DC ZVA
Richard Henderson [Thu, 5 Mar 2020 16:09:21 +0000 (16:09 +0000)] 
target/arm: Clean address for DC ZVA

This data access was forgotten when we added support for cleaning
addresses of TBI information.

Fixes: 3a471103ac1823ba
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200302175829.2183-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agotarget/arm: Use DEF_HELPER_FLAGS for helper_dc_zva
Richard Henderson [Thu, 5 Mar 2020 16:09:21 +0000 (16:09 +0000)] 
target/arm: Use DEF_HELPER_FLAGS for helper_dc_zva

The function does not write registers, and only reads them by
implication via the exception path.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200302175829.2183-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agotarget/arm: Move helper_dc_zva to helper-a64.c
Richard Henderson [Thu, 5 Mar 2020 16:09:20 +0000 (16:09 +0000)] 
target/arm: Move helper_dc_zva to helper-a64.c

This is an aarch64-only function.  Move it out of the shared file.
This patch is code movement only.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200302175829.2183-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agotarget/arm: Apply TBI to ESR_ELx in helper_exception_return
Richard Henderson [Thu, 5 Mar 2020 16:09:20 +0000 (16:09 +0000)] 
target/arm: Apply TBI to ESR_ELx in helper_exception_return

We missed this case within AArch64.ExceptionReturn.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200302175829.2183-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agotarget/arm: Introduce core_to_aa64_mmu_idx
Richard Henderson [Thu, 5 Mar 2020 16:09:20 +0000 (16:09 +0000)] 
target/arm: Introduce core_to_aa64_mmu_idx

If by context we know that we're in AArch64 mode, we need not
test for M-profile when reconstructing the full ARMMMUIdx.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200302175829.2183-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agotarget/arm: Optimize cpu_mmu_index
Richard Henderson [Thu, 5 Mar 2020 16:09:20 +0000 (16:09 +0000)] 
target/arm: Optimize cpu_mmu_index

We now cache the core mmu_idx in env->hflags.  Rather than recompute
from scratch, extract the field.  All of the uses of cpu_mmu_index
within target/arm are within helpers, and env->hflags is always stable
within a translation block from whence helpers are called.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200302175829.2183-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agotarget/arm: Replicate TBI/TBID bits for single range regimes
Richard Henderson [Thu, 5 Mar 2020 16:09:20 +0000 (16:09 +0000)] 
target/arm: Replicate TBI/TBID bits for single range regimes

Replicate the single TBI bit from TCR_EL2 and TCR_EL3 so that
we can unconditionally use pointer bit 55 to index into our
composite TBI1:TBI0 field.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20200302175829.2183-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/arm/cubieboard: report error when using unsupported -bios argument
Niek Linnenbank [Thu, 5 Mar 2020 16:09:19 +0000 (16:09 +0000)] 
hw/arm/cubieboard: report error when using unsupported -bios argument

The Cubieboard machine does not support the -bios argument.
Report an error when -bios is used and exit immediately.

Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Message-id: 20200227220149.6845-5-nieklinnenbank@gmail.com
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/arm/cubieboard: restrict allowed RAM size to 512MiB and 1GiB
Niek Linnenbank [Thu, 5 Mar 2020 16:09:19 +0000 (16:09 +0000)] 
hw/arm/cubieboard: restrict allowed RAM size to 512MiB and 1GiB

The Cubieboard contains either 512MiB or 1GiB of onboard RAM [1].
Prevent changing RAM to a different size which could break user programs.

 [1] http://linux-sunxi.org/Cubieboard

Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Message-id: 20200227220149.6845-4-nieklinnenbank@gmail.com
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/arm/cubieboard: restrict allowed CPU type to ARM Cortex-A8
Niek Linnenbank [Thu, 5 Mar 2020 16:09:19 +0000 (16:09 +0000)] 
hw/arm/cubieboard: restrict allowed CPU type to ARM Cortex-A8

The Cubieboard has an ARM Cortex-A8.  Instead of simply ignoring a
bogus -cpu option provided by the user, give them an error message so
they know their command line is wrong.

Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Message-id: 20200227220149.6845-3-nieklinnenbank@gmail.com
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[PMM: tweaked commit message]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/arm/cubieboard: use ARM Cortex-A8 as the default CPU in machine definition
Niek Linnenbank [Thu, 5 Mar 2020 16:09:19 +0000 (16:09 +0000)] 
hw/arm/cubieboard: use ARM Cortex-A8 as the default CPU in machine definition

The Cubieboard is a singleboard computer with an Allwinner A10 System-on-Chip [1].
As documented in the Allwinner A10 User Manual V1.5 [2], the SoC has an ARM
Cortex-A8 processor. Currently the Cubieboard machine definition specifies the
ARM Cortex-A9 in its description and as the default CPU.

This patch corrects the Cubieboard machine definition to use the ARM Cortex-A8.

The only user-visible effect is that our textual description of the
machine was wrong, because hw/arm/allwinner-a10.c always creates a
Cortex-A8 CPU regardless of the default value in the MachineClass struct.

 [1] http://docs.cubieboard.org/products/start#cubieboard1
 [2] https://linux-sunxi.org/File:Allwinner_A10_User_manual_V1.5.pdf

Fixes: 8a863c8120994981a099
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
Message-id: 20200227220149.6845-2-nieklinnenbank@gmail.com
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
[note in commit message that the bug didn't have much visible effect]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agotests/tcg/aarch64: Add newline in pauth-1 printf
Richard Henderson [Thu, 5 Mar 2020 16:09:19 +0000 (16:09 +0000)] 
tests/tcg/aarch64: Add newline in pauth-1 printf

Make the output just a bit prettier when running by hand.

Cc: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200229012811.24129-13-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agotarget/arm: Honor the HCR_EL2.TTLB bit
Richard Henderson [Thu, 5 Mar 2020 16:09:18 +0000 (16:09 +0000)] 
target/arm: Honor the HCR_EL2.TTLB bit

This bit traps EL1 access to tlb maintenance insns.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200229012811.24129-12-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agotarget/arm: Honor the HCR_EL2.TPU bit
Richard Henderson [Thu, 5 Mar 2020 16:09:18 +0000 (16:09 +0000)] 
target/arm: Honor the HCR_EL2.TPU bit

This bit traps EL1 access to cache maintenance insns that operate
to the point of unification.  There are no longer any references to
plain aa64_cacheop_access, so remove it.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200229012811.24129-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agotarget/arm: Honor the HCR_EL2.TPCP bit
Richard Henderson [Thu, 5 Mar 2020 16:09:18 +0000 (16:09 +0000)] 
target/arm: Honor the HCR_EL2.TPCP bit

This bit traps EL1 access to cache maintenance insns that operate
to the point of coherency or persistence.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200229012811.24129-10-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agotarget/arm: Honor the HCR_EL2.TACR bit
Richard Henderson [Thu, 5 Mar 2020 16:09:18 +0000 (16:09 +0000)] 
target/arm: Honor the HCR_EL2.TACR bit

This bit traps EL1 access to the auxiliary control registers.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200229012811.24129-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agotarget/arm: Honor the HCR_EL2.TSW bit
Richard Henderson [Thu, 5 Mar 2020 16:09:18 +0000 (16:09 +0000)] 
target/arm: Honor the HCR_EL2.TSW bit

These bits trap EL1 access to set/way cache maintenance insns.

Buglink: https://bugs.launchpad.net/bugs/1863685
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200229012811.24129-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agotarget/arm: Honor the HCR_EL2.{TVM,TRVM} bits
Richard Henderson [Thu, 5 Mar 2020 16:09:17 +0000 (16:09 +0000)] 
target/arm: Honor the HCR_EL2.{TVM,TRVM} bits

These bits trap EL1 access to various virtual memory controls.

Buglink: https://bugs.launchpad.net/bugs/1855072
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200229012811.24129-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agotarget/arm: Improve masking in arm_hcr_el2_eff
Richard Henderson [Thu, 5 Mar 2020 16:09:17 +0000 (16:09 +0000)] 
target/arm: Improve masking in arm_hcr_el2_eff

Update the {TGE,E2H} == '11' masking to ARMv8.6.
If EL2 is configured for aarch32, disable all of
the bits that are RES0 in aarch32 mode.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200229012811.24129-6-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agotarget/arm: Remove EL2 and EL3 setup from user-only
Richard Henderson [Thu, 5 Mar 2020 16:09:17 +0000 (16:09 +0000)] 
target/arm: Remove EL2 and EL3 setup from user-only

We have disabled EL2 and EL3 for user-only, which means that these
registers "don't exist" and should not be set.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200229012811.24129-5-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agotarget/arm: Disable has_el2 and has_el3 for user-only
Richard Henderson [Thu, 5 Mar 2020 16:09:17 +0000 (16:09 +0000)] 
target/arm: Disable has_el2 and has_el3 for user-only

In arm_cpu_reset, we configure many system registers so that user-only
behaves as it should with a minimum of ifdefs.  However, we do not set
all of the system registers as required for a cpu with EL2 and EL3.

Disabling EL2 and EL3 mean that we will not look at those registers,
which means that we don't have to worry about configuring them.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200229012811.24129-4-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agotarget/arm: Add HCR_EL2 bit definitions from ARMv8.6
Richard Henderson [Thu, 5 Mar 2020 16:09:16 +0000 (16:09 +0000)] 
target/arm: Add HCR_EL2 bit definitions from ARMv8.6

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200229012811.24129-3-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agotarget/arm: Improve masking of HCR/HCR2 RES0 bits
Richard Henderson [Thu, 5 Mar 2020 16:09:16 +0000 (16:09 +0000)] 
target/arm: Improve masking of HCR/HCR2 RES0 bits

Don't merely start with v8.0, handle v7VE as well.  Ensure that writes
from aarch32 mode do not change bits in the other half of the register.
Protect reads of aa64 id registers with ARM_FEATURE_AARCH64.

Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200229012811.24129-2-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/timer/cadence_ttc: move timer_new from init() into realize() to avoid memleaks
Pan Nengyuan [Thu, 5 Mar 2020 16:09:16 +0000 (16:09 +0000)] 
hw/timer/cadence_ttc: move timer_new from init() into realize() to avoid memleaks

There are some memleaks when we call 'device_list_properties'. This patch move timer_new from init into realize to fix it.

Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Pan Nengyuan <pannengyuan@huawei.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 20200227025055.14341-7-pannengyuan@huawei.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/arm/strongarm: move timer_new from init() into realize() to avoid memleaks
Pan Nengyuan [Thu, 5 Mar 2020 16:09:16 +0000 (16:09 +0000)] 
hw/arm/strongarm: move timer_new from init() into realize() to avoid memleaks

There are some memleaks when we call 'device_list_properties'. This patch move timer_new from init into realize to fix it.

Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Pan Nengyuan <pannengyuan@huawei.com>
Message-id: 20200227025055.14341-5-pannengyuan@huawei.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/arm/spitz: move timer_new from init() into realize() to avoid memleaks
Pan Nengyuan [Thu, 5 Mar 2020 16:09:16 +0000 (16:09 +0000)] 
hw/arm/spitz: move timer_new from init() into realize() to avoid memleaks

There are some memleaks when we call 'device_list_properties'. This patch move timer_new from init into realize to fix it.

Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Pan Nengyuan <pannengyuan@huawei.com>
Message-id: 20200227025055.14341-4-pannengyuan@huawei.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/arm/pxa2xx: move timer_new from init() into realize() to avoid memleaks
Pan Nengyuan [Thu, 5 Mar 2020 16:09:15 +0000 (16:09 +0000)] 
hw/arm/pxa2xx: move timer_new from init() into realize() to avoid memleaks

There are some memleaks when we call 'device_list_properties'. This patch move timer_new from init into realize to fix it.

Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Pan Nengyuan <pannengyuan@huawei.com>
Message-id: 20200227025055.14341-3-pannengyuan@huawei.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/arm/musicpal: Simplify since the machines are little-endian only
Philippe Mathieu-Daudé [Thu, 5 Mar 2020 16:09:15 +0000 (16:09 +0000)] 
hw/arm/musicpal: Simplify since the machines are little-endian only

We only build the little-endian softmmu configurations. Checking
for big endian is pointless, remove the unused code.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/arm/z2: Simplify since the machines are little-endian only
Philippe Mathieu-Daudé [Thu, 5 Mar 2020 16:09:15 +0000 (16:09 +0000)] 
hw/arm/z2: Simplify since the machines are little-endian only

We only build the little-endian softmmu configurations. Checking
for big endian is pointless, remove the unused code.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/arm/omap_sx1: Simplify since the machines are little-endian only
Philippe Mathieu-Daudé [Thu, 5 Mar 2020 16:09:15 +0000 (16:09 +0000)] 
hw/arm/omap_sx1: Simplify since the machines are little-endian only

We only build the little-endian softmmu configurations. Checking
for big endian is pointless, remove the unused code.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/arm/mainstone: Simplify since the machines are little-endian only
Philippe Mathieu-Daudé [Thu, 5 Mar 2020 16:09:15 +0000 (16:09 +0000)] 
hw/arm/mainstone: Simplify since the machines are little-endian only

We only build the little-endian softmmu configurations. Checking
for big endian is pointless, remove the unused code.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/arm/gumstix: Simplify since the machines are little-endian only
Philippe Mathieu-Daudé [Thu, 5 Mar 2020 16:09:14 +0000 (16:09 +0000)] 
hw/arm/gumstix: Simplify since the machines are little-endian only

As the Connex and Verdex machines only boot in little-endian,
we can simplify the code.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/arm/smmu-common: Simplify smmu_find_smmu_pcibus() logic
Philippe Mathieu-Daudé [Thu, 5 Mar 2020 16:09:14 +0000 (16:09 +0000)] 
hw/arm/smmu-common: Simplify smmu_find_smmu_pcibus() logic

The smmu_find_smmu_pcibus() function was introduced (in commit
cac994ef43b) in a code format that could return an incorrect
pointer, which was then fixed by the previous commit.
We could have avoided this by writing the if() statement
differently. Do it now, in case this function is re-used.
The code is easier to review (harder to miss bugs).

Acked-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/arm/smmu-common: a fix to smmu_find_smmu_pcibus
Eric Auger [Thu, 5 Mar 2020 16:09:14 +0000 (16:09 +0000)] 
hw/arm/smmu-common: a fix to smmu_find_smmu_pcibus

Make sure a null SMMUPciBus is returned in case we were
not able to identify a pci bus matching the @bus_num.

This matches the fix done on intel iommu in commit:
a2e1cd41ccfe796529abfd1b6aeb1dd4393762a2

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Message-Id: <20200226172628.17449-1-eric.auger@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agotarget/arm: Implement (trivially) ARMv8.2-TTCNP
Peter Maydell [Thu, 5 Mar 2020 16:09:14 +0000 (16:09 +0000)] 
target/arm: Implement (trivially) ARMv8.2-TTCNP

The ARMv8.2-TTCNP extension allows an implementation to optimize by
sharing TLB entries between multiple cores, provided that software
declares that it's ready to deal with this by setting a CnP bit in
the TTBRn_ELx.  It is mandatory from ARMv8.2 onward.

For QEMU's TLB implementation, sharing TLB entries between different
cores would not really benefit us and would be a lot of work to
implement.  So we implement this extension in the "trivial" manner:
we allow the guest to set and read back the CnP bit, but don't change
our behaviour (this is an architecturally valid implementation
choice).

The only code path which looks at the TTBRn_ELx values for the
long-descriptor format where the CnP bit is defined is already doing
enough masking to not get confused when the CnP bit at the bottom of
the register is set, so we can simply add a comment noting why we're
relying on that mask.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200225193822.18874-1-peter.maydell@linaro.org

2 years agohw/arm: versal: Generate xlnx-versal-virt zdma FDT nodes
Edgar E. Iglesias [Thu, 5 Mar 2020 16:09:14 +0000 (16:09 +0000)] 
hw/arm: versal: Generate xlnx-versal-virt zdma FDT nodes

Generate xlnx-versal-virt zdma FDT nodes.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Reviewed-by: KONRAD Frederic <frederic.konrad@adacore.com>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/arm: versal: Add support for the LPD ADMAs
Edgar E. Iglesias [Thu, 5 Mar 2020 16:09:13 +0000 (16:09 +0000)] 
hw/arm: versal: Add support for the LPD ADMAs

Add support for the Versal LPD ADMAs.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Reviewed-by: KONRAD Frederic <frederic.konrad@adacore.com>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoMerge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2020-03-05' into staging
Peter Maydell [Thu, 5 Mar 2020 15:18:18 +0000 (15:18 +0000)] 
Merge remote-tracking branch 'remotes/armbru/tags/pull-qapi-2020-03-05' into staging

QAPI patches for 2020-03-05

# gpg: Signature made Thu 05 Mar 2020 12:42:15 GMT
# gpg:                using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653
# gpg:                issuer "armbru@redhat.com"
# gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full]
# gpg:                 aka "Markus Armbruster <armbru@pond.sub.org>" [full]
# Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867  4E5F 3870 B400 EB91 8653

* remotes/armbru/tags/pull-qapi-2020-03-05:
  qapi: Brush off some (py)lint
  qapi: Use super() now we have Python 3
  qapi: Drop conditionals for Python 2
  qapi: Inheriting from object is pointless with Python 3, drop

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoMerge remote-tracking branch 'remotes/stsquad/tags/pull-testing-040320-1' into staging
Peter Maydell [Thu, 5 Mar 2020 12:13:51 +0000 (12:13 +0000)] 
Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-040320-1' into staging

Testing updates

  - some clean-ups for tests/vm
  - enable tools build for MacOSX
  - bump avocado to a newer version
  - bump travis env for avocado

# gpg: Signature made Wed 04 Mar 2020 10:00:19 GMT
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* remotes/stsquad/tags/pull-testing-040320-1:
  travis.yml: install python3 numpy and opencv libraries
  tests/acceptance: bump avocado requirements to 76.0
  configure: detect and report genisoimage
  travis: enable tools build on OS X
  tests/vm: Added gen_cloud_init_iso() to basevm.py
  tests/vm: give wait_ssh() option to wait for root
  tests/vm: increased max timeout for vm boot.
  tests/vm: Debug mode shows ssh output.
  tests/vm: use $(PYTHON) consistently

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoqapi: Brush off some (py)lint
Markus Armbruster [Wed, 4 Mar 2020 15:59:32 +0000 (16:59 +0100)] 
qapi: Brush off some (py)lint

Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20200304155932.20452-5-armbru@redhat.com>
Reviewed-by: John Snow <jsnow@redhat.com>
2 years agoqapi: Use super() now we have Python 3
Markus Armbruster [Wed, 4 Mar 2020 15:59:31 +0000 (16:59 +0100)] 
qapi: Use super() now we have Python 3

Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20200304155932.20452-4-armbru@redhat.com>
Reviewed-by: John Snow <jsnow@redhat.com>
2 years agoqapi: Drop conditionals for Python 2
Markus Armbruster [Wed, 4 Mar 2020 15:59:30 +0000 (16:59 +0100)] 
qapi: Drop conditionals for Python 2

Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20200304155932.20452-3-armbru@redhat.com>
Reviewed-by: John Snow <jsnow@redhat.com>
2 years agoqapi: Inheriting from object is pointless with Python 3, drop
Markus Armbruster [Wed, 4 Mar 2020 15:59:29 +0000 (16:59 +0100)] 
qapi: Inheriting from object is pointless with Python 3, drop

Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20200304155932.20452-2-armbru@redhat.com>
Reviewed-by: John Snow <jsnow@redhat.com>
2 years agotravis.yml: install python3 numpy and opencv libraries
Alex Bennée [Tue, 3 Mar 2020 15:06:22 +0000 (15:06 +0000)] 
travis.yml: install python3 numpy and opencv libraries

These are used for the acceptance framebuffer tests to count Tux. As
we need slightly newer python3 for opencv we bump up to bionic.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20200303150622.20133-10-alex.bennee@linaro.org>

2 years agotests/acceptance: bump avocado requirements to 76.0
Alex Bennée [Tue, 3 Mar 2020 15:06:21 +0000 (15:06 +0000)] 
tests/acceptance: bump avocado requirements to 76.0

If we want to use @skipUnless decorations on the class we need a
newer version of avocado.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200303150622.20133-9-alex.bennee@linaro.org>

2 years agoconfigure: detect and report genisoimage
Alex Bennée [Tue, 3 Mar 2020 15:06:20 +0000 (15:06 +0000)] 
configure: detect and report genisoimage

This is used for some of the vm-build tests so lets detect it and
behave sanely when it is not installed.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200303150622.20133-8-alex.bennee@linaro.org>

2 years agotravis: enable tools build on OS X
Laurent Vivier [Tue, 3 Mar 2020 15:06:19 +0000 (15:06 +0000)] 
travis: enable tools build on OS X

As we can build tools on OS X we should check we don't break build
when we submit new codes.

Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20200302154630.45620-3-lvivier@redhat.com>
Message-Id: <20200303150622.20133-7-alex.bennee@linaro.org>

2 years agotests/vm: Added gen_cloud_init_iso() to basevm.py
Robert Foley [Tue, 3 Mar 2020 15:06:18 +0000 (15:06 +0000)] 
tests/vm: Added gen_cloud_init_iso() to basevm.py

This method was located in both centos and ubuntu.i386.

Signed-off-by: Robert Foley <robert.foley@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Puhov <peter.puhov@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20200219163537.22098-6-robert.foley@linaro.org>
Message-Id: <20200303150622.20133-6-alex.bennee@linaro.org>

2 years agotests/vm: give wait_ssh() option to wait for root
Robert Foley [Tue, 3 Mar 2020 15:06:17 +0000 (15:06 +0000)] 
tests/vm: give wait_ssh() option to wait for root

Allow wait_ssh to wait for root user to be ready.
This solves the issue where we perform a wait_ssh()
successfully, but the root user is not yet ready
to be logged in.

Signed-off-by: Robert Foley <robert.foley@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Puhov <peter.puhov@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20200219163537.22098-5-robert.foley@linaro.org>
Message-Id: <20200303150622.20133-5-alex.bennee@linaro.org>

2 years agotests/vm: increased max timeout for vm boot.
Robert Foley [Tue, 3 Mar 2020 15:06:16 +0000 (15:06 +0000)] 
tests/vm: increased max timeout for vm boot.

Add change to increase timeout waiting for VM to boot.
Needed for some emulation cases where it can take longer
than 5 minutes to boot.

Signed-off-by: Robert Foley <robert.foley@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Puhov <peter.puhov@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20200219163537.22098-4-robert.foley@linaro.org>
Message-Id: <20200303150622.20133-4-alex.bennee@linaro.org>

2 years agotests/vm: Debug mode shows ssh output.
Robert Foley [Tue, 3 Mar 2020 15:06:15 +0000 (15:06 +0000)] 
tests/vm: Debug mode shows ssh output.

Add changes to tests/vm/basevm.py so that during debug mode we show ssh output.

Signed-off-by: Robert Foley <robert.foley@linaro.org>
Reviewed-by: Peter Puhov <peter.puhov@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20200219163537.22098-3-robert.foley@linaro.org>
Message-Id: <20200303150622.20133-3-alex.bennee@linaro.org>

2 years agotests/vm: use $(PYTHON) consistently
Robert Foley [Tue, 3 Mar 2020 15:06:14 +0000 (15:06 +0000)] 
tests/vm: use $(PYTHON) consistently

Change Makefile.include to use $(PYTHON) so for vm-boot-ssh to be
consistent with other cases like vm-build.

Signed-off-by: Robert Foley <robert.foley@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Puhov <peter.puhov@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20200219163537.22098-2-robert.foley@linaro.org>
Message-Id: <20200303150622.20133-2-alex.bennee@linaro.org>

2 years agoMerge remote-tracking branch 'remotes/dgilbert-gitlab/tags/pull-virtiofs-20200303...
Peter Maydell [Tue, 3 Mar 2020 15:20:12 +0000 (15:20 +0000)] 
Merge remote-tracking branch 'remotes/dgilbert-gitlab/tags/pull-virtiofs-20200303' into staging

Virtiofsd pull 2020-03-03

xattr fixes from Misono.

# gpg: Signature made Tue 03 Mar 2020 15:15:04 GMT
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* remotes/dgilbert-gitlab/tags/pull-virtiofs-20200303:
  virtiofsd: Fix xattr operations
  virtiofsd: passthrough_ll: cleanup getxattr/listxattr

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agovirtiofsd: Fix xattr operations
Misono Tomohiro [Thu, 27 Feb 2020 05:59:27 +0000 (14:59 +0900)] 
virtiofsd: Fix xattr operations

Current virtiofsd has problems about xattr operations and
they does not work properly for directory/symlink/special file.

The fundamental cause is that virtiofsd uses openat() + f...xattr()
systemcalls for xattr operation but we should not open symlink/special
file in the daemon. Therefore the function is restricted.

Fix this problem by:
 1. during setup of each thread, call unshare(CLONE_FS)
 2. in xattr operations (i.e. lo_getxattr), if inode is not a regular
    file or directory, use fchdir(proc_loot_fd) + ...xattr() +
    fchdir(root.fd) instead of openat() + f...xattr()

    (Note: for a regular file/directory openat() + f...xattr()
     is still used for performance reason)

With this patch, xfstests generic/062 passes on virtiofs.

This fix is suggested by Miklos Szeredi and Stefan Hajnoczi.
The original discussion can be found here:
  https://www.redhat.com/archives/virtio-fs/2019-October/msg00046.html

Signed-off-by: Misono Tomohiro <misono.tomohiro@jp.fujitsu.com>
Message-Id: <20200227055927.24566-3-misono.tomohiro@jp.fujitsu.com>
Acked-by: Vivek Goyal <vgoyal@redhat.com>
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2 years agovirtiofsd: passthrough_ll: cleanup getxattr/listxattr
Misono Tomohiro [Thu, 27 Feb 2020 05:59:26 +0000 (14:59 +0900)] 
virtiofsd: passthrough_ll: cleanup getxattr/listxattr

This is a cleanup patch to simplify the following xattr fix and
there is no functional changes.

- Move memory allocation to head of the function
- Unify fgetxattr/flistxattr call for both size == 0 and
  size != 0 case
- Remove redundant lo_inode_put call in error path
  (Note: second call is ignored now since @inode is already NULL)

Signed-off-by: Misono Tomohiro <misono.tomohiro@jp.fujitsu.com>
Message-Id: <20200227055927.24566-2-misono.tomohiro@jp.fujitsu.com>
Acked-by: Vivek Goyal <vgoyal@redhat.com>
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2 years agoMerge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into staging
Peter Maydell [Tue, 3 Mar 2020 12:03:59 +0000 (12:03 +0000)] 
Merge remote-tracking branch 'remotes/jasowang/tags/net-pull-request' into staging

# gpg: Signature made Tue 03 Mar 2020 10:06:06 GMT
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# Primary key fingerprint: 215D 46F4 8246 689E C77F  3562 EF04 965B 398D 6211

* remotes/jasowang/tags/net-pull-request: (23 commits)
  l2tpv3: fix RFC number typo in qemu-options.hx
  colo: Update Documentation for continuous replication
  net/filter.c: Add Options to insert filters anywhere in the filter list
  tests/test-replication.c: Add test for for secondary node continuing replication
  block/replication.c: Ignore requests after failover
  hw: net: cadence_gem: Fix build errors in DB_PRINT()
  NetRxPkt: fix hash calculation of IPV6 TCP
  NetRxPkt: Introduce support for additional hash types
  e1000e: Avoid hw_error if legacy mode used
  dp8393x: Don't stop reception upon RBE interrupt assertion
  dp8393x: Don't reset Silicon Revision register
  dp8393x: Always update RRA pointers and sequence numbers
  dp8393x: Clear descriptor in_use field to release packet
  dp8393x: Pad frames to word or long word boundary
  dp8393x: Use long-word-aligned RRA pointers in 32-bit mode
  dp8393x: Don't clobber packet checksum
  dp8393x: Implement packet size limit and RBAE interrupt
  dp8393x: Clear RRRA command register bit only when appropriate
  dp8393x: Update LLFA and CRDA registers from rx descriptor
  dp8393x: Have dp8393x_receive() return the packet size
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoMerge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf3' into...
Peter Maydell [Tue, 3 Mar 2020 11:06:39 +0000 (11:06 +0000)] 
Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-5.0-sf3' into staging

RISC-V Patches for the 5.0 Soft Freeze, Part 3

This pull request is almost entirely an implementation of the draft hypervisor
extension.  This extension is still in draft and is expected to have
incompatible changes before being frozen, but we've had good luck managing
other RISC-V draft extensions in QEMU so far.

Additionally, there's a fix to PCI addressing and some improvements to the
M-mode timer.

This boots linux and passes make check for me.

# gpg: Signature made Tue 03 Mar 2020 00:23:20 GMT
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* remotes/palmer/tags/riscv-for-master-5.0-sf3: (38 commits)
  hw/riscv: Provide rdtime callback for TCG in CLINT emulation
  target/riscv: Emulate TIME CSRs for privileged mode
  riscv: virt: Allow PCI address 0
  target/riscv: Allow enabling the Hypervisor extension
  target/riscv: Add the MSTATUS_MPV_ISSET helper macro
  target/riscv: Add support for the 32-bit MSTATUSH CSR
  target/riscv: Set htval and mtval2 on execptions
  target/riscv: Raise the new execptions when 2nd stage translation fails
  target/riscv: Implement second stage MMU
  target/riscv: Allow specifying MMU stage
  target/riscv: Respect MPRV and SPRV for floating point ops
  target/riscv: Mark both sstatus and msstatus_hs as dirty
  target/riscv: Disable guest FP support based on virtual status
  target/riscv: Only set TB flags with FP status if enabled
  target/riscv: Remove the hret instruction
  target/riscv: Add hfence instructions
  target/riscv: Add Hypervisor trap return support
  target/riscv: Add hypvervisor trap support
  target/riscv: Generate illegal instruction on WFI when V=1
  target/ricsv: Flush the TLB on virtulisation mode changes
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agol2tpv3: fix RFC number typo in qemu-options.hx
Stefan Hajnoczi [Sat, 29 Feb 2020 11:17:27 +0000 (11:17 +0000)] 
l2tpv3: fix RFC number typo in qemu-options.hx

The L2TPv3 RFC number is 3931:
https://tools.ietf.org/html/rfc3931

Reported-by: Henrik Johansson <henrikjohansson@rocketmail.com>
Reviewed-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2 years agocolo: Update Documentation for continuous replication
Lukas Straub [Thu, 24 Oct 2019 14:25:57 +0000 (16:25 +0200)] 
colo: Update Documentation for continuous replication

Document the qemu command-line and qmp commands for continuous replication

Signed-off-by: Lukas Straub <lukasstraub2@web.de>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2 years agonet/filter.c: Add Options to insert filters anywhere in the filter list
Lukas Straub [Thu, 24 Oct 2019 14:25:48 +0000 (16:25 +0200)] 
net/filter.c: Add Options to insert filters anywhere in the filter list

To switch the Secondary to Primary, we need to insert new filters
before the filter-rewriter.

Add the options insert= and position= to be able to insert filters
anywhere in the filter list.

position should be "head" or "tail" to insert at the head or
tail of the filter list or it should be "id=<id>" to specify
the id of another filter.
insert should be either "before" or "behind" to specify where to
insert the new filter relative to the one specified with position.

Signed-off-by: Lukas Straub <lukasstraub2@web.de>
Reviewed-by: Zhang Chen <chen.zhang@intel.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2 years agotests/test-replication.c: Add test for for secondary node continuing replication
Lukas Straub [Thu, 24 Oct 2019 14:25:44 +0000 (16:25 +0200)] 
tests/test-replication.c: Add test for for secondary node continuing replication

This simulates the case that happens when we resume COLO after failover.

Signed-off-by: Lukas Straub <lukasstraub2@web.de>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2 years agoblock/replication.c: Ignore requests after failover
Lukas Straub [Thu, 24 Oct 2019 14:25:35 +0000 (16:25 +0200)] 
block/replication.c: Ignore requests after failover

After failover the Secondary side of replication shouldn't change state, because
it now functions as our primary disk.

In replication_start, replication_do_checkpoint, replication_stop, ignore
the request if current state is BLOCK_REPLICATION_DONE (sucessful failover) or
BLOCK_REPLICATION_FAILOVER (failover in progres i.e. currently merging active
and hidden images into the base image).

Signed-off-by: Lukas Straub <lukasstraub2@web.de>
Reviewed-by: Zhang Chen <chen.zhang@intel.com>
Acked-by: Max Reitz <mreitz@redhat.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2 years agohw: net: cadence_gem: Fix build errors in DB_PRINT()
Bin Meng [Fri, 9 Aug 2019 07:25:44 +0000 (00:25 -0700)] 
hw: net: cadence_gem: Fix build errors in DB_PRINT()

When CADENCE_GEM_ERR_DEBUG is turned on, there are several
compilation errors in DB_PRINT(). Fix them.

While we are here, update to use appropriate modifiers in
the same DB_PRINT() call.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2 years agoNetRxPkt: fix hash calculation of IPV6 TCP
Yuri Benditovich [Mon, 27 Jan 2020 11:54:05 +0000 (13:54 +0200)] 
NetRxPkt: fix hash calculation of IPV6 TCP

When requested to calculate the hash for TCPV6 packet,
ignore overrides of source and destination addresses
in in extension headers.
Use these overrides when new hash type NetPktRssIpV6TcpEx
requested.
Use this type in e1000e hash calculation for IPv6 TCP, which
should take in account overrides of the addresses.

Signed-off-by: Yuri Benditovich <yuri.benditovich@daynix.com>
Acked-by: Dmitry Fleytman <dmitry.fleytman@gmail.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2 years agoNetRxPkt: Introduce support for additional hash types
Yuri Benditovich [Mon, 27 Jan 2020 11:54:04 +0000 (13:54 +0200)] 
NetRxPkt: Introduce support for additional hash types

Add support for following hash types:
IPV6 TCP with extension headers
IPV4 UDP
IPV6 UDP
IPV6 UDP with extension headers

Signed-off-by: Yuri Benditovich <yuri.benditovich@daynix.com>
Acked-by: Dmitry Fleytman <dmitry.fleytman@gmail.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2 years agoe1000e: Avoid hw_error if legacy mode used
Yuri Benditovich [Mon, 27 Jan 2020 16:03:12 +0000 (18:03 +0200)] 
e1000e: Avoid hw_error if legacy mode used

https://bugzilla.redhat.com/show_bug.cgi?id=1787142
The emulation issues hw_error if PSRCTL register
is written, for example, with zero value.
Such configuration does not present any problem when
DTYP bits of RCTL register define legacy format of
transfer descriptors. Current commit discards check
for BSIZE0 and BSIZE1 when legacy mode used.

Acked-by: Dmitry Fleytman <dmitry.fleytman@gmail.com>
Signed-off-by: Yuri Benditovich <yuri.benditovich@daynix.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
2 years agodp8393x: Don't stop reception upon RBE interrupt assertion
Finn Thain [Wed, 29 Jan 2020 09:27:49 +0000 (20:27 +1100)] 
dp8393x: Don't stop reception upon RBE interrupt assertion

Section 3.4.7 of the datasheet explains that,

    The RBE bit in the Interrupt Status register is set when the
    SONIC finishes using the second to last receive buffer and reads
    the last RRA descriptor. Actually, the SONIC is not truly out of
    resources, but gives the system an early warning of an impending
    out of resources condition.

RBE does not mean actual receive buffer exhaustion, and reception should
not be stopped. This is important because Linux will not check and clear
the RBE interrupt until it receives another packet. But that won't
happen if can_receive returns false. This bug causes the SONIC to become
deaf (until reset).

Fix this with a new flag to indicate actual receive buffer exhaustion.

Signed-off-by: Finn Thain <fthain@telegraphics.com.au>
Tested-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Jason Wang <jasowang@redhat.com>