qemu.git
14 months agohw/sd/sdhci: Resume pending DMA transfers on MMIO accesses
Philippe Mathieu-Daudé [Thu, 3 Sep 2020 17:00:04 +0000 (19:00 +0200)] 
hw/sd/sdhci: Resume pending DMA transfers on MMIO accesses

If we have pending DMA requests scheduled, process them first.
So far we don't need to implement a bottom half to process them.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Alexander Bulekov <alxndr@bu.edu>
Message-Id: <20200903172806.489710-3-f4bug@amsat.org>

14 months agohw/sd/sdhci: Stop multiple transfers when block count is cleared
Philippe Mathieu-Daudé [Thu, 3 Sep 2020 16:05:41 +0000 (18:05 +0200)] 
hw/sd/sdhci: Stop multiple transfers when block count is cleared

Clearing BlockCount stops multiple transfers.

See "SD Host Controller Simplified Specification Version 2.00":

- 2.2.3. Block Count Register (Offset 006h)
- Table 2-8 : Determination of Transfer Type

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Alexander Bulekov <alxndr@bu.edu>
Message-Id: <20200903172806.489710-2-f4bug@amsat.org>

14 months agohw/sd/sdhci: Fix DMA Transfer Block Size field
Philippe Mathieu-Daudé [Tue, 1 Sep 2020 13:22:06 +0000 (15:22 +0200)] 
hw/sd/sdhci: Fix DMA Transfer Block Size field

The 'Transfer Block Size' field is 12-bit wide.

See section '2.2.2. Block Size Register (Offset 004h)' in datasheet.

Two different bug reproducer available:
- https://bugs.launchpad.net/qemu/+bug/1892960
- https://ruhr-uni-bochum.sciebo.de/s/NNWP2GfwzYKeKwE?path=%2Fsdhci_oob_write1

Cc: qemu-stable@nongnu.org
Buglink: https://bugs.launchpad.net/qemu/+bug/1892960
Fixes: d7dfca0807a ("hw/sdhci: introduce standard SD host controller")
Reported-by: Alexander Bulekov <alxndr@bu.edu>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Prasad J Pandit <pjp@fedoraproject.org>
Tested-by: Alexander Bulekov <alxndr@bu.edu>
Message-Id: <20200901140411.112150-3-f4bug@amsat.org>

14 months agohw/sd/sdhci: Document the datasheet used
Philippe Mathieu-Daudé [Tue, 1 Sep 2020 13:23:14 +0000 (15:23 +0200)] 
hw/sd/sdhci: Document the datasheet used

Add datasheet name in the file header.

We can not add the direct download link since there is a disclaimers
to agree first on the SD Association website (www.sdcard.org).

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Alexander Bulekov <alxndr@bu.edu>
Message-Id: <20200901140411.112150-3-f4bug@amsat.org>

14 months agohw/sd/sdhci: Fix qemu_log_mask() format string
Philippe Mathieu-Daudé [Tue, 1 Sep 2020 13:21:54 +0000 (15:21 +0200)] 
hw/sd/sdhci: Fix qemu_log_mask() format string

Add missing newline character in qemu_log_mask() format.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Alexander Bulekov <alxndr@bu.edu>
Message-Id: <20200901140411.112150-2-f4bug@amsat.org>

14 months agoMerge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20201020-1' into...
Peter Maydell [Tue, 20 Oct 2020 20:11:35 +0000 (21:11 +0100)] 
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20201020-1' into staging

target-arm queue:
 * Fix AArch32 SMLAD incorrect setting of Q bit
 * AArch32 VCVT fixed-point to float is always round-to-nearest
 * strongarm: Fix 'time to transmit a char' unit comment
 * Restrict APEI tables generation to the 'virt' machine
 * bcm2835: minor code cleanups
 * bcm2835: connect all IRQs from SYS_timer device
 * correctly flush TLBs when TBI is enabled
 * tests/qtest: Add npcm7xx timer test
 * loads-stores.rst: add footnote that clarifies GETPC usage
 * Fix reported EL for mte_check_fail
 * Ignore HCR_EL2.ATA when {E2H,TGE} != 11
 * microbit_i2c: Fix coredump when dump-vmstate
 * nseries: Fix loading kernel image on n8x0 machines
 * Implement v8.1M low-overhead-loops

# gpg: Signature made Tue 20 Oct 2020 21:10:35 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20201020-1: (29 commits)
  target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension
  target/arm: Allow M-profile CPUs with FP16 to set FPSCR.FP16
  target/arm: Fix has_vfp/has_neon ID reg squashing for M-profile
  target/arm: Implement v8.1M low-overhead-loop instructions
  target/arm: Implement v8.1M branch-future insns (as NOPs)
  target/arm: Don't allow BLX imm for M-profile
  target/arm: Make the t32 insn[25:23]=111 group non-overlapping
  target/arm: Implement v8.1M conditional-select insns
  target/arm: Implement v8.1M NOCP handling
  decodetree: Fix codegen for non-overlapping group inside overlapping group
  hw/arm/nseries: Fix loading kernel image on n8x0 machines
  microbit_i2c: Fix coredump when dump-vmstate
  target/arm: Ignore HCR_EL2.ATA when {E2H,TGE} != 11
  target/arm: Fix reported EL for mte_check_fail
  target/arm: Remove redundant mmu_idx lookup
  hw/intc/bcm2836_control: Use IRQ definitions instead of magic numbers
  hw/intc/bcm2835_ic: Trace GPU/CPU IRQ handlers
  loads-stores.rst: add footnote that clarifies GETPC usage
  tests/qtest: Add npcm7xx timer test
  target/arm: Use tlb_flush_page_bits_by_mmuidx*
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14 months agotarget/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension
Peter Maydell [Mon, 19 Oct 2020 15:13:01 +0000 (16:13 +0100)] 
target/arm: Implement FPSCR.LTPSIZE for M-profile LOB extension

If the M-profile low-overhead-branch extension is implemented, FPSCR
bits [18:16] are a new field LTPSIZE.  If MVE is not implemented
(currently always true for us) then this field always reads as 4 and
ignores writes.

These bits used to be the vector-length field for the old
short-vector extension, so we need to take care that they are not
misinterpreted as setting vec_len. We do this with a rearrangement
of the vfp_set_fpscr() code that deals with vec_len, vec_stride
and also the QC bit; this obviates the need for the M-profile
only masking step that we used to have at the start of the function.

We provide a new field in CPUState for LTPSIZE, even though this
will always be 4, in preparation for MVE, so we don't have to
come back later and split it out of the vfp.xregs[FPSCR] value.
(This state struct field will be saved and restored as part of
the FPSCR value via the vmstate_fpscr in machine.c.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201019151301.2046-11-peter.maydell@linaro.org

14 months agotarget/arm: Allow M-profile CPUs with FP16 to set FPSCR.FP16
Peter Maydell [Mon, 19 Oct 2020 15:13:00 +0000 (16:13 +0100)] 
target/arm: Allow M-profile CPUs with FP16 to set FPSCR.FP16

M-profile CPUs with half-precision floating point support should
be able to write to FPSCR.FZ16, but an M-profile specific masking
of the value at the top of vfp_set_fpscr() currently prevents that.
This is not yet an active bug because we have no M-profile
FP16 CPUs, but needs to be fixed before we can add any.

The bits that the masking is effectively preventing from being
set are the A-profile only short-vector Len and Stride fields,
plus the Neon QC bit. Rearrange the order of the function so
that those fields are handled earlier and only under a suitable
guard; this allows us to drop the M-profile specific masking,
making FZ16 writeable.

This change also makes the QC bit correctly RAZ/WI for older
no-Neon A-profile cores.

This refactoring also paves the way for the low-overhead-branch
LTPSIZE field, which uses some of the bits that are used for
A-profile Stride and Len.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201019151301.2046-10-peter.maydell@linaro.org

14 months agotarget/arm: Fix has_vfp/has_neon ID reg squashing for M-profile
Peter Maydell [Mon, 19 Oct 2020 15:12:59 +0000 (16:12 +0100)] 
target/arm: Fix has_vfp/has_neon ID reg squashing for M-profile

In arm_cpu_realizefn(), if the CPU has VFP or Neon disabled then we
squash the ID register fields so that we don't advertise it to the
guest.  This code was written for A-profile and needs some tweaks to
work correctly on M-profile:

 * A-profile only fields should not be zeroed on M-profile:
   - MVFR0.FPSHVEC,FPTRAP
   - MVFR1.SIMDLS,SIMDINT,SIMDSP,SIMDHP
   - MVFR2.SIMDMISC
 * M-profile only fields should be zeroed on M-profile:
   - MVFR1.FP16

In particular, because MVFR1.SIMDHP on A-profile is the same field as
MVFR1.FP16 on M-profile this code was incorrectly disabling FP16
support on an M-profile CPU (where has_neon is always false).  This
isn't a visible bug yet because we don't have any M-profile CPUs with
FP16 support, but the change is necessary before we introduce any.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20201019151301.2046-9-peter.maydell@linaro.org

14 months agotarget/arm: Implement v8.1M low-overhead-loop instructions
Peter Maydell [Mon, 19 Oct 2020 15:12:58 +0000 (16:12 +0100)] 
target/arm: Implement v8.1M low-overhead-loop instructions

v8.1M's "low-overhead-loop" extension has three instructions
for looping:
 * DLS (start of a do-loop)
 * WLS (start of a while-loop)
 * LE (end of a loop)

The loop-start instructions are both simple operations to start a
loop whose iteration count (if any) is in LR.  The loop-end
instruction handles "decrement iteration count and jump back to loop
start"; it also caches the information about the branch back to the
start of the loop to improve performance of the branch on subsequent
iterations.

As with the branch-future instructions, the architecture permits an
implementation to discard the LO_BRANCH_INFO cache at any time, and
QEMU takes the IMPDEF option to never set it in the first place
(equivalent to discarding it immediately), because for us a "real"
implementation would be unnecessary complexity.

(This implementation only provides the simple looping constructs; the
vector extension MVE (Helium) adds some extra variants to handle
looping across vectors.  We'll add those later when we implement
MVE.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201019151301.2046-8-peter.maydell@linaro.org

14 months agotarget/arm: Implement v8.1M branch-future insns (as NOPs)
Peter Maydell [Mon, 19 Oct 2020 15:12:57 +0000 (16:12 +0100)] 
target/arm: Implement v8.1M branch-future insns (as NOPs)

v8.1M implements a new 'branch future' feature, which is a
set of instructions that request the CPU to perform a branch
"in the future", when it reaches a particular execution address.
In hardware, the expected implementation is that the information
about the branch location and destination is cached and then
acted upon when execution reaches the specified address.
However the architecture permits an implementation to discard
this cached information at any point, and so guest code must
always include a normal branch insn at the branch point as
a fallback. In particular, an implementation is specifically
permitted to treat all BF insns as NOPs (which is equivalent
to discarding the cached information immediately).

For QEMU, implementing this caching of branch information
would be complicated and would not improve the speed of
execution at all, so we make the IMPDEF choice to implement
all BF insns as NOPs.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20201019151301.2046-7-peter.maydell@linaro.org

14 months agotarget/arm: Don't allow BLX imm for M-profile
Peter Maydell [Mon, 19 Oct 2020 15:12:56 +0000 (16:12 +0100)] 
target/arm: Don't allow BLX imm for M-profile

The BLX immediate insn in the Thumb encoding always performs
a switch from Thumb to Arm state. This would be totally useless
in M-profile which has no Arm decoder, and so the instruction
does not exist at all there. Make the encoding UNDEF for M-profile.

(This part of the encoding space is used for the branch-future
and low-overhead-loop insns in v8.1M.)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20201019151301.2046-6-peter.maydell@linaro.org

14 months agotarget/arm: Make the t32 insn[25:23]=111 group non-overlapping
Peter Maydell [Mon, 19 Oct 2020 15:12:55 +0000 (16:12 +0100)] 
target/arm: Make the t32 insn[25:23]=111 group non-overlapping

The t32 decode has a group which represents a set of insns
which overlap with B_cond_thumb because they have [25:23]=111
(which is an invalid condition code field for the branch insn).
This group is currently defined using the {} overlap-OK syntax,
but it is almost entirely non-overlapping patterns. Switch
it over to use a non-overlapping group.

For this to be valid syntactically, CPS must move into the same
overlapping-group as the hint insns (CPS vs hints was the
only actual use of the overlap facility for the group).

The non-overlapping subgroup for CLREX/DSB/DMB/ISB/SB is no longer
necessary and so we can remove it (promoting those insns to
be members of the parent group).

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20201019151301.2046-5-peter.maydell@linaro.org

14 months agotarget/arm: Implement v8.1M conditional-select insns
Peter Maydell [Mon, 19 Oct 2020 15:12:54 +0000 (16:12 +0100)] 
target/arm: Implement v8.1M conditional-select insns

v8.1M brings four new insns to M-profile:
 * CSEL  : Rd = cond ? Rn : Rm
 * CSINC : Rd = cond ? Rn : Rm+1
 * CSINV : Rd = cond ? Rn : ~Rm
 * CSNEG : Rd = cond ? Rn : -Rm

Implement these.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20201019151301.2046-4-peter.maydell@linaro.org

14 months agotarget/arm: Implement v8.1M NOCP handling
Peter Maydell [Mon, 19 Oct 2020 15:12:53 +0000 (16:12 +0100)] 
target/arm: Implement v8.1M NOCP handling

From v8.1M, disabled-coprocessor handling changes slightly:
 * coprocessors 8, 9, 14 and 15 are also governed by the
   cp10 enable bit, like cp11
 * an extra range of instruction patterns is considered
   to be inside the coprocessor space

We previously marked these up with TODO comments; implement the
correct behaviour.

Unfortunately there is no ID register field which indicates this
behaviour.  We could in theory test an unrelated ID register which
indicates guaranteed-to-be-in-v8.1M behaviour like ID_ISAR0.CmpBranch
>= 3 (low-overhead-loops), but it seems better to simply define a new
ARM_FEATURE_V8_1M feature flag and use it for this and other
new-in-v8.1M behaviour that isn't identifiable from the ID registers.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201019151301.2046-3-peter.maydell@linaro.org

14 months agodecodetree: Fix codegen for non-overlapping group inside overlapping group
Peter Maydell [Mon, 19 Oct 2020 15:12:52 +0000 (16:12 +0100)] 
decodetree: Fix codegen for non-overlapping group inside overlapping group

For nested groups like:

  {
    [
      pattern 1
      pattern 2
    ]
    pattern 3
  }

the intended behaviour is that patterns 1 and 2 must not
overlap with each other; if the insn matches neither then
we fall through to pattern 3 as the next thing in the
outer overlapping group.

Currently we generate incorrect code for this situation,
because in the code path for a failed match inside the
inner non-overlapping group we generate a "return" statement,
which causes decode to stop entirely rather than continuing
to the next thing in the outer group.

Generate a "break" instead, so that decode flow behaves
as required for this nested group case.

Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20201019151301.2046-2-peter.maydell@linaro.org

14 months agohw/arm/nseries: Fix loading kernel image on n8x0 machines
Philippe Mathieu-Daudé [Mon, 19 Oct 2020 09:51:48 +0000 (11:51 +0200)] 
hw/arm/nseries: Fix loading kernel image on n8x0 machines

Commit 7998beb9c2e removed the ram_size initialization in the
arm_boot_info structure, however it is used by arm_load_kernel().

Initialize the field to fix:

  $ qemu-system-arm -M n800 -append 'console=ttyS1' \
    -kernel meego-arm-n8x0-1.0.80.20100712.1431-vmlinuz-2.6.35~rc4-129.1-n8x0
  qemu-system-arm: kernel 'meego-arm-n8x0-1.0.80.20100712.1431-vmlinuz-2.6.35~rc4-129.1-n8x0' is too large to fit in RAM (kernel size 1964608, RAM size 0)

Noticed while running the test introduced in commit 050a82f0c5b
("tests/acceptance: Add a test for the N800 and N810 arm machines").

Fixes: 7998beb9c2e ("arm/nseries: use memdev for RAM")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Tested-by: Thomas Huth <thuth@redhat.com>
Message-id: 20201019095148.1602119-1-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14 months agomicrobit_i2c: Fix coredump when dump-vmstate
Peng Liang [Mon, 19 Oct 2020 09:34:01 +0000 (17:34 +0800)] 
microbit_i2c: Fix coredump when dump-vmstate

VMStateDescription.fields should be end with VMSTATE_END_OF_LIST().
However, microbit_i2c_vmstate doesn't follow it.  Let's change it.

Fixes: 9d68bf564e ("arm: Stub out NRF51 TWI magnetometer/accelerometer detection")
Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Peng Liang <liangpeng10@huawei.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20201019093401.2993833-1-liangpeng10@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14 months agotarget/arm: Ignore HCR_EL2.ATA when {E2H,TGE} != 11
Richard Henderson [Thu, 8 Oct 2020 16:21:55 +0000 (11:21 -0500)] 
target/arm: Ignore HCR_EL2.ATA when {E2H,TGE} != 11

Unlike many other bits in HCR_EL2, the description for this
bit does not contain the phrase "if ... this field behaves
as 0 for all purposes other than", so do not squash the bit
in arm_hcr_el2_eff.

Instead, replicate the E2H+TGE test in the two places that
require it.

Reported-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Tested-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Message-id: 20201008162155.161886-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14 months agotarget/arm: Fix reported EL for mte_check_fail
Richard Henderson [Thu, 8 Oct 2020 16:21:54 +0000 (11:21 -0500)] 
target/arm: Fix reported EL for mte_check_fail

The reporting in AArch64.TagCheckFail only depends on PSTATE.EL,
and not the AccType of the operation.  There are two guest
visible problems that affect LDTR and STTR because of this:

(1) Selecting TCF0 vs TCF1 to decide on reporting,
(2) Report "data abort same el" not "data abort lower el".

Reported-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Tested-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Message-id: 20201008162155.161886-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14 months agotarget/arm: Remove redundant mmu_idx lookup
Richard Henderson [Thu, 8 Oct 2020 16:21:53 +0000 (11:21 -0500)] 
target/arm: Remove redundant mmu_idx lookup

We already have the full ARMMMUIdx as computed from the
function parameter.

For the purpose of regime_has_2_ranges, we can ignore any
difference between AccType_Normal and AccType_Unpriv, which
would be the only difference between the passed mmu_idx
and arm_mmu_idx_el.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Tested-by: Vincenzo Frascino <vincenzo.frascino@arm.com>
Message-id: 20201008162155.161886-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14 months agohw/intc/bcm2836_control: Use IRQ definitions instead of magic numbers
Philippe Mathieu-Daudé [Sat, 17 Oct 2020 18:07:31 +0000 (20:07 +0200)] 
hw/intc/bcm2836_control: Use IRQ definitions instead of magic numbers

The IRQ values are defined few lines earlier, use them instead of
the magic numbers.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201017180731.1165871-3-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14 months agohw/intc/bcm2835_ic: Trace GPU/CPU IRQ handlers
Philippe Mathieu-Daudé [Sat, 17 Oct 2020 18:07:30 +0000 (20:07 +0200)] 
hw/intc/bcm2835_ic: Trace GPU/CPU IRQ handlers

Add trace events for GPU and CPU IRQs.

Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201017180731.1165871-2-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14 months agoloads-stores.rst: add footnote that clarifies GETPC usage
Emanuele Giuseppe Esposito [Thu, 15 Oct 2020 09:51:47 +0000 (11:51 +0200)] 
loads-stores.rst: add footnote that clarifies GETPC usage

Current documentation is not too clear on the GETPC usage.
In particular, when used outside the top level helper function
it causes unexpected behavior.

Signed-off-by: Emanuele Giuseppe Esposito <e.emanuelegiuseppe@gmail.com>
Message-id: 20201015095147.1691-1-e.emanuelegiuseppe@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14 months agotests/qtest: Add npcm7xx timer test
Havard Skinnemoen [Thu, 8 Oct 2020 23:21:49 +0000 (16:21 -0700)] 
tests/qtest: Add npcm7xx timer test

This test exercises the various modes of the npcm7xx timer. In
particular, it triggers the bug found by the fuzzer, as reported here:

https://lists.gnu.org/archive/html/qemu-devel/2020-09/msg02992.html

It also found several other bugs, especially related to interrupt
handling.

The test exercises all the timers in all the timer modules, which
expands to 180 test cases in total.

Reviewed-by: Tyrone Ting <kfting@nuvoton.com>
Signed-off-by: Havard Skinnemoen <hskinnemoen@google.com>
Message-id: 20201008232154.94221-2-hskinnemoen@google.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14 months agotarget/arm: Use tlb_flush_page_bits_by_mmuidx*
Richard Henderson [Fri, 16 Oct 2020 21:07:54 +0000 (14:07 -0700)] 
target/arm: Use tlb_flush_page_bits_by_mmuidx*

When TBI is enabled in a given regime, 56 bits of the address
are significant and we need to clear out any other matching
virtual addresses with differing tags.

The other uses of tlb_flush_page (without mmuidx) in this file
are only used by aarch32 mode.

Fixes: 38d931687fa1
Reported-by: Jordan Frank <jordanfrank@fb.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201016210754.818257-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14 months agoaccel/tcg: Add tlb_flush_page_bits_by_mmuidx*
Richard Henderson [Fri, 16 Oct 2020 21:07:53 +0000 (14:07 -0700)] 
accel/tcg: Add tlb_flush_page_bits_by_mmuidx*

On ARM, the Top Byte Ignore feature means that only 56 bits of
the address are significant in the virtual address.  We are
required to give the entire 64-bit address to FAR_ELx on fault,
which means that we do not "clean" the top byte early in TCG.

This new interface allows us to flush all 256 possible aliases
for a given page, currently missed by tlb_flush_page*.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20201016210754.818257-2-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14 months agohw/arm/bcm2835_peripherals: Correctly wire the SYS_timer IRQs
Philippe Mathieu-Daudé [Sat, 10 Oct 2020 20:37:09 +0000 (22:37 +0200)] 
hw/arm/bcm2835_peripherals: Correctly wire the SYS_timer IRQs

The SYS_timer is not directly wired to the ARM core, but to the
SoC (peripheral) interrupt controller.

Fixes: 0e5bbd74064 ("hw/arm/bcm2835_peripherals: Use the SYS_timer")
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201010203709.3116542-5-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14 months agohw/timer/bcm2835: Support the timer COMPARE registers
Philippe Mathieu-Daudé [Sat, 10 Oct 2020 20:37:08 +0000 (22:37 +0200)] 
hw/timer/bcm2835: Support the timer COMPARE registers

This peripheral has 1 free-running timer and 4 compare registers.

Only the free-running timer is implemented. Add support the
COMPARE registers (each register is wired to an IRQ).

Reference: "BCM2835 ARM Peripherals" datasheet [*]
            chapter 12 "System Timer":

  The System Timer peripheral provides four 32-bit timer channels
  and a single 64-bit free running counter. Each channel has an
  output compare register, which is compared against the 32 least
  significant bits of the free running counter values. When the
  two values match, the system timer peripheral generates a signal
  to indicate a match for the appropriate channel. The match signal
  is then fed into the interrupt controller.

This peripheral is used since Linux 3.7, commit ee4af5696720
("ARM: bcm2835: add system timer").

[*] https://www.raspberrypi.org/app/uploads/2012/02/BCM2835-ARM-Peripherals.pdf

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Message-id: 20201010203709.3116542-4-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14 months agohw/timer/bcm2835: Rename variable holding CTRL_STATUS register
Philippe Mathieu-Daudé [Sat, 10 Oct 2020 20:37:07 +0000 (22:37 +0200)] 
hw/timer/bcm2835: Rename variable holding CTRL_STATUS register

The variable holding the CTRL_STATUS register is misnamed
'status'. Rename it 'ctrl_status' to make it more obvious
this register is also used to control the peripheral.

Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201010203709.3116542-3-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14 months agohw/timer/bcm2835: Introduce BCM2835_SYSTIMER_COUNT definition
Philippe Mathieu-Daudé [Sat, 10 Oct 2020 20:37:06 +0000 (22:37 +0200)] 
hw/timer/bcm2835: Introduce BCM2835_SYSTIMER_COUNT definition

Use the BCM2835_SYSTIMER_COUNT definition instead of the
magic '4' value.

Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201010203709.3116542-2-f4bug@amsat.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14 months agohw/arm: Restrict APEI tables generation to the 'virt' machine
Philippe Mathieu-Daudé [Thu, 8 Oct 2020 16:14:14 +0000 (18:14 +0200)] 
hw/arm: Restrict APEI tables generation to the 'virt' machine

While APEI is a generic ACPI feature (usable by X86 and ARM64), only
the 'virt' machine uses it, by enabling the RAS Virtualization. See
commit 2afa8c8519: "hw/arm/virt: Introduce a RAS machine option").

Restrict the APEI tables generation code to the single user: the virt
machine. If another machine wants to use it, it simply has to 'select
ACPI_APEI' in its Kconfig.

Fixes: aa16508f1d ("ACPI: Build related register address fields via hardware error fw_cfg blob")
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Dongjiu Geng <gengdongjiu@huawei.com>
Acked-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20201008161414.2672569-1-philmd@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14 months agohw/arm/strongarm: Fix 'time to transmit a char' unit comment
Philippe Mathieu-Daudé [Wed, 14 Oct 2020 21:36:01 +0000 (23:36 +0200)] 
hw/arm/strongarm: Fix 'time to transmit a char' unit comment

The time to transmit a char is expressed in nanoseconds, not in ticks.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20201014213601.205222-1-f4bug@amsat.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
14 months agotarget/arm: AArch32 VCVT fixed-point to float is always round-to-nearest
Peter Maydell [Tue, 13 Oct 2020 10:35:32 +0000 (11:35 +0100)] 
target/arm: AArch32 VCVT fixed-point to float is always round-to-nearest

For AArch32, unlike the VCVT of integer to float, which honours the
rounding mode specified by the FPSCR, VCVT of fixed-point to float is
always round-to-nearest. (AArch64 fixed-point-to-float conversions
always honour the FPCR rounding mode.)

Implement this by providing _round_to_nearest versions of the
relevant helpers which set the rounding mode temporarily when making
the call to the underlying softfloat function.

We only need to change the VFP VCVT instructions, because the
standard- FPSCR value used by the Neon VCVT is always set to
round-to-nearest, so we don't need to do the extra work of saving
and restoring the rounding mode.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201013103532.13391-1-peter.maydell@linaro.org

14 months agotarget/arm: Fix SMLAD incorrect setting of Q bit
Peter Maydell [Fri, 9 Oct 2020 14:47:12 +0000 (15:47 +0100)] 
target/arm: Fix SMLAD incorrect setting of Q bit

The SMLAD instruction is supposed to:
 * signed multiply Rn[15:0] * Rm[15:0]
 * signed multiply Rn[31:16] * Rm[31:16]
 * perform a signed addition of the products and Ra
 * set Rd to the low 32 bits of the theoretical
   infinite-precision result
 * set the Q flag if the sign-extension of Rd
   would differ from the infinite-precision result
   (ie on overflow)

Our current implementation doesn't quite do this, though: it performs
an addition of the products setting Q on overflow, and then it adds
Ra, again possibly setting Q.  This sometimes incorrectly sets Q when
the architecturally mandated only-check-for-overflow-once algorithm
does not. For instance:
 r1 = 0x80008000; r2 = 0x80008000; r3 = 0xffffffff
 smlad r0, r1, r2, r3
This is (-32768 * -32768) + (-32768 * -32768) - 1

The products are both 0x4000_0000, so when added together as 32-bit
signed numbers they overflow (and QEMU sets Q), but because the
addition of Ra == -1 brings the total back down to 0x7fff_ffff
there is no overflow for the complete operation and setting Q is
incorrect.

Fix this edge case by resorting to 64-bit arithmetic for the
case where we need to add three values together.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20201009144712.11187-1-peter.maydell@linaro.org

14 months agoMerge remote-tracking branch 'remotes/aperard/tags/pull-xen-20201020' into staging
Peter Maydell [Tue, 20 Oct 2020 10:20:36 +0000 (11:20 +0100)] 
Merge remote-tracking branch 'remotes/aperard/tags/pull-xen-20201020' into staging

Xen queue

* cleanup patches.
* improve xen backend setup performance when other xen guests are
  running/booting.
* improve xen guest migration when running in a stubdomain.

# gpg: Signature made Tue 20 Oct 2020 10:55:11 BST
# gpg:                using RSA key F80C006308E22CFD8A92E7980CF5572FD7FB55AF
# gpg:                issuer "anthony.perard@citrix.com"
# gpg: Good signature from "Anthony PERARD <anthony.perard@gmail.com>" [marginal]
# gpg:                 aka "Anthony PERARD <anthony.perard@citrix.com>" [marginal]
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg:          It is not certain that the signature belongs to the owner.
# Primary key fingerprint: 5379 2F71 024C 600F 778A  7161 D8D5 7199 DF83 42C8
#      Subkey fingerprint: F80C 0063 08E2 2CFD 8A92  E798 0CF5 572F D7FB 55AF

* remotes/aperard/tags/pull-xen-20201020:
  hw/xen: Set suppress-vmdesc for Xen machines
  xen-bus: reduce scope of backend watch
  xen: Rename XENBACKEND_DEVICE to XENBACKEND
  xen: xenguest is not used so is not needed

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15 months agohw/xen: Set suppress-vmdesc for Xen machines
Jason Andryuk [Tue, 13 Oct 2020 19:05:06 +0000 (15:05 -0400)] 
hw/xen: Set suppress-vmdesc for Xen machines

xen-save-devices-state doesn't currently generate a vmdesc, so restore
always triggers "Expected vmdescription section, but got 0".  This is
not a problem when restore comes from a file.  However, when QEMU runs
in a linux stubdom and comes over a console, EOF is not received.  This
causes a delay restoring - though it does restore.

Setting suppress-vmdesc skips looking for the vmdesc during restore and
avoids the wait.

The other approach would be generate a vmdesc in qemu_save_device_state.
Since COLO shared that function, and the vmdesc is just discarded on
restore, we choose to skip it.

Reported-by: Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com>
Signed-off-by: Jason Andryuk <jandryuk@gmail.com>
Acked-by: Anthony PERARD <anthony.perard@citrix.com>
Message-Id: <20201013190506.3325-1-jandryuk@gmail.com>
Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
15 months agoxen-bus: reduce scope of backend watch
Paul Durrant [Thu, 1 Oct 2020 08:15:00 +0000 (09:15 +0100)] 
xen-bus: reduce scope of backend watch

Currently a single watch on /local/domain/X/backend is registered by each
QEMU process running in service domain X (where X is usually 0). The purpose
of this watch is to ensure that QEMU is notified when the Xen toolstack
creates a new device backend area.
Such a backend area is specific to a single frontend area created for a
specific guest domain and, since each QEMU process is also created to service
a specfic guest domain, it is unnecessary and inefficient to notify all QEMU
processes.
Only the QEMU process associated with the same guest domain need
receive the notification. This patch re-factors the watch registration code
such that notifications are targetted appropriately.

Reported-by: Jerome Leseinne <jerome.leseinne@gmail.com>
Signed-off-by: Paul Durrant <pdurrant@amazon.com>
Reviewed-by: Anthony PERARD <anthony.perard@citrix.com>
Message-Id: <20201001081500.1026-1-paul@xen.org>
Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
15 months agoxen: Rename XENBACKEND_DEVICE to XENBACKEND
Eduardo Habkost [Wed, 2 Sep 2020 22:43:05 +0000 (18:43 -0400)] 
xen: Rename XENBACKEND_DEVICE to XENBACKEND

Make the type checking macro name consistent with the TYPE_*
constant.

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Acked-by: Anthony PERARD <anthony.perard@citrix.com>
Message-Id: <20200902224311.1321159-58-ehabkost@redhat.com>
Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
15 months agoxen: xenguest is not used so is not needed
Michael Tokarev [Mon, 27 Jul 2020 14:00:48 +0000 (17:00 +0300)] 
xen: xenguest is not used so is not needed

There's no references in only file which includes xenguest.h
to any xen definitions. And there's no references to -lxenguest
in qemu, either. Drop it.

Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
Reviewed-by: Anthony PERARD <anthony.perard@citrix.com>
Message-Id: <20200727140048.19779-1-mjt@msgid.tls.msk.ru>
[perard: rebased]
Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
15 months agoMerge remote-tracking branch 'remotes/cschoenebeck/tags/pull-9p-20201019' into staging
Peter Maydell [Mon, 19 Oct 2020 13:39:26 +0000 (14:39 +0100)] 
Merge remote-tracking branch 'remotes/cschoenebeck/tags/pull-9p-20201019' into staging

9pfs: add tests using local fs driver

The currently existing 9pfs test cases are all solely using the 9pfs 'synth'
fileystem driver, which is a very simple and purely simulated (in RAM only)
filesystem. There are issues though where the 'synth' fs driver is not
sufficient. For example the following two bugs need test cases running the
9pfs 'local' fs driver:

https://bugs.launchpad.net/qemu/+bug/1336794
https://bugs.launchpad.net/qemu/+bug/1877384

This patch set for that reason introduces 9pfs test cases using the 9pfs
'local' filesystem driver along to the already existing tests on 'synth'.

# gpg: Signature made Mon 19 Oct 2020 13:39:08 BST
# gpg:                using RSA key 96D8D110CF7AF8084F88590134C2B58765A47395
# gpg:                issuer "qemu_oss@crudebyte.com"
# gpg: Good signature from "Christian Schoenebeck <qemu_oss@crudebyte.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: ECAB 1A45 4014 1413 BA38  4926 30DB 47C3 A012 D5F4
#      Subkey fingerprint: 96D8 D110 CF7A F808 4F88  5901 34C2 B587 65A4 7395

* remotes/cschoenebeck/tags/pull-9p-20201019:
  tests/9pfs: add local Tmkdir test
  tests/9pfs: add virtio_9p_test_path()
  tests/9pfs: wipe local 9pfs test directory
  tests/9pfs: introduce local tests
  tests/9pfs: change qtest name prefix to synth
  9pfs: suppress performance warnings on qtest runs

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15 months agoMerge remote-tracking branch 'remotes/kraxel/tags/usb-20201019-pull-request' into...
Peter Maydell [Mon, 19 Oct 2020 12:43:43 +0000 (13:43 +0100)] 
Merge remote-tracking branch 'remotes/kraxel/tags/usb-20201019-pull-request' into staging

usb: fixes for dwc2 + ehci.

# gpg: Signature made Mon 19 Oct 2020 13:33:16 BST
# gpg:                using RSA key 4CB6D8EED3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full]
# gpg:                 aka "Gerd Hoffmann <gerd@kraxel.org>" [full]
# gpg:                 aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full]
# Primary key fingerprint: A032 8CFF B93A 17A7 9901  FE7D 4CB6 D8EE D3E8 7138

* remotes/kraxel/tags/usb-20201019-pull-request:
  hw/usb/hcd-dwc2: fix divide-by-zero in dwc2_handle_packet()
  usb/hcd-ehci: Fix error handling on missing device for iTD
  usb: hcd-dwc2: change assert()s to qemu_log_mask(LOG_GUEST_ERROR...)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15 months agotests/9pfs: add local Tmkdir test
Christian Schoenebeck [Thu, 8 Oct 2020 18:34:56 +0000 (20:34 +0200)] 
tests/9pfs: add local Tmkdir test

This test case uses the 9pfs 'local' driver to create a directory
and then checks if the expected directory was actually created
(as real directory) on host side.

This patch introduces a custom split() implementation, because
the test code requires non empty array elements as result. For
that reason g_strsplit() would not be a good alternative, as
it would require additional filter code for reshuffling the
array, and the resulting code would be even more complex than
this split() function.

Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Message-Id: <be342f236842272275f65dbe05587f0a5409ad77.1602182956.git.qemu_oss@crudebyte.com>
Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
15 months agotests/9pfs: add virtio_9p_test_path()
Christian Schoenebeck [Thu, 8 Oct 2020 18:34:56 +0000 (20:34 +0200)] 
tests/9pfs: add virtio_9p_test_path()

This new public function virtio_9p_test_path() allows 9pfs
'local' tests to translate a path from guest scope to host
scope. For instance by passing an empty string it would
return the root path on host of the exported 9pfs tree.

Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Message-Id: <b563d3c73c6391ec927a2622c9f65c09ca56bd83.1602182956.git.qemu_oss@crudebyte.com>
Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
15 months agotests/9pfs: wipe local 9pfs test directory
Christian Schoenebeck [Thu, 8 Oct 2020 18:34:56 +0000 (20:34 +0200)] 
tests/9pfs: wipe local 9pfs test directory

Before running the first 9pfs test case, make sure the test directory
for running the 9pfs 'local' tests on is entirely empty. For that
reason simply delete the test directory (if any) before (re)creating
it on test suite startup.

Note: The preferable precise behaviour would be the test directory
only being wiped once *before* a test suite run. Right now the test
directory is also wiped at the *end* of a test suite run because
libqos is calling the virtio_9p_register_nodes() callback for some
reason also when a test suite completed. This is suboptimal as
developers cannot immediately see what files and directories the
9pfs local tests created precisely after the test suite completed.
But fortunately the test directory is not wiped if some test failed.
So it is probably not worth it drilling another hole into libqos
for this issue.

Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Message-Id: <b30776ea3289dc40dabc7d0063d825d21d9a65bf.1602182956.git.qemu_oss@crudebyte.com>
Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
15 months agotests/9pfs: introduce local tests
Christian Schoenebeck [Thu, 8 Oct 2020 18:34:56 +0000 (20:34 +0200)] 
tests/9pfs: introduce local tests

This patch introduces 9pfs test cases using the 9pfs 'local'
filesystem driver which reads/writes/creates/deletes real files
and directories.

In this initial version, there is only one local test which actually
only checks if the 9pfs 'local' device was created successfully.

Before the 9pfs 'local' tests are run, a test directory 'qtest-9p-local'
is created (with world rwx permissions) under the current working
directory. At this point that test directory is not auto deleted yet.

Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Message-Id: <81fc4b3b6b6c9bf7999e79f5e7cbc364a5f09ddb.1602182956.git.qemu_oss@crudebyte.com>
Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
15 months agotests/9pfs: change qtest name prefix to synth
Christian Schoenebeck [Thu, 8 Oct 2020 18:34:56 +0000 (20:34 +0200)] 
tests/9pfs: change qtest name prefix to synth

All existing 9pfs test cases are using the 'synth' fs driver so far, which
means they are not accessing real files, but a purely simulated (in RAM
only) file system.

Let's make this clear by changing the prefix of the individual qtest case
names from 'fs/' to 'synth/'. That way they'll be easily distinguishable
from upcoming new 9pfs test cases supposed to be using a different fs
driver.

Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Message-Id: <e04e75acb849b085c6d6320b2433a15fa935bcff.1602182956.git.qemu_oss@crudebyte.com>
Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
15 months ago9pfs: suppress performance warnings on qtest runs
Christian Schoenebeck [Mon, 19 Oct 2020 11:10:18 +0000 (13:10 +0200)] 
9pfs: suppress performance warnings on qtest runs

Don't trigger any performance warning if we're just running test cases,
because tests intentionally run for edge cases.

So far performance warnings were suppressed for the 'synth' fs driver
backend only. This patch suppresses them for all 9p fs driver backends.

Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Message-Id: <a2d2ff2163f8853ea782a7a1d4e6f2afd7c29ffe.1603106145.git.qemu_oss@crudebyte.com>
Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
15 months agoMerge remote-tracking branch 'remotes/mcayland/tags/qemu-macppc-20201019' into staging
Peter Maydell [Mon, 19 Oct 2020 10:46:03 +0000 (11:46 +0100)] 
Merge remote-tracking branch 'remotes/mcayland/tags/qemu-macppc-20201019' into staging

qemu-macppc updates

# gpg: Signature made Mon 19 Oct 2020 08:13:16 BST
# gpg:                using RSA key CC621AB98E82200D915CC9C45BC2C56FAE0F321F
# gpg:                issuer "mark.cave-ayland@ilande.co.uk"
# gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" [full]
# Primary key fingerprint: CC62 1AB9 8E82 200D 915C  C9C4 5BC2 C56F AE0F 321F

* remotes/mcayland/tags/qemu-macppc-20201019:
  mac_oldworld: Change PCI address of macio to match real hardware
  mac_oldworld: Drop some variables
  mac_oldworld: Drop a variable, use get_system_memory() directly
  mac_newworld: Allow loading binary ROM image
  mac_oldworld: Allow loading binary ROM image
  m48t59: remove legacy m48t59_init() function
  ppc405_boards: use qdev properties instead of legacy m48t59_init() function
  sun4u: use qdev properties instead of legacy m48t59_init() function
  sun4m: use qdev properties instead of legacy m48t59_init() function
  m48t59-isa: remove legacy m48t59_init_isa() function
  uninorth: use qdev gpios for PCI IRQs
  grackle: use qdev gpios for PCI IRQs
  macio: don't reference serial_hd() directly within the device

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15 months agoMerge remote-tracking branch 'remotes/philmd-gitlab/tags/mips-next-20201017' into...
Peter Maydell [Mon, 19 Oct 2020 09:52:56 +0000 (10:52 +0100)] 
Merge remote-tracking branch 'remotes/philmd-gitlab/tags/mips-next-20201017' into staging

MIPS patches queue

. Fix some comment spelling errors
. Demacro some TCG helpers
. Add loongson-ext lswc2/lsdc2 group of instructions
. Log unimplemented cache opcode
. Increase number of TLB entries on the 34Kf core
. Allow the CPU to use dynamic frequencies
. Calculate the CP0 timer period using the CPU frequency
. Set CPU frequency for each machine
. Fix Malta FPGA I/O region size
. Allow running qtests when ROM is missing
. Add record/replay acceptance tests
. Update MIPS CPU documentation
. MAINTAINERS updates

CI jobs results:
  https://gitlab.com/philmd/qemu/-/pipelines/203931842
  https://travis-ci.org/github/philmd/qemu/builds/736491461
  https://cirrus-ci.com/build/6272264062631936
  https://app.shippable.com/github/philmd/qemu/runs/886/summary/console

# gpg: Signature made Sat 17 Oct 2020 14:59:53 BST
# gpg:                using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [full]
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD  6BB2 E3E3 2C2C DEAD C0DE

* remotes/philmd-gitlab/tags/mips-next-20201017: (44 commits)
  target/mips: Increase number of TLB entries on the 34Kf core (16 -> 64)
  MAINTAINERS: Remove duplicated Malta test entries
  MAINTAINERS: Downgrade MIPS Boston to 'Odd Fixes', fix Paul Burton mail
  MAINTAINERS: Put myself forward for MIPS target
  MAINTAINERS: Remove myself
  docs/system: Update MIPS CPU documentation
  tests/acceptance: Add MIPS record/replay tests
  hw/mips: Remove exit(1) in case of missing ROM
  hw/mips: Rename TYPE_MIPS_BOSTON to TYPE_BOSTON
  hw/mips: Simplify code using ROUND_UP(INITRD_PAGE_SIZE)
  hw/mips: Simplify loading 64-bit ELF kernels
  hw/mips/malta: Use clearer qdev style
  hw/mips/malta: Move gt64120 related code together
  hw/mips/malta: Fix FPGA I/O region size
  target/mips/cpu: Display warning when CPU is used without input clock
  hw/mips/cps: Do not allow use without input clock
  hw/mips/malta: Set CPU frequency to 320 MHz
  hw/mips/boston: Set CPU frequency to 1 GHz
  hw/mips/cps: Expose input clock and connect it to CPU cores
  hw/mips/jazz: Correct CPU frequencies
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15 months agohw/usb/hcd-dwc2: fix divide-by-zero in dwc2_handle_packet()
Mauro Matteo Cascella [Thu, 15 Oct 2020 07:59:57 +0000 (09:59 +0200)] 
hw/usb/hcd-dwc2: fix divide-by-zero in dwc2_handle_packet()

Check the value of mps to avoid potential divide-by-zero later in the function.
Since HCCHAR_MPS is guest controllable, this prevents a malicious/buggy guest
from crashing the QEMU process on the host.

Signed-off-by: Mauro Matteo Cascella <mcascell@redhat.com>
Reviewed-by: Paul Zimmerman <pauldzim@gmail.com>
Reported-by: Gaoning Pan <gaoning.pgn@antgroup.com>
Reported-by: Xingwei Lin <linyi.lxw@antfin.com>
Message-id: 20201015075957.268823-1-mcascell@redhat.com
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
15 months agousb/hcd-ehci: Fix error handling on missing device for iTD
Anthony PERARD [Wed, 14 Oct 2020 10:41:06 +0000 (11:41 +0100)] 
usb/hcd-ehci: Fix error handling on missing device for iTD

The EHCI Host Controller emulation attempt to locate the device
associated with a periodic isochronous transfer description (iTD) and
when this fail the host controller is reset.

But according the EHCI spec 1.0 section 5.15.2.4 Host System
Error, the host controller is supposed to reset itself only when it
failed to communicate with the Host (Operating System), like when
there's an error on the PCI bus. If a transaction fails, there's
nothing in the spec that say to reset the host controller.

This patch rework the error path so that the host controller can keep
working when the OS setup a bogus transaction, it also revert to the
behavior of the EHCI emulation to before commits:
e94682f1fe ("ehci: check device is not NULL before calling usb_ep_get()")
7011baece2 ("usb: remove unnecessary NULL device check from usb_ep_get()")

The issue has been found while trying to passthrough a USB device to a
Windows Server 2012 Xen guest via "usb-ehci", which prevent the USB
device from working in Windows. ("usb-ehci" alone works, windows only
setup this weird periodic iTD to device 127 endpoint 15 when the USB
device is passthrough.)

Signed-off-by: Anthony PERARD <anthony.perard@citrix.com>
Message-id: 20201014104106.2962640-1-anthony.perard@citrix.com
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
15 months agousb: hcd-dwc2: change assert()s to qemu_log_mask(LOG_GUEST_ERROR...)
Paul Zimmerman [Sun, 20 Sep 2020 02:14:49 +0000 (19:14 -0700)] 
usb: hcd-dwc2: change assert()s to qemu_log_mask(LOG_GUEST_ERROR...)

Change several assert()s to qemu_log_mask(LOG_GUEST_ERROR...),
to prevent the guest from causing Qemu to assert. Also fix up
several existing qemu_log_mask()s to include the function name in
the message.

Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Paul Zimmerman <pauldzim@gmail.com>
Message-id: 20200920021449.830-1-pauldzim@gmail.com
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
15 months agomac_oldworld: Change PCI address of macio to match real hardware
BALATON Zoltan [Thu, 15 Oct 2020 23:47:17 +0000 (01:47 +0200)] 
mac_oldworld: Change PCI address of macio to match real hardware

The board firmware expect these to be at fixed addresses and programs
them without probing, this patch puts the macio device at the expected
PCI address.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <f14bcaf3cf129500710ba5289980a134086bd949.1602805637.git.balaton@eik.bme.hu>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
15 months agomac_oldworld: Drop some variables
BALATON Zoltan [Thu, 15 Oct 2020 23:47:17 +0000 (01:47 +0200)] 
mac_oldworld: Drop some variables

Values not used frequently enough may not worth putting in a local
variable, especially with names almost as long as the original value
because that does not improve readability, to the contrary it makes it
harder to see what value is used. Drop a few such variables.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <d67bc8d914a366ca6822b5190c1308d31af5c9b3.1602805637.git.balaton@eik.bme.hu>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
15 months agomac_oldworld: Drop a variable, use get_system_memory() directly
BALATON Zoltan [Thu, 15 Oct 2020 23:47:17 +0000 (01:47 +0200)] 
mac_oldworld: Drop a variable, use get_system_memory() directly

Half of the occurances already use get_system_memory() directly
instead of sysmem variable, convert the two other uses to
get_system_memory() too which seems to be more common and drop the
variable.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <b4c714e03690deb6f94f80f7a5b2af47d90550ae.1602805637.git.balaton@eik.bme.hu>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
15 months agomac_newworld: Allow loading binary ROM image
BALATON Zoltan [Thu, 15 Oct 2020 23:47:17 +0000 (01:47 +0200)] 
mac_newworld: Allow loading binary ROM image

Fall back to load binary ROM image if loading ELF fails. This also
moves PROM_BASE and PROM_SIZE defines to board as these are matching
the ROM size and address on this board and removes the now unused
PROM_ADDR and BIOS_SIZE defines from common mac.h.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <4d58ffe7645a0c746c8fed6aa8775c0867b624e0.1602805637.git.balaton@eik.bme.hu>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
15 months agomac_oldworld: Allow loading binary ROM image
BALATON Zoltan [Sat, 17 Oct 2020 15:47:29 +0000 (17:47 +0200)] 
mac_oldworld: Allow loading binary ROM image

The beige G3 Power Macintosh has a 4MB firmware ROM. Fix the size of
the rom region and fall back to loading a binary image with -bios if
loading ELF image failed. This allows testing emulation with a ROM
image from real hardware as well as using an ELF OpenBIOS image.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20201017155139.5A36A746331@zero.eik.bme.hu>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
15 months agom48t59: remove legacy m48t59_init() function
Mark Cave-Ayland [Fri, 16 Oct 2020 18:27:39 +0000 (19:27 +0100)] 
m48t59: remove legacy m48t59_init() function

Now that all of the callers of this function have been switched to use qdev
properties, this legacy init function can now be removed.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20201016182739.22875-6-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Hervé Poussineau <hpoussin@reactos.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
15 months agoppc405_boards: use qdev properties instead of legacy m48t59_init() function
Mark Cave-Ayland [Fri, 16 Oct 2020 18:27:38 +0000 (19:27 +0100)] 
ppc405_boards: use qdev properties instead of legacy m48t59_init() function

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20201016182739.22875-5-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Hervé Poussineau <hpoussin@reactos.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
15 months agosun4u: use qdev properties instead of legacy m48t59_init() function
Mark Cave-Ayland [Fri, 16 Oct 2020 18:27:37 +0000 (19:27 +0100)] 
sun4u: use qdev properties instead of legacy m48t59_init() function

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20201016182739.22875-4-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Hervé Poussineau <hpoussin@reactos.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
15 months agosun4m: use qdev properties instead of legacy m48t59_init() function
Mark Cave-Ayland [Fri, 16 Oct 2020 18:27:36 +0000 (19:27 +0100)] 
sun4m: use qdev properties instead of legacy m48t59_init() function

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20201016182739.22875-3-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Hervé Poussineau <hpoussin@reactos.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
15 months agom48t59-isa: remove legacy m48t59_init_isa() function
Mark Cave-Ayland [Fri, 16 Oct 2020 18:27:35 +0000 (19:27 +0100)] 
m48t59-isa: remove legacy m48t59_init_isa() function

This function is no longer used within the codebase.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20201016182739.22875-2-mark.cave-ayland@ilande.co.uk>
Reviewed-by: Hervé Poussineau <hpoussin@reactos.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
15 months agouninorth: use qdev gpios for PCI IRQs
Mark Cave-Ayland [Tue, 13 Oct 2020 11:49:22 +0000 (12:49 +0100)] 
uninorth: use qdev gpios for PCI IRQs

Currently an object link property is used to pass a reference to the OpenPIC
into the PCI host bridge so that pci_unin_init_irqs() can connect the PCI
IRQs to the PIC itself.

This can be simplified by defining the PCI IRQs as qdev gpios and then wiring
up the PCI IRQs to the PIC in the New World machine init function.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201013114922.2946-4-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
15 months agograckle: use qdev gpios for PCI IRQs
Mark Cave-Ayland [Tue, 13 Oct 2020 11:49:21 +0000 (12:49 +0100)] 
grackle: use qdev gpios for PCI IRQs

Currently an object link property is used to pass a reference to the Heathrow
PIC into the PCI host bridge so that grackle_init_irqs() can connect the PCI
IRQs to the PIC itself.

This can be simplified by defining the PCI IRQs as qdev gpios and then wiring
up the PCI IRQs to the PIC in the Old World machine init function.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201013114922.2946-3-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
15 months agomacio: don't reference serial_hd() directly within the device
Mark Cave-Ayland [Tue, 13 Oct 2020 11:49:20 +0000 (12:49 +0100)] 
macio: don't reference serial_hd() directly within the device

Instead use qdev_prop_set_chr() to configure the ESCC serial chardevs at the
Mac Old World and New World machine level.

Also remove the now obsolete comment referring to the use of serial_hd() and
the setting of user_creatable to false accordingly.

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20201013114922.2946-2-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
15 months agoMerge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging
Peter Maydell [Sat, 17 Oct 2020 19:52:55 +0000 (20:52 +0100)] 
Merge remote-tracking branch 'remotes/bonzini-gitlab/tags/for-upstream' into staging

* Drop ninjatool and just require ninja (Paolo)
* Fix docs build under msys2 (Yonggang)
* HAX snafu fix (Claudio)
* Disable signal handlers during fuzzing (Alex)
* Miscellaneous fixes (Bruce, Greg)

# gpg: Signature made Sat 17 Oct 2020 15:45:56 BST
# gpg:                using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg:                issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg:                 aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4  E2F7 7E15 100C CD36 69B1
#      Subkey fingerprint: F133 3857 4B66 2389 866C  7682 BFFB D25F 78C7 AE83

* remotes/bonzini-gitlab/tags/for-upstream: (22 commits)
  ci: include configure and meson logs in all jobs if configure fails
  hax: unbreak accelerator cpu code after cpus.c split
  fuzz: Disable QEMU's SIG{INT,HUP,TERM} handlers
  cirrus: Enable doc build on msys2/mingw
  meson: Move the detection logic for sphinx to meson
  meson: move SPHINX_ARGS references within "if build_docs"
  docs: Fix Sphinx configuration for msys2/mingw
  meson: Only install icons and qemu.desktop if have_system
  configure: fix handling of --docdir parameter
  meson: cleanup curses/iconv test
  meson.build: don't condition iconv detection on library detection
  build: add --enable/--disable-libudev
  build: replace ninjatool with ninja
  build: cleanups to Makefile
  add ninja to dockerfiles, CI configurations and test VMs
  dockerfiles: enable Centos 8 PowerTools
  configure: move QEMU_INCLUDES to meson
  tests: add missing generated sources to testqapi
  make: run shell with pipefail
  tests/Makefile.include: unbreak non-tcg builds
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
15 months agoci: include configure and meson logs in all jobs if configure fails
Paolo Bonzini [Fri, 16 Oct 2020 09:49:28 +0000 (05:49 -0400)] 
ci: include configure and meson logs in all jobs if configure fails

Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
15 months agohax: unbreak accelerator cpu code after cpus.c split
Claudio Fontana [Fri, 16 Oct 2020 08:00:32 +0000 (10:00 +0200)] 
hax: unbreak accelerator cpu code after cpus.c split

during my split of cpus.c, code line
"current_cpu = cpu"
was removed by mistake, causing hax to break.

This commit fixes the situation restoring it.

Reported-by: Volker Rümelin <vr_qemu@t-online.de>
Fixes: e92558e4bf8059ce4f0b310afe218802b72766bc
Signed-off-by: Claudio Fontana <cfontana@suse.de>
Message-Id: <20201016080032.13914-1-cfontana@suse.de>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
15 months agofuzz: Disable QEMU's SIG{INT,HUP,TERM} handlers
Alexander Bulekov [Wed, 14 Oct 2020 14:21:57 +0000 (10:21 -0400)] 
fuzz: Disable QEMU's SIG{INT,HUP,TERM} handlers

Prior to this patch, the only way I found to terminate the fuzzer was
either to:
 1. Explicitly specify the number of fuzzer runs with the -runs= flag
 2. SIGKILL the process with "pkill -9 qemu-fuzz-*" or similar

In addition to being annoying to deal with, SIGKILLing the process skips
over any exit handlers(e.g. registered with atexit()). This is bad,
since some fuzzers might create temporary files that should ideally be
removed on exit using an exit handler. The only way to achieve a clean
exit now is to specify -runs=N , but the desired "N" is tricky to
identify prior to fuzzing.

Why doesn't the process exit with standard SIGINT,SIGHUP,SIGTERM
signals? QEMU installs its own handlers for these signals in
os-posix.c:os_setup_signal_handling, which notify the main loop that an
exit was requested. The fuzzer, however, does not run qemu_main_loop,
which performs the main_loop_should_exit() check.  This means that the
fuzzer effectively ignores these signals. As we don't really care about
cleanly stopping the disposable fuzzer "VM", this patch uninstalls
QEMU's signal handlers. Thus, we can stop the fuzzer with
SIG{INT,HUP,TERM} and the fuzzing code can optionally use atexit() to
clean up temporary files/resources.

Reviewed-by: Darren Kenny <darren.kenny@oracle.com>
Signed-off-by: Alexander Bulekov <alxndr@bu.edu>
Message-Id: <20201014142157.46028-1-alxndr@bu.edu>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
15 months agocirrus: Enable doc build on msys2/mingw
Yonggang Luo [Thu, 15 Oct 2020 22:06:26 +0000 (06:06 +0800)] 
cirrus: Enable doc build on msys2/mingw

Currently rST depends on old version sphinx-2.x.
Install it by downloading it.
Remove the need of university mirror, the main repo are recovered.

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Message-Id: <20201015220626.418-5-luoyonggang@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
15 months agomeson: Move the detection logic for sphinx to meson
Yonggang Luo [Thu, 15 Oct 2020 22:06:25 +0000 (06:06 +0800)] 
meson: Move the detection logic for sphinx to meson

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Message-Id: <20201015220626.418-4-luoyonggang@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
15 months agomeson: move SPHINX_ARGS references within "if build_docs"
Paolo Bonzini [Fri, 16 Oct 2020 08:05:26 +0000 (04:05 -0400)] 
meson: move SPHINX_ARGS references within "if build_docs"

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
15 months agodocs: Fix Sphinx configuration for msys2/mingw
Yonggang Luo [Thu, 15 Oct 2020 22:06:23 +0000 (06:06 +0800)] 
docs: Fix Sphinx configuration for msys2/mingw

Python doesn't support running ../scripts/kernel-doc directly.

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Message-Id: <20201015220626.418-2-luoyonggang@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
15 months agomeson: Only install icons and qemu.desktop if have_system
Bruce Rogers [Thu, 15 Oct 2020 20:18:40 +0000 (14:18 -0600)] 
meson: Only install icons and qemu.desktop if have_system

These files are not needed for a linux-user only install.

Signed-off-by: Bruce Rogers <brogers@suse.com>
Message-Id: <20201015201840.282956-1-brogers@suse.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
15 months agoconfigure: fix handling of --docdir parameter
Bruce Rogers [Thu, 15 Oct 2020 19:07:42 +0000 (13:07 -0600)] 
configure: fix handling of --docdir parameter

Commit ca8c0909f01 changed qemu_docdir to be docdir, then later uses the
qemu_docdir name in the final assignment. Unfortunately, one instance of
qemu_docdir was missed: the one which comes from the --docdir parameter.
This patch restores the proper handling of the --docdir parameter.

Fixes: ca8c0909f01 ("configure: build docdir like other suffixed
directories")

Signed-off-by: Bruce Rogers <brogers@suse.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20201015190742.270629-1-brogers@suse.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
15 months agomeson: cleanup curses/iconv test
Paolo Bonzini [Thu, 15 Oct 2020 17:26:50 +0000 (13:26 -0400)] 
meson: cleanup curses/iconv test

Skip the test if it is system emulation is not requested, and
differentiate errors for lack of iconv and lack of curses.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
15 months agomeson.build: don't condition iconv detection on library detection
Bruce Rogers [Wed, 14 Oct 2020 22:19:39 +0000 (16:19 -0600)] 
meson.build: don't condition iconv detection on library detection

It isn't necessarily the case that use of iconv requires an additional
library. For that reason we shouldn't conditionalize iconv detection on
libiconv.found.

Fixes: 5285e593c33 (configure: Fixes ncursesw detection under msys2/mingw by convert them to meson)

Signed-off-by: Bruce Rogers <brogers@suse.com>
Reviewed-by: Yonggang Luo<l <brogers@suse.com>uoyonggang@gmail.com>
Reviewed-by:Yonggang Luo <luoyonggang@gmail.com>
Message-Id: <20201014221939.196958-1-brogers@suse.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
15 months agobuild: add --enable/--disable-libudev
Paolo Bonzini [Thu, 15 Oct 2020 10:09:27 +0000 (06:09 -0400)] 
build: add --enable/--disable-libudev

Initially, libudev detection was bundled with --enable-mpath because
qemu-pr-helper was the only user of libudev.  Recently however the USB
U2F emulation has also started using libudev, so add a separate
option.  This also allows 1) disabling libudev if desired for static
builds and 2) for non-static builds, requiring libudev even if
multipath support is undesirable.

The multipath test is adjusted, because it is now possible to enter it
with configurations that should fail, such as --static --enable-mpath
--disable-libudev.

Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
15 months agobuild: replace ninjatool with ninja
Paolo Bonzini [Thu, 13 Aug 2020 13:28:11 +0000 (09:28 -0400)] 
build: replace ninjatool with ninja

Now that the build is done entirely by Meson, there is no need
to keep the Makefile conversion.  Instead, we can ask Ninja about
the targets it exposes and forward them.

The main advantages are, from smallest to largest:

- reducing the possible namespace pollution within the Makefile

- removal of a relatively large Python program

- faster build because parsing Makefile.ninja is slower than
parsing build.ninja; and faster build after Meson runs because
we do not have to generate Makefile.ninja.

- tracking of command lines, which provides more accurate rebuilds

In addition the change removes the requirement for GNU make 3.82, which
was annoying on Mac, and avoids bugs on Windows due to ninjatool not
knowing how to convert Windows escapes to POSIX escapes.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
15 months agobuild: cleanups to Makefile
Paolo Bonzini [Thu, 15 Oct 2020 16:20:02 +0000 (12:20 -0400)] 
build: cleanups to Makefile

Group similar rules, add comments to "else" and "endif" lines,
detect too-old config-host.mak before messing things up.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
15 months agoadd ninja to dockerfiles, CI configurations and test VMs
Paolo Bonzini [Thu, 13 Aug 2020 13:58:50 +0000 (09:58 -0400)] 
add ninja to dockerfiles, CI configurations and test VMs

Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
15 months agodockerfiles: enable Centos 8 PowerTools
Paolo Bonzini [Wed, 14 Oct 2020 11:12:37 +0000 (07:12 -0400)] 
dockerfiles: enable Centos 8 PowerTools

ninja is included in the CentOS PowerTools repository.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
15 months agoconfigure: move QEMU_INCLUDES to meson
Paolo Bonzini [Wed, 14 Oct 2020 12:45:42 +0000 (08:45 -0400)] 
configure: move QEMU_INCLUDES to meson

Confusingly, QEMU_INCLUDES is not used by configure tests.  Moving
it to meson.build ensures that Windows paths are specified instead of
the msys paths like /c/Users/...

Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
15 months agotests: add missing generated sources to testqapi
Paolo Bonzini [Wed, 14 Oct 2020 11:20:17 +0000 (07:20 -0400)] 
tests: add missing generated sources to testqapi

Ninja notices them due to a different order in visiting the graph.

Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
15 months agomake: run shell with pipefail
Paolo Bonzini [Wed, 14 Oct 2020 11:35:13 +0000 (07:35 -0400)] 
make: run shell with pipefail

Without pipefail, it is possible to miss failures if the recipes
include pipes.

Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
15 months agotests/Makefile.include: unbreak non-tcg builds
Paolo Bonzini [Tue, 13 Oct 2020 19:21:21 +0000 (21:21 +0200)] 
tests/Makefile.include: unbreak non-tcg builds

Remove from check-block the requirement that all TARGET_DIRS are built.

Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
15 months agoMakefile: Ensure cscope.out/tags/TAGS are generated in the source tree
Greg Kurz [Thu, 15 Oct 2020 14:49:06 +0000 (16:49 +0200)] 
Makefile: Ensure cscope.out/tags/TAGS are generated in the source tree

Tools usually expect the index files to be in the source tree, eg. emacs.
This is already the case when doing out-of-tree builds, but with in-tree
builds they end up in the build directory.

Force cscope, ctags and etags to put them in the source tree.

Signed-off-by: Greg Kurz <groug@kaod.org>
Message-Id: <160277334665.1754102.10921580280105870386.stgit@bahia.lan>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
15 months agosubmodules: bump meson to 0.55.3
Paolo Bonzini [Thu, 15 Oct 2020 07:20:45 +0000 (03:20 -0400)] 
submodules: bump meson to 0.55.3

This adds some bugfixes, and allows MSYS2 to configure
without "--ninja=ninja".

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
15 months agotarget/mips: Increase number of TLB entries on the 34Kf core (16 -> 64)
Philippe Mathieu-Daudé [Fri, 16 Oct 2020 13:20:37 +0000 (15:20 +0200)] 
target/mips: Increase number of TLB entries on the 34Kf core (16 -> 64)

Per "MIPS32 34K Processor Core Family Software User's Manual,
Revision 01.13" page 8 in "Joint TLB (JTLB)" section:

  "The JTLB is a fully associative TLB cache containing 16, 32,
   or 64-dual-entries mapping up to 128 virtual pages to their
   corresponding physical addresses."

There is no particular reason to restrict the 34Kf core model to
16 TLB entries, so raise its config to 64.

This is helpful for other projects, in particular the Yocto Project:

  Yocto Project uses qemu-system-mips 34Kf cpu model, to run 32bit
  MIPS CI loop. It was observed that in this case CI test execution
  time was almost twice longer than 64bit MIPS variant that runs
  under MIPS64R2-generic model. It was investigated and concluded
  that the difference in number of TLBs 16 in 34Kf case vs 64 in
  MIPS64R2-generic is responsible for most of CI real time execution
  difference. Because with 16 TLBs linux user-land trashes TLB more
  and it needs to execute more instructions in TLB refill handler
  calls, as result it runs much longer.

(https://lists.gnu.org/archive/html/qemu-devel/2020-10/msg03428.html)

Buglink: https://bugzilla.yoctoproject.org/show_bug.cgi?id=13992
Reported-by: Victor Kamensky <kamensky@cisco.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20201016133317.553068-1-f4bug@amsat.org>

15 months agoMAINTAINERS: Remove duplicated Malta test entries
Philippe Mathieu-Daudé [Fri, 9 Oct 2020 15:11:00 +0000 (17:11 +0200)] 
MAINTAINERS: Remove duplicated Malta test entries

The Malta tests are already covered in the Malta section.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20201013101659.3557154-3-f4bug@amsat.org>

15 months agoMAINTAINERS: Downgrade MIPS Boston to 'Odd Fixes', fix Paul Burton mail
Philippe Mathieu-Daudé [Fri, 9 Oct 2020 16:15:59 +0000 (18:15 +0200)] 
MAINTAINERS: Downgrade MIPS Boston to 'Odd Fixes', fix Paul Burton mail

Paul's Wavecomp email has been bouncing for months. He told us
he "no longer has access to modern MIPS CPUs or Boston hardware,
and wouldn't currently have time to spend on them if he did." [1]
but "perhaps that might change in the future." [2].
Be fair and downgrade the status of the Boston board to "Odd Fixes"
(has a maintainer but they don't have time to do much other).
Similarly to commit 2b107c2c1c (".mailmap: Update Paul Burton email
address"), update his email address here too.

[1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg718739.html
[2] https://www.mail-archive.com/qemu-devel@nongnu.org/msg728605.html

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20201013101659.3557154-4-f4bug@amsat.org>

15 months agoMAINTAINERS: Put myself forward for MIPS target
Philippe Mathieu-Daudé [Fri, 9 Oct 2020 15:05:13 +0000 (17:05 +0200)] 
MAINTAINERS: Put myself forward for MIPS target

To avoid the MIPS target being orphan, volunteer to keep an eye
on it and put together pull requests.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20201013101659.3557154-2-f4bug@amsat.org>

15 months agoMAINTAINERS: Remove myself
Aleksandar Markovic [Wed, 7 Oct 2020 20:37:21 +0000 (22:37 +0200)] 
MAINTAINERS: Remove myself

I have been working on project other than QEMU for some time, and would
like to devote myself to that project. It is impossible for me to find
enough time to perform maintainer's duties with needed meticulousness
and patience.

I wish prosperous future to QEMU and all colleagues in QEMU community.

Signed-off-by: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
Message-Id: <1602103041-32017-6-git-send-email-aleksandar.qemu.devel@gmail.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15 months agodocs/system: Update MIPS CPU documentation
Huacai Chen [Wed, 7 Oct 2020 08:39:35 +0000 (16:39 +0800)] 
docs/system: Update MIPS CPU documentation

Add Loongson-3A CPU models description.

Signed-off-by: Huacai Chen <chenhc@lemote.com>
Message-Id: <1602059975-10115-10-git-send-email-chenhc@lemote.com>
[PMD: Split patch in 2: CPU / machine]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15 months agotests/acceptance: Add MIPS record/replay tests
Pavel Dovgalyuk [Thu, 15 Oct 2020 11:25:02 +0000 (14:25 +0300)] 
tests/acceptance: Add MIPS record/replay tests

This patch adds MIPS-targeted acceptance tests for
record/replay functions.

Signed-off-by: Pavel Dovgalyuk <pavel.dovgalyuk@ispras.ru>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <160276110297.2705.10918105269658307206.stgit@pasha-ThinkPad-X280>
[PMD: Moved 'override timeout' comment from instance to class,
      moved nanomips tests to ReplayKernelSlow class,
      tagged ReplayKernelSlow class with AVOCADO_TIMEOUT_EXPECTED]
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15 months agohw/mips: Remove exit(1) in case of missing ROM
Pavel Dovgalyuk [Tue, 21 Jul 2020 06:15:05 +0000 (09:15 +0300)] 
hw/mips: Remove exit(1) in case of missing ROM

This patch updates MIPS-based machines to allow starting them without ROM.
In this case CPU starts to execute instructions from the empty memory,
but QEMU allows introspecting the machine configuration.

Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <159531210571.24117.231100997794891819.stgit@pasha-ThinkPad-X280>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15 months agohw/mips: Rename TYPE_MIPS_BOSTON to TYPE_BOSTON
Eduardo Habkost [Wed, 2 Sep 2020 22:42:26 +0000 (18:42 -0400)] 
hw/mips: Rename TYPE_MIPS_BOSTON to TYPE_BOSTON

This will make the type name constant consistent with the name of
the type checking macro.

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20200902224311.1321159-19-ehabkost@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
15 months agohw/mips: Simplify code using ROUND_UP(INITRD_PAGE_SIZE)
Philippe Mathieu-Daudé [Sun, 27 Sep 2020 11:18:17 +0000 (13:18 +0200)] 
hw/mips: Simplify code using ROUND_UP(INITRD_PAGE_SIZE)

Instead of using a INITRD_PAGE_MASK definition, use the
simpler INITRD_PAGE_SIZE one which allows us to simplify
the code by using directly the self-explicit ROUND_UP()
macro.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200927163943.614604-3-f4bug@amsat.org>

15 months agohw/mips: Simplify loading 64-bit ELF kernels
Philippe Mathieu-Daudé [Sun, 27 Sep 2020 12:21:11 +0000 (14:21 +0200)] 
hw/mips: Simplify loading 64-bit ELF kernels

Since 82790064116 ("Cast ELF datatypes properly to host 64bit types")
we don't need to sign-extend the entry_point address. Remove this
unnecessary code.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200927163943.614604-2-f4bug@amsat.org>