qemu.git
22 months agohw/arm/nseries: Replace the bluetooth chardev with a "null" chardev
Thomas Huth [Wed, 20 Nov 2019 09:10:11 +0000 (10:10 +0100)] 
hw/arm/nseries: Replace the bluetooth chardev with a "null" chardev

We are going to remove the bitrotten bluetooth backend, so we can
not use it in the n800 and n810 machines anymore. Replace the chardev
here with a "null" chardev and stop including the "hw/bt.h" header.

I am not aware of a full working N8x0 environment that can be used to
test these machines, but the Linux kernel from the Meego project that
can be found on http://stskeeps.subnetmask.net/meego-n8x0/ still seems
to boot as far as it did before.

Message-Id: <20191120091014.16883-2-thuth@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
22 months agoMerge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-dec-16-2019' into...
Peter Maydell [Mon, 16 Dec 2019 14:07:56 +0000 (14:07 +0000)] 
Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-dec-16-2019' into staging

MIPS queue for December 16th, 2019

# gpg: Signature made Mon 16 Dec 2019 12:29:24 GMT
# gpg:                using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [full]
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01  DD75 D497 2A89 67F7 5A65

* remotes/amarkovic/tags/mips-queue-dec-16-2019:
  MAINTAINERS: Add a file to MIPS section
  MAINTAINERS: Add three files to Malta section
  MAINTAINERS: Adjust maintainership for Malta board
  MAINTAINERS: Adjust maintainership for Fulong 2E board
  MAINTAINERS: Add a section on UI translation
  hw/mips: Deprecate the r4k machine
  mips: fulong 2e: Renovate coding style
  mips: r4000: Renovate coding style
  mips: mipssim: Renovate coding style
  mips: malta: Renovate coding style
  mips: jazz: Renovate coding style

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agoMerge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20191216-1' into...
Peter Maydell [Mon, 16 Dec 2019 13:04:33 +0000 (13:04 +0000)] 
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20191216-1' into staging

target-arm queue:
 * Add support for Cortex-M7 CPU
 * exynos4210_gic: Suppress gcc9 format-truncation warnings
 * aspeed: Various minor bug fixes and improvements
 * aspeed: Add support for the tacoma-bmc board
 * Honour HCR_EL32.TID1 and .TID2 trapping requirements
 * Handle trapping to EL2 of AArch32 VMRS instructions
 * Handle AArch32 CP15 trapping via HSTR_EL2
 * Add support for missing Jazelle system registers
 * arm/arm-powerctl: set NSACR.{CP11, CP10} bits in arm_set_cpu_on
 * Add support for DC CVAP & DC CVADP instructions
 * Fix assertion when SCR.NS is changed in Secure-SVC &c
 * enable SHPC native hot plug in arm ACPI

# gpg: Signature made Mon 16 Dec 2019 11:08:07 GMT
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20191216-1: (34 commits)
  target/arm: ensure we use current exception state after SCR update
  hw/arm/virt: Simplify by moving the gic in the machine state
  hw/arm/acpi: enable SHPC native hot plug
  hw/arm/acpi: simplify AML bit and/or statement
  hw/arm/sbsa-ref: Simplify by moving the gic in the machine state
  target/arm: Add support for DC CVAP & DC CVADP ins
  migration: ram: Switch to ram block writeback
  Memory: Enable writeback for given memory region
  tcg: cputlb: Add probe_read
  arm/arm-powerctl: set NSACR.{CP11, CP10} bits in arm_set_cpu_on()
  target/arm: Add support for missing Jazelle system registers
  target/arm: Handle AArch32 CP15 trapping via HSTR_EL2
  target/arm: Handle trapping to EL2 of AArch32 VMRS instructions
  target/arm: Honor HCR_EL2.TID1 trapping requirements
  target/arm: Honor HCR_EL2.TID2 trapping requirements
  aspeed: Change the "nic" property definition
  aspeed: Change the "scu" property definition
  gpio: fix memory leak in aspeed_gpio_init()
  aspeed: Add support for the tacoma-bmc board
  aspeed: Remove AspeedBoardConfig array and use AspeedMachineClass
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agoMAINTAINERS: Add a file to MIPS section
Aleksandar Markovic [Tue, 10 Dec 2019 12:55:19 +0000 (13:55 +0100)] 
MAINTAINERS: Add a file to MIPS section

File tests/acceptance/linux_ssh_mips_malta.py is crucial for
entire MIPS platform, so add it to the MIPS section. The
maintainership will be shared with others.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1575982519-29852-6-git-send-email-aleksandar.markovic@rt-rk.com>

22 months agoMAINTAINERS: Add three files to Malta section
Aleksandar Markovic [Tue, 10 Dec 2019 12:55:18 +0000 (13:55 +0100)] 
MAINTAINERS: Add three files to Malta section

Add three files that were recently introduced in a refactoring,
that Malta emulation relies on. They are added by this patch
to Malta section, but they are not added to the general MIPS
section, since they are really not MIPS-specific, and there
may be some non-MIPS hardware using them in future.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1575982519-29852-5-git-send-email-aleksandar.markovic@rt-rk.com>

22 months agoMAINTAINERS: Adjust maintainership for Malta board
Aleksandar Markovic [Tue, 10 Dec 2019 12:55:17 +0000 (13:55 +0100)] 
MAINTAINERS: Adjust maintainership for Malta board

Change the maintainership for Malta board to improve its quality.

Acked-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1575982519-29852-4-git-send-email-aleksandar.markovic@rt-rk.com>

22 months agoMAINTAINERS: Adjust maintainership for Fulong 2E board
Aleksandar Markovic [Tue, 10 Dec 2019 12:55:16 +0000 (13:55 +0100)] 
MAINTAINERS: Adjust maintainership for Fulong 2E board

Change the maintainership for Fulong 2E board to improve its quality.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Acked-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1575982519-29852-3-git-send-email-aleksandar.markovic@rt-rk.com>

22 months agoMAINTAINERS: Add a section on UI translation
Aleksandar Markovic [Tue, 10 Dec 2019 12:55:15 +0000 (13:55 +0100)] 
MAINTAINERS: Add a section on UI translation

There should be a person who will quickly evaluate new UI
translation, and find a way to update existing ones should
something changes in UI.

Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1575982519-29852-2-git-send-email-aleksandar.markovic@rt-rk.com>

22 months agohw/mips: Deprecate the r4k machine
Philippe Mathieu-Daudé [Mon, 25 Nov 2019 10:41:03 +0000 (11:41 +0100)] 
hw/mips: Deprecate the r4k machine

The r4k machine was introduced in 2005 (6af0bf9c7) and its last
logical change was in 2005 (9542611a6). After that, one can
count 164 maintenance commits (QEMU API changes) with the
exception of 1 fix in 2015 (memory leak, commit 3ad9fd5a).

This machine was introduced as a proof of concept to run a MIPS
CPU. Two years later, the Malta machine was added (commit
5856de80), modeling a real platform.

Note also this machine has no specification except 5 lines in
the header of this file:

 * emulates a simple machine with ISA-like bus.
 * ISA IO space mapped to the 0x14000000 (PHYS) and
 * ISA memory at the 0x10000000 (PHYS, 16Mb in size).
 * All peripherial devices are attached to this "bus" with
 * the standard PC ISA addresses.

The Linux kernel support for this machine has been dropped more
than 10 years ago in commit 302922e5.

It is time to deprecate this obsolete machine. Users are
recommended to use the Malta board, and its hardware is well
documented.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Acked-by: Aurelien Jarno <aurelien@aurel32.net>
Message-Id: <20191125104103.28962-1-philmd@redhat.com>

22 months agomips: fulong 2e: Renovate coding style
Filip Bozuta [Fri, 6 Dec 2019 13:58:07 +0000 (14:58 +0100)] 
mips: fulong 2e: Renovate coding style

The script checkpatch.pl located in scripts folder was
used to detect all errors and warrnings in files:
    hw/mips/mips_fulong2e.c
    hw/isa/vt82c686.c
    hw/pci-host/bonito.c
    include/hw/isa/vt82c686.h

These mips Fulong 2E machine files were edited and
all the errors and warrings generated by the checkpatch.pl
script were corrected and then the script was
ran again to make sure there are no more errors and warnings.

Signed-off-by: Filip Bozuta <Filip.Bozuta@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1575640687-20744-6-git-send-email-Filip.Bozuta@rt-rk.com>

22 months agomips: r4000: Renovate coding style
Filip Bozuta [Fri, 6 Dec 2019 13:58:06 +0000 (14:58 +0100)] 
mips: r4000: Renovate coding style

The script checkpatch.pl located in scripts folder was
used to detect all errors and warrnings in file:
    hw/mips/mips_r4k.c

This mips r4000 machine file was edited and
all the errors and warrings generated by the checkpatch.pl
script were corrected and then the script was
ran again to make sure there are no more errors and warnings.

Signed-off-by: Filip Bozuta <Filip.Bozuta@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1575640687-20744-5-git-send-email-Filip.Bozuta@rt-rk.com>

22 months agomips: mipssim: Renovate coding style
Filip Bozuta [Fri, 6 Dec 2019 13:58:05 +0000 (14:58 +0100)] 
mips: mipssim: Renovate coding style

The script checkpatch.pl located in scripts folder was
used to detect all errors and warrnings in files:
    hw/mips/mips_mipssim.c
    hw/net/mipsnet.c

All these mips mipssim machine files were edited and
all the errors and warrings generated by the checkpatch.pl
script were corrected and then the script was
ran again to make sure there are no more errors and warnings.

Signed-off-by: Filip Bozuta <Filip.Bozuta@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1575640687-20744-4-git-send-email-Filip.Bozuta@rt-rk.com>

22 months agomips: malta: Renovate coding style
Filip Bozuta [Fri, 6 Dec 2019 13:58:04 +0000 (14:58 +0100)] 
mips: malta: Renovate coding style

The script checkpatch.pl located in scripts folder was
used to detect all errors and warrnings in files:
    hw/mips/mips_malta.c
    hw/mips/gt64xxx_pci.c
    tests/acceptance/linux_ssh_mips_malta.py

All these mips malta machine files were edited and
all the errors and warrings generated by the checkpatch.pl
script were corrected and then the script was
ran again to make sure there are no more errors and warnings.

Signed-off-by: Filip Bozuta <Filip.Bozuta@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1575640687-20744-3-git-send-email-Filip.Bozuta@rt-rk.com>

22 months agomips: jazz: Renovate coding style
Filip Bozuta [Fri, 6 Dec 2019 13:58:03 +0000 (14:58 +0100)] 
mips: jazz: Renovate coding style

The script checkpatch.pl located in scripts folder was
used to detect all errors and warrnings in files:
    hw/mips/mips_jazz.c
    hw/display/jazz_led.c
    hw/dma/rc4030.c

All these mips jazz machine files were edited and
all the errors and warrings generated by the checkpatch.pl
script were corrected and then the script was
ran again to make sure there are no more errors and warnings.

Signed-off-by: Filip Bozuta <Filip.Bozuta@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1575640687-20744-2-git-send-email-Filip.Bozuta@rt-rk.com>

22 months agotarget/arm: ensure we use current exception state after SCR update
Alex Bennée [Thu, 12 Dec 2019 11:47:34 +0000 (11:47 +0000)] 
target/arm: ensure we use current exception state after SCR update

A write to the SCR can change the effective EL by droppping the system
from secure to non-secure mode. However if we use a cached current_el
from before the change we'll rebuild the flags incorrectly. To fix
this we introduce the ARM_CP_NEWEL CP flag to indicate the new EL
should be used when recomputing the flags.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20191212114734.6962-1-alex.bennee@linaro.org
Cc: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20191209143723.6368-1-alex.bennee@linaro.org>
Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agohw/arm/virt: Simplify by moving the gic in the machine state
Philippe Mathieu-Daudé [Mon, 9 Dec 2019 09:03:06 +0000 (10:03 +0100)] 
hw/arm/virt: Simplify by moving the gic in the machine state

Make the gic a field in the machine state, and instead of filling
an array of qemu_irq and passing it around, directly call
qdev_get_gpio_in() on the gic field.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Message-id: 20191209090306.20433-1-philmd@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agohw/arm/acpi: enable SHPC native hot plug
Heyi Guo [Mon, 9 Dec 2019 06:37:19 +0000 (14:37 +0800)] 
hw/arm/acpi: enable SHPC native hot plug

After the introduction of generic PCIe root port and PCIe-PCI bridge,
we will also have SHPC controller on ARM, so just enable SHPC native
hot plug.

Also update tests/data/acpi/virt/DSDT* to pass "make check".

Cc: Shannon Zhao <shannon.zhaosl@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: "Michael S. Tsirkin" <mst@redhat.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Heyi Guo <guoheyi@huawei.com>
Message-id: 20191209063719.23086-3-guoheyi@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agohw/arm/acpi: simplify AML bit and/or statement
Heyi Guo [Mon, 9 Dec 2019 06:37:18 +0000 (14:37 +0800)] 
hw/arm/acpi: simplify AML bit and/or statement

The last argument of AML bit and/or statement is the target variable,
so we don't need to use a NULL target and then an additional store
operation; using just aml_and() or aml_or() statement is enough.

Also update tests/data/acpi/virt/DSDT* to pass "make check".

Cc: Shannon Zhao <shannon.zhaosl@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: "Michael S. Tsirkin" <mst@redhat.com>
Cc: Igor Mammedov <imammedo@redhat.com>
Suggested-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Heyi Guo <guoheyi@huawei.com>
Message-id: 20191209063719.23086-2-guoheyi@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agohw/arm/sbsa-ref: Simplify by moving the gic in the machine state
Philippe Mathieu-Daudé [Fri, 6 Dec 2019 16:23:03 +0000 (17:23 +0100)] 
hw/arm/sbsa-ref: Simplify by moving the gic in the machine state

Make the gic a field in the machine state, and instead of filling
an array of qemu_irq and passing it around, directly call
qdev_get_gpio_in() on the gic field.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20191206162303.30338-1-philmd@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agotarget/arm: Add support for DC CVAP & DC CVADP ins
Beata Michalska [Thu, 21 Nov 2019 00:08:43 +0000 (00:08 +0000)] 
target/arm: Add support for DC CVAP & DC CVADP ins

ARMv8.2 introduced support for Data Cache Clean instructions
to PoP (point-of-persistence) - DC CVAP and PoDP (point-of-deep-persistence)
- DV CVADP. Both specify conceptual points in a memory system where all writes
that are to reach them are considered persistent.
The support provided considers both to be actually the same so there is no
distinction between the two. If none is available (there is no backing store
for given memory) both will result in Data Cache Clean up to the point of
coherency. Otherwise sync for the specified range shall be performed.

Signed-off-by: Beata Michalska <beata.michalska@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20191121000843.24844-5-beata.michalska@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agomigration: ram: Switch to ram block writeback
Beata Michalska [Thu, 21 Nov 2019 00:08:42 +0000 (00:08 +0000)] 
migration: ram: Switch to ram block writeback

Switch to ram block writeback for pmem migration.

Signed-off-by: Beata Michalska <beata.michalska@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Acked-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Message-id: 20191121000843.24844-4-beata.michalska@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agoMemory: Enable writeback for given memory region
Beata Michalska [Thu, 21 Nov 2019 00:08:41 +0000 (00:08 +0000)] 
Memory: Enable writeback for given memory region

Add an option to trigger memory writeback to sync given memory region
with the corresponding backing store, case one is available.
This extends the support for persistent memory, allowing syncing on-demand.

Signed-off-by: Beata Michalska <beata.michalska@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20191121000843.24844-3-beata.michalska@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agotcg: cputlb: Add probe_read
Beata Michalska [Thu, 21 Nov 2019 00:08:40 +0000 (00:08 +0000)] 
tcg: cputlb: Add probe_read

Add probe_read alongside the write probing equivalent.

Signed-off-by: Beata Michalska <beata.michalska@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20191121000843.24844-2-beata.michalska@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agoarm/arm-powerctl: set NSACR.{CP11, CP10} bits in arm_set_cpu_on()
Niek Linnenbank [Mon, 2 Dec 2019 21:09:43 +0000 (22:09 +0100)] 
arm/arm-powerctl: set NSACR.{CP11, CP10} bits in arm_set_cpu_on()

This change ensures that the FPU can be accessed in Non-Secure mode
when the CPU core is reset using the arm_set_cpu_on() function call.
The NSACR.{CP11,CP10} bits define the exception level required to
access the FPU in Non-Secure mode. Without these bits set, the CPU
will give an undefined exception trap on the first FPU access for the
secondary cores under Linux.

This is necessary because in this power-control codepath QEMU
is effectively emulating a bit of EL3 firmware, and has to set
the CPU up as the EL3 firmware would.

Fixes: fc1120a7f5
Cc: qemu-stable@nongnu.org
Signed-off-by: Niek Linnenbank <nieklinnenbank@gmail.com>
[PMM: added clarifying para to commit message]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agotarget/arm: Add support for missing Jazelle system registers
Marc Zyngier [Sun, 1 Dec 2019 12:20:18 +0000 (12:20 +0000)] 
target/arm: Add support for missing Jazelle system registers

QEMU lacks the minimum Jazelle implementation that is required
by the architecture (everything is RAZ or RAZ/WI). Add it
together with the HCR_EL2.TID0 trapping that goes with it.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20191201122018.25808-6-maz@kernel.org
[PMM: moved ARMCPRegInfo array to file scope, marked it
 'static global', moved new condition down in
 register_cp_regs_for_features() to go with other feature
 things rather than up with the v6/v7/v8 stuff]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agotarget/arm: Handle AArch32 CP15 trapping via HSTR_EL2
Marc Zyngier [Sun, 1 Dec 2019 12:20:17 +0000 (12:20 +0000)] 
target/arm: Handle AArch32 CP15 trapping via HSTR_EL2

HSTR_EL2 offers a way to trap ranges of CP15 system register
accesses to EL2, and it looks like this register is completely
ignored by QEMU.

To avoid adding extra .accessfn filters all over the place (which
would have a direct performance impact), let's add a new TB flag
that gets set whenever HSTR_EL2 is non-zero and that QEMU translates
a context where this trap has a chance to apply, and only generate
the extra access check if the hypervisor is actively using this feature.

Tested with a hand-crafted KVM guest accessing CBAR.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20191201122018.25808-5-maz@kernel.org
[PMM: use is_a64(); fix comment syntax]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agotarget/arm: Handle trapping to EL2 of AArch32 VMRS instructions
Marc Zyngier [Sun, 1 Dec 2019 12:20:16 +0000 (12:20 +0000)] 
target/arm: Handle trapping to EL2 of AArch32 VMRS instructions

HCR_EL2.TID3 requires that AArch32 reads of MVFR[012] are trapped to
EL2, and HCR_EL2.TID0 does the same for reads of FPSID.
In order to handle this, introduce a new TCG helper function that
checks for these control bits before executing the VMRC instruction.

Tested with a hacked-up version of KVM/arm64 that sets the control
bits for 32bit guests.

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20191201122018.25808-4-maz@kernel.org
[PMM: move helper declaration to helper.h; make it
 TCG_CALL_NO_WG]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agotarget/arm: Honor HCR_EL2.TID1 trapping requirements
Marc Zyngier [Sun, 1 Dec 2019 12:20:15 +0000 (12:20 +0000)] 
target/arm: Honor HCR_EL2.TID1 trapping requirements

HCR_EL2.TID1 mandates that access from EL1 to REVIDR_EL1, AIDR_EL1
(and their 32bit equivalents) as well as TCMTR, TLBTR are trapped
to EL2. QEMU ignores it, making it harder for a hypervisor to
virtualize the HW (though to be fair, no known hypervisor actually
cares).

Do the right thing by trapping to EL2 if HCR_EL2.TID1 is set.

Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20191201122018.25808-3-maz@kernel.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agotarget/arm: Honor HCR_EL2.TID2 trapping requirements
Marc Zyngier [Sun, 1 Dec 2019 12:20:14 +0000 (12:20 +0000)] 
target/arm: Honor HCR_EL2.TID2 trapping requirements

HCR_EL2.TID2 mandates that access from EL1 to CTR_EL0, CCSIDR_EL1,
CCSIDR2_EL1, CLIDR_EL1, CSSELR_EL1 are trapped to EL2, and QEMU
completely ignores it, making it impossible for hypervisors to
virtualize the cache hierarchy.

Do the right thing by trapping to EL2 if HCR_EL2.TID2 is set.

Signed-off-by: Marc Zyngier <maz@kernel.org>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20191201122018.25808-2-maz@kernel.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agoaspeed: Change the "nic" property definition
Cédric Le Goater [Tue, 19 Nov 2019 14:12:11 +0000 (15:12 +0100)] 
aspeed: Change the "nic" property definition

The Aspeed MII model has a link pointing to its associated FTGMAC100
NIC in the machine.

Change the "nic" property definition so that it explicitly sets the
pointer. The property isn't optional : not being able to set the link
is a bug and QEMU should rather abort than exit in this case.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-18-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agoaspeed: Change the "scu" property definition
Cédric Le Goater [Tue, 19 Nov 2019 14:12:10 +0000 (15:12 +0100)] 
aspeed: Change the "scu" property definition

The Aspeed Watchdog and Timer models have a link pointing to the SCU
controller model of the machine.

Change the "scu" property definition so that it explicitly sets the
pointer. The property isn't optional : not being able to set the link
is a bug and QEMU should rather abort than exit in this case.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-17-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agogpio: fix memory leak in aspeed_gpio_init()
PanNengyuan [Tue, 19 Nov 2019 14:12:09 +0000 (15:12 +0100)] 
gpio: fix memory leak in aspeed_gpio_init()

Address Sanitizer shows memory leak in hw/gpio/aspeed_gpio.c:875

Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: PanNengyuan <pannengyuan@huawei.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-16-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agoaspeed: Add support for the tacoma-bmc board
Cédric Le Goater [Tue, 19 Nov 2019 14:12:08 +0000 (15:12 +0100)] 
aspeed: Add support for the tacoma-bmc board

The Tacoma BMC board is replacement board for the BMC of the OpenPOWER
Witherspoon system. It uses a AST2600 SoC instead of a AST2500 and the
I2C layout is the same as it controls the same main board. Used for HW
bringup.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-15-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agoaspeed: Remove AspeedBoardConfig array and use AspeedMachineClass
Cédric Le Goater [Tue, 19 Nov 2019 14:12:07 +0000 (15:12 +0100)] 
aspeed: Remove AspeedBoardConfig array and use AspeedMachineClass

AspeedBoardConfig is a redundant way to define class attributes and it
complexifies the machine definition and initialization.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-14-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agoaspeed/smc: Add AST2600 timings registers
Cédric Le Goater [Tue, 19 Nov 2019 14:12:06 +0000 (15:12 +0100)] 
aspeed/smc: Add AST2600 timings registers

Each CS has its own Read Timing Compensation Register on newer SoCs.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-13-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agoaspeed/smc: Do not map disabled segment on the AST2600
Cédric Le Goater [Tue, 19 Nov 2019 14:12:05 +0000 (15:12 +0100)] 
aspeed/smc: Do not map disabled segment on the AST2600

The segments can be disabled on the AST2600 (zero register value).
CS0 is open by default but not the other CS. This is closing the
access to the flash device in user mode and forbids scanning.

In the model, check the segment size and disable the associated region
when the value is zero.

Fixes: bcaa8ddd081c ("aspeed/smc: Add AST2600 support")
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-12-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agoaspeed/smc: Restore default AHB window mapping at reset
Cédric Le Goater [Tue, 19 Nov 2019 14:12:04 +0000 (15:12 +0100)] 
aspeed/smc: Restore default AHB window mapping at reset

The current model only restores the Segment Register values but leaves
the previous CS mapping behind. Introduce a helper setting the
register value and mapping the region at the requested address. Use
this helper when a Segment register is set and at reset.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-11-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agowatchdog/aspeed: Fix AST2600 frequency behaviour
Joel Stanley [Tue, 19 Nov 2019 14:12:03 +0000 (15:12 +0100)] 
watchdog/aspeed: Fix AST2600 frequency behaviour

The AST2600 control register sneakily changed the meaning of bit 4
without anyone noticing. It no longer controls the 1MHz vs APB clock
select, and instead always runs at 1MHz.

The AST2500 was always 1MHz too, but it retained bit 4, making it read
only. We can model both using the same fixed 1MHz calculation.

Fixes: 6b2b2a703cad ("hw: wdt_aspeed: Add AST2600 support")
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-10-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agowatchdog/aspeed: Improve watchdog timeout message
Joel Stanley [Tue, 19 Nov 2019 14:12:02 +0000 (15:12 +0100)] 
watchdog/aspeed: Improve watchdog timeout message

Users benefit from knowing which watchdog timer has expired. The address
of the watchdog's registers unambiguously indicates which has expired,
so log that.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-9-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agoaspeed/scu: Fix W1C behavior
Joel Stanley [Tue, 19 Nov 2019 14:12:01 +0000 (15:12 +0100)] 
aspeed/scu: Fix W1C behavior

This models the clock write one to clear registers, and fixes up some
incorrect behavior in all of the write to clear registers.

There was also a typo in one of the register definitions.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-8-clg@kaod.org
[clg: checkpatch.pl fixes ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agoaspeed/sdmc: Make ast2600 default 1G
Joel Stanley [Tue, 19 Nov 2019 14:12:00 +0000 (15:12 +0100)] 
aspeed/sdmc: Make ast2600 default 1G

Most boards have this much.

Reviewed-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-7-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agoaspeed/i2c: Add trace events
Cédric Le Goater [Tue, 19 Nov 2019 14:11:59 +0000 (15:11 +0100)] 
aspeed/i2c: Add trace events

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Tested-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-6-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agoaspeed/i2c: Add support for DMA transfers
Cédric Le Goater [Tue, 19 Nov 2019 14:11:58 +0000 (15:11 +0100)] 
aspeed/i2c: Add support for DMA transfers

The I2C controller of the Aspeed AST2500 and AST2600 SoCs supports DMA
transfers to and from DRAM.

A pair of registers defines the buffer address and the length of the
DMA transfer. The address should be aligned on 4 bytes and the maximum
length should not exceed 4K. The receive or transmit DMA transfer can
then be initiated with specific bits in the Command/Status register of
the controller.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Tested-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-5-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agoaspeed: Add a DRAM memory region at the SoC level
Cédric Le Goater [Tue, 19 Nov 2019 14:11:57 +0000 (15:11 +0100)] 
aspeed: Add a DRAM memory region at the SoC level

Currently, we link the DRAM memory region to the FMC model (for DMAs)
through a property alias at the SoC level. The I2C model will need a
similar region for DMA support, add a DRAM region property at the SoC
level for both model to use.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Tested-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-4-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agoaspeed/i2c: Check SRAM enablement on AST2500
Cédric Le Goater [Tue, 19 Nov 2019 14:11:56 +0000 (15:11 +0100)] 
aspeed/i2c: Check SRAM enablement on AST2500

The SRAM must be enabled before using the Buffer Pool mode or the DMA
mode. This is not required on other SoCs.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Tested-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-3-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agoaspeed/i2c: Add support for pool buffer transfers
Cédric Le Goater [Tue, 19 Nov 2019 14:11:55 +0000 (15:11 +0100)] 
aspeed/i2c: Add support for pool buffer transfers

The Aspeed I2C controller can operate in different transfer modes :

  - Byte Buffer mode, using a dedicated register to transfer a
    byte. This is what the model supports today.

  - Pool Buffer mode, using an internal SRAM to transfer multiple
    bytes in the same command sequence.

Each SoC has different SRAM characteristics. On the AST2400, 2048
bytes of SRAM are available at offset 0x800 of the controller AHB
window. The pool buffer can be configured from 1 to 256 bytes per bus.

On the AST2500, the SRAM is at offset 0x200 and the pool buffer is of
16 bytes per bus.

On the AST2600, the SRAM is at offset 0xC00 and the pool buffer is of
32 bytes per bus. It can be splitted in two for TX and RX but the
current model does not add support for it as it it unused by known
drivers.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Tested-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20191119141211.25716-2-clg@kaod.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agoexynos4210_gic: Suppress gcc9 format-truncation warnings
David Gibson [Mon, 2 Dec 2019 06:08:06 +0000 (17:08 +1100)] 
exynos4210_gic: Suppress gcc9 format-truncation warnings

exynos4210_gic_realize() prints the number of cpus into some temporary
buffers, but it only allows 3 bytes space for it.  That's plenty:
existing machines will only ever set this value to EXYNOS4210_NCPUS
(2).  But the compiler can't always figure that out, so some[*] gcc9
versions emit -Wformat-truncation warnings.

We can fix that by hinting the constraint to the compiler with a
suitably placed assert().

[*] The bizarre thing here, is that I've long gotten these warnings
    compiling in a 32-bit x86 container as host - Fedora 30 with
    gcc-9.2.1-1.fc30.i686 - but it compiles just fine on my normal
    x86_64 host - Fedora 30 with and gcc-9.2.1-1.fc30.x86_64.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
[PMM: deleted stray blank line]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agotarget/arm: Add support for cortex-m7 CPU
Christophe Lyon [Mon, 2 Dec 2019 17:35:10 +0000 (17:35 +0000)] 
target/arm: Add support for cortex-m7 CPU

This is derived from cortex-m4 description, adding DP support and FPv5
instructions with the corresponding flags in isar and mvfr2.

Checked that it could successfully execute
vrinta.f32 s15, s15
while cortex-m4 emulation rejects it with "illegal instruction".

Signed-off-by: Christophe Lyon <christophe.lyon@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20191025090841.10299-1-christophe.lyon@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agoMerge remote-tracking branch 'remotes/cohuck/tags/s390x-20191214-2' into staging
Peter Maydell [Mon, 16 Dec 2019 10:35:33 +0000 (10:35 +0000)] 
Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20191214-2' into staging

First s390x update for 5.0:
- compat machines (also for other architectures)
- cleanups and fixes in reset handling
- fence off guest-set-time, as we have no hwclock
- fix some misuses of the error API
- further cleanups

# gpg: Signature made Sat 14 Dec 2019 09:33:17 GMT
# gpg:                using RSA key C3D0D66DC3624FF6A8C018CEDECF6B93C6F02FAF
# gpg:                issuer "cohuck@redhat.com"
# gpg: Good signature from "Cornelia Huck <conny@cornelia-huck.de>" [unknown]
# gpg:                 aka "Cornelia Huck <huckc@linux.vnet.ibm.com>" [full]
# gpg:                 aka "Cornelia Huck <cornelia.huck@de.ibm.com>" [full]
# gpg:                 aka "Cornelia Huck <cohuck@kernel.org>" [unknown]
# gpg:                 aka "Cornelia Huck <cohuck@redhat.com>" [unknown]
# Primary key fingerprint: C3D0 D66D C362 4FF6 A8C0  18CE DECF 6B93 C6F0 2FAF

* remotes/cohuck/tags/s390x-20191214-2:
  qga: fence guest-set-time if hwclock not available
  s390x/tcg: clear local interrupts on reset normal
  s390x/cpumodel: Fix query-cpu-definitions error API violations
  s390x/cpumodel: Fix query-cpu-model-FOO error API violations
  s390x/cpumodel: Fix realize() error API violations
  s390x/cpumodel: Fix feature property error API violations
  s390x/event-facility: Fix realize() error API violations
  s390x: Fix cpu normal reset ri clearing
  s390x: kvm: Make kvm_sclp_service_call void
  s390x: Beautify diag308 handling
  s390x: Move clear reset
  s390x: Move initial reset
  s390x: Move reset normal to shared reset handler
  s390x: Don't do a normal reset on the initial cpu
  hw: add compat machines for 5.0
  vfio-ccw: Fix error message

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agoqga: fence guest-set-time if hwclock not available
Cornelia Huck [Wed, 27 Nov 2019 10:43:25 +0000 (11:43 +0100)] 
qga: fence guest-set-time if hwclock not available

The Posix implementation of guest-set-time invokes hwclock to
set/retrieve the time to/from the hardware clock. If hwclock
is not available, the user is currently informed that "hwclock
failed to set hardware clock to system time", which is quite
misleading. This may happen e.g. on s390x, which has a different
timekeeping concept anyway.

Let's check for the availability of the hwclock command and
return QERR_UNSUPPORTED for guest-set-time if it is not available.

Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Michael Roth <mdroth@linux.vnet.ibm.com>
Message-Id: <20191205115350.18713-1-cohuck@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
22 months agos390x/tcg: clear local interrupts on reset normal
Cornelia Huck [Wed, 4 Dec 2019 17:04:47 +0000 (18:04 +0100)] 
s390x/tcg: clear local interrupts on reset normal

We neglected to clean up pending interrupts and emergency signals;
fix that.

Message-Id: <20191206135404.16051-1-cohuck@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
22 months agos390x/cpumodel: Fix query-cpu-definitions error API violations
Markus Armbruster [Wed, 4 Dec 2019 09:36:22 +0000 (10:36 +0100)] 
s390x/cpumodel: Fix query-cpu-definitions error API violations

qmp_query_cpu_definitions() passes @errp to get_max_cpu_model(), then
frees any error it gets back.  This effectively ignores errors.
Dereferencing @errp is wrong; see the big comment in error.h.  Passing
@errp is also wrong, because it works only as long as @errp is neither
@error_fatal nor @error_abort.  Introduced in commit 38cba1f4d8
"s390x: return unavailable features via query-cpu-definitions".

No caller actually passes such @errp values.

Fix anyway: simply pass NULL to get_max_cpu_model().

Cc: David Hildenbrand <david@redhat.com>
Cc: Cornelia Huck <cohuck@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Message-Id: <20191204093625.14836-16-armbru@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
22 months agos390x/cpumodel: Fix query-cpu-model-FOO error API violations
Markus Armbruster [Wed, 4 Dec 2019 09:36:21 +0000 (10:36 +0100)] 
s390x/cpumodel: Fix query-cpu-model-FOO error API violations

cpu_model_from_info() is a helper for qmp_query_cpu_model_expansion(),
qmp_query_cpu_model_comparison(), qmp_query_cpu_model_baseline().  It
dereferences @errp when the visitor or the QOM setter fails.  That's
wrong; see the big comment in error.h.  Introduced in commit
137974cea3 's390x/cpumodel: implement QMP interface
"query-cpu-model-expansion"'.

Its three callers have the same issue.  Introduced in commit
4e82ef0502 's390x/cpumodel: implement QMP interface
"query-cpu-model-comparison"' and commit f1a47d08ef 's390x/cpumodel:
implement QMP interface "query-cpu-model-baseline"'.

No caller actually passes null.

Fix anyway: splice in a local Error *err, and error_propagate().

Cc: David Hildenbrand <david@redhat.com>
Cc: Cornelia Huck <cohuck@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Message-Id: <20191204093625.14836-15-armbru@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
22 months agos390x/cpumodel: Fix realize() error API violations
Markus Armbruster [Wed, 4 Dec 2019 09:36:20 +0000 (10:36 +0100)] 
s390x/cpumodel: Fix realize() error API violations

get_max_cpu_model() dereferences @errp when
kvm_s390_get_host_cpu_model() fails, apply_cpu_model() dereferences it
when kvm_s390_apply_cpu_model() fails, and s390_realize_cpu_model()
dereferences it when get_max_cpu_model() or check_compatibility()
fail.  That's wrong; see the big comment in error.h.  All three
introduced in commit 80560137cf "s390x/cpumodel: check and apply the
CPU model".

No caller actually passes null.

Fix anyway: splice in a local Error *err, and error_propagate().

Cc: David Hildenbrand <david@redhat.com>
Cc: Cornelia Huck <cohuck@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Message-Id: <20191204093625.14836-14-armbru@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
22 months agos390x/cpumodel: Fix feature property error API violations
Markus Armbruster [Wed, 4 Dec 2019 09:36:19 +0000 (10:36 +0100)] 
s390x/cpumodel: Fix feature property error API violations

s390x-cpu property setters set_feature() and set_feature_group()
dereference @errp when the visitor fails.  That's wrong; see the big
comment in error.h.  Introduced in commit 0754f60429 "s390x/cpumodel:
expose features and feature groups as properties".

No caller actually passes null.

Fix anyway: splice in a local Error *err, and error_propagate().

Cc: David Hildenbrand <david@redhat.com>
Cc: Cornelia Huck <cohuck@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Message-Id: <20191204093625.14836-13-armbru@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
22 months agos390x/event-facility: Fix realize() error API violations
Markus Armbruster [Wed, 4 Dec 2019 09:36:18 +0000 (10:36 +0100)] 
s390x/event-facility: Fix realize() error API violations

sclp_events_bus_realize() dereferences @errp when
object_property_set_bool() fails.  That's wrong; see the big comment
in error.h.  Introduced in commit f6102c329c "s390/sclp: rework sclp
event facility initialization + device realization".

No caller actually passes null.

Fix anyway: splice in a local Error *err, and error_propagate().

Cc: David Hildenbrand <david@redhat.com>
Cc: Cornelia Huck <cohuck@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Message-Id: <20191204093625.14836-12-armbru@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
22 months agos390x: Fix cpu normal reset ri clearing
Janosch Frank [Tue, 3 Dec 2019 13:28:12 +0000 (08:28 -0500)] 
s390x: Fix cpu normal reset ri clearing

As it turns out we need to clear the ri controls and PSW enablement
bit to be architecture compliant.

Signed-off-by: Janosch Frank <frankja@linux.ibm.com>
Reviewed-by: Christian Borntraeger <borntraeger@de.ibm.com>
Message-Id: <20191203132813.2734-4-frankja@linux.ibm.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
22 months agos390x: kvm: Make kvm_sclp_service_call void
Janosch Frank [Fri, 29 Nov 2019 09:17:13 +0000 (04:17 -0500)] 
s390x: kvm: Make kvm_sclp_service_call void

It defaults to returning 0 anyway and that return value is not
necessary, as 0 is also the default rc that the caller would return.

While doing that we can simplify the logic a bit and return early if
we inject a PGM exception.

Signed-off-by: Janosch Frank <frankja@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20191129091713.4582-1-frankja@linux.ibm.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
22 months agos390x: Beautify diag308 handling
Janosch Frank [Wed, 27 Nov 2019 17:50:45 +0000 (12:50 -0500)] 
s390x: Beautify diag308 handling

Let's improve readability by:
* Using constants for the subcodes
* Moving parameter checking into a function
* Removing subcode > 6 check as the default case catches that

Signed-off-by: Janosch Frank <frankja@linux.ibm.com>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Message-Id: <20191127175046.4911-6-frankja@linux.ibm.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
22 months agos390x: Move clear reset
Janosch Frank [Wed, 27 Nov 2019 17:50:44 +0000 (12:50 -0500)] 
s390x: Move clear reset

Let's also move the clear reset function into the reset handler.

Signed-off-by: Janosch Frank <frankja@linux.ibm.com>
Message-Id: <20191127175046.4911-5-frankja@linux.ibm.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
22 months agos390x: Move initial reset
Janosch Frank [Thu, 28 Nov 2019 08:37:23 +0000 (03:37 -0500)] 
s390x: Move initial reset

Let's move the intial reset into the reset handler and cleanup
afterwards.

Signed-off-by: Janosch Frank <frankja@linux.ibm.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Message-Id: <20191128083723.11937-1-frankja@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
22 months agos390x: Move reset normal to shared reset handler
Janosch Frank [Wed, 27 Nov 2019 17:50:42 +0000 (12:50 -0500)] 
s390x: Move reset normal to shared reset handler

Let's start moving the cpu reset functions into a single function with
a switch/case, so we can later use fallthroughs and share more code
between resets.

This patch introduces the reset function by renaming cpu_reset().

Signed-off-by: Janosch Frank <frankja@linux.ibm.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Message-Id: <20191127175046.4911-3-frankja@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
22 months agos390x: Don't do a normal reset on the initial cpu
Janosch Frank [Wed, 27 Nov 2019 17:50:41 +0000 (12:50 -0500)] 
s390x: Don't do a normal reset on the initial cpu

The initiating cpu needs to be reset with an initial reset. While
doing a normal reset followed by a initial reset is not wrong per se,
the Ultravisor will only allow the correct reset to be performed.

Signed-off-by: Janosch Frank <frankja@linux.ibm.com>
Reviewed-by: David Hildenbrand <david@redhat.com>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Message-Id: <20191127175046.4911-2-frankja@linux.ibm.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
22 months agohw: add compat machines for 5.0
Cornelia Huck [Tue, 12 Nov 2019 10:48:11 +0000 (11:48 +0100)] 
hw: add compat machines for 5.0

Add 5.0 machine types for arm/i440fx/q35/s390x/spapr.

For i440fx and q35, unversioned cpu models are still translated
to -v1; I'll leave changing this (if desired) to the respective
maintainers.

Signed-off-by: Cornelia Huck <cohuck@redhat.com>
Message-Id: <20191112104811.30323-1-cohuck@redhat.com>
Acked-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
22 months agovfio-ccw: Fix error message
Boris Fiuczynski [Thu, 28 Nov 2019 14:30:14 +0000 (15:30 +0100)] 
vfio-ccw: Fix error message

Signed-off-by: Boris Fiuczynski <fiuczy@linux.ibm.com>
Reviewed-by: Eric Farman <farman@linux.ibm.com>
Message-Id: <20191128143015.5231-1-fiuczy@linux.ibm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
22 months agoMerge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging
Peter Maydell [Fri, 13 Dec 2019 18:14:07 +0000 (18:14 +0000)] 
Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging

Pull request

# gpg: Signature made Fri 13 Dec 2019 14:32:11 GMT
# gpg:                using RSA key 8695A8BFD3F97CDAAC35775A9CA4ABB381AB73C8
# gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>" [full]
# gpg:                 aka "Stefan Hajnoczi <stefanha@gmail.com>" [full]
# Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35  775A 9CA4 ABB3 81AB 73C8

* remotes/stefanha/tags/block-pull-request:
  iothread: document -object iothread on man page
  virtio-blk: advertise F_WCE (F_FLUSH) if F_CONFIG_WCE is advertised

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agoMerge remote-tracking branch 'remotes/dgilbert/tags/pull-virtiofs-20191213a' into...
Peter Maydell [Fri, 13 Dec 2019 15:58:53 +0000 (15:58 +0000)] 
Merge remote-tracking branch 'remotes/dgilbert/tags/pull-virtiofs-20191213a' into staging

virtiofs pull 2019-12-13: Minor fixes and cleanups

Cleanup from Marc-André and MSI-X fix from Stefan.

# gpg: Signature made Fri 13 Dec 2019 11:53:49 GMT
# gpg:                using RSA key 45F5C71B4A0CB7FB977A9FA90516331EBC5BFDE7
# gpg: Good signature from "Dr. David Alan Gilbert (RH2) <dgilbert@redhat.com>" [full]
# Primary key fingerprint: 45F5 C71B 4A0C B7FB 977A  9FA9 0516 331E BC5B FDE7

* remotes/dgilbert/tags/pull-virtiofs-20191213a:
  virtio-fs: fix MSI-X nvectors calculation
  vhost-user-fs: remove "vhostfd" property

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agoMerge remote-tracking branch 'remotes/gkurz/tags/9p-next-2019-12-12' into staging
Peter Maydell [Fri, 13 Dec 2019 13:47:45 +0000 (13:47 +0000)] 
Merge remote-tracking branch 'remotes/gkurz/tags/9p-next-2019-12-12' into staging

- conversion of virtfs-proxy-helper from libcap to libcap-ng
- removal of libcap-dev from docker, travis and gitlab CI
- removal of deprecate "-virtfs_synth" option

# gpg: Signature made Thu 12 Dec 2019 19:55:53 GMT
# gpg:                using RSA key B4828BAF943140CEF2A3491071D4D5E5822F73D6
# gpg: Good signature from "Greg Kurz <groug@kaod.org>" [full]
# gpg:                 aka "Gregory Kurz <gregory.kurz@free.fr>" [full]
# gpg:                 aka "[jpeg image of size 3330]" [full]
# Primary key fingerprint: B482 8BAF 9431 40CE F2A3  4910 71D4 D5E5 822F 73D6

* remotes/gkurz/tags/9p-next-2019-12-12:
  virtfs: Remove the deprecated "-virtfs_synth" option
  travis.yml: Drop libcap-dev
  ci: Use libcap-ng
  docker: remove libcap development packages
  virtfs-proxy-helper: switch from libcap to libcap-ng

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agoOpen 5.0 development tree
Peter Maydell [Fri, 13 Dec 2019 11:59:06 +0000 (11:59 +0000)] 
Open 5.0 development tree

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agoiothread: document -object iothread on man page
Stefan Hajnoczi [Fri, 25 Oct 2019 12:22:36 +0000 (14:22 +0200)] 
iothread: document -object iothread on man page

Add -object iothread documentation to the man page, including references
to the query-iothread QMP command and qom-set syntax for adjusting
adaptive polling parameters at run-time.

Reported-by: Zhenyu Ye <yezhenyu2@huawei.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-id: 20191025122236.29815-1-stefanha@redhat.com
Message-Id: <20191025122236.29815-1-stefanha@redhat.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
22 months agovirtio-blk: advertise F_WCE (F_FLUSH) if F_CONFIG_WCE is advertised
Evgeny Yakovlev [Tue, 5 Nov 2019 18:22:17 +0000 (21:22 +0300)] 
virtio-blk: advertise F_WCE (F_FLUSH) if F_CONFIG_WCE is advertised

Virtio spec 1.1 (and earlier), 5.2.5.2 Driver Requirements: Device
Initialization:

"Devices SHOULD always offer VIRTIO_BLK_F_FLUSH, and MUST offer it if
they offer VIRTIO_BLK_F_CONFIG_WCE"

Currently F_CONFIG_WCE and F_WCE are not connected to each other.
Qemu will advertise F_CONFIG_WCE if config-wce argument is
set for virtio-blk device. And F_WCE is advertised only if
underlying block backend actually has it's caching enabled.

Fix this by advertising F_WCE if F_CONFIG_WCE is also advertised.

To preserve backwards compatibility with newer machine types make this
behaviour governed by "x-enable-wce-if-config-wce" virtio-blk-device
property and introduce hw_compat_4_2 with new property being off by
default for all machine types <= 4.2 (but don't introduce 4.3
machine type itself yet).

Signed-off-by: Evgeny Yakovlev <wrfsh@yandex-team.ru>
Message-Id: <1572978137-189218-1-git-send-email-wrfsh@yandex-team.ru>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
22 months agovirtio-fs: fix MSI-X nvectors calculation
Stefan Hajnoczi [Mon, 9 Dec 2019 11:07:59 +0000 (11:07 +0000)] 
virtio-fs: fix MSI-X nvectors calculation

The following MSI-X vectors are required:
 * VIRTIO Configuration Change
 * hiprio virtqueue
 * requests virtqueues

Fix the calculation to reserve enough MSI-X vectors.  Otherwise guest
drivers fall back to a sub-optional configuration where all virtqueues
share a single vector.

This change does not break live migration compatibility since
vhost-user-fs-pci devices are not migratable yet.

Reported-by: Vivek Goyal <vgoyal@redhat.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20191209110759.35227-1-stefanha@redhat.com>
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
22 months agovhost-user-fs: remove "vhostfd" property
Marc-André Lureau [Sat, 16 Nov 2019 11:20:16 +0000 (15:20 +0400)] 
vhost-user-fs: remove "vhostfd" property

The property doesn't make much sense for a vhost-user device.

Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20191116112016.14872-1-marcandre.lureau@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
22 months agoUpdate version for v4.2.0 release v4.2.0
Peter Maydell [Thu, 12 Dec 2019 16:45:57 +0000 (16:45 +0000)] 
Update version for v4.2.0 release

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agoUpdate version for v4.2.0-rc5 release v4.2.0-rc5
Peter Maydell [Tue, 10 Dec 2019 17:15:21 +0000 (17:15 +0000)] 
Update version for v4.2.0-rc5 release

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agovirtfs: Remove the deprecated "-virtfs_synth" option
Thomas Huth [Mon, 9 Dec 2019 14:52:40 +0000 (15:52 +0100)] 
virtfs: Remove the deprecated "-virtfs_synth" option

It's been marked as deprecated since QEMU v4.1, time to remove it now.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Greg Kurz <groug@kaod.org>
22 months agotravis.yml: Drop libcap-dev
Greg Kurz [Mon, 2 Dec 2019 14:29:20 +0000 (15:29 +0100)] 
travis.yml: Drop libcap-dev

Commit 7e46261368d1 converted virtfs-proxy-helper to using libcap-ng. There
aren't any users of libcap anymore. No need to install libcap-dev.

Signed-off-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
22 months agoci: Use libcap-ng
Dr. David Alan Gilbert [Fri, 29 Nov 2019 14:21:26 +0000 (14:21 +0000)] 
ci: Use libcap-ng

We currently enable libcap-dev in build-clang to pick up the 9p proxy
helper.  Paolo's patch changes (commit 7e46261368d1) that to use
libcap-ng, so switch to using it.  This also means we'll be testing the
scsi pr manager and the bridge helper.

Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Acked-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
[groug, mention SHA1 that dropped libcap]
Signed-off-by: Greg Kurz <groug@kaod.org>
22 months agodocker: remove libcap development packages
Paolo Bonzini [Fri, 29 Nov 2019 15:08:01 +0000 (16:08 +0100)] 
docker: remove libcap development packages

Libcap was dropped from virtio-9p (commit 7e46261368d1), so remove it from
the dockerfiles as well.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Acked-by: Alex Bennée <alex.bennee@linaro.org>
[groug, mention SHA1 that dropped libcap]
Signed-off-by: Greg Kurz <groug@kaod.org>
22 months agoMerge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2019-12-09' into staging
Peter Maydell [Mon, 9 Dec 2019 16:06:51 +0000 (16:06 +0000)] 
Merge remote-tracking branch 'remotes/ericb/tags/pull-nbd-2019-12-09' into staging

bitmap fix for 4.2-rc5

- Fix a regression that broke bitmap deletion without a transaction,
and causes a crash with transaction (only transaction is new to 4.2),
when a qcow2 file contains persistent bitmaps from prior shutdown

# gpg: Signature made Mon 09 Dec 2019 15:28:19 GMT
# gpg:                using RSA key 71C2CC22B1C4602927D2F3AAA7A16B4A2527436A
# gpg: Good signature from "Eric Blake <eblake@redhat.com>" [full]
# gpg:                 aka "Eric Blake (Free Software Programmer) <ebb9@byu.net>" [full]
# gpg:                 aka "[jpeg image of size 6874]" [full]
# Primary key fingerprint: 71C2 CC22 B1C4 6029 27D2  F3AA A7A1 6B4A 2527 436A

* remotes/ericb/tags/pull-nbd-2019-12-09:
  block/qcow2-bitmap: fix crash bug in qcow2_co_remove_persistent_dirty_bitmap

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agoblock/qcow2-bitmap: fix crash bug in qcow2_co_remove_persistent_dirty_bitmap
Vladimir Sementsov-Ogievskiy [Thu, 5 Dec 2019 19:30:49 +0000 (22:30 +0300)] 
block/qcow2-bitmap: fix crash bug in qcow2_co_remove_persistent_dirty_bitmap

Here is double bug:

First, return error but not set errp. This may lead to:
qmp block-dirty-bitmap-remove may report success when actually failed

block-dirty-bitmap-remove used in a transaction will crash, as
qmp_transaction will think that it returned success and will call
block_dirty_bitmap_remove_commit which will crash, as state->bitmap is
NULL

Second (like in anecdote), this case is not an error at all. As it is
documented in the comment above bdrv_co_remove_persistent_dirty_bitmap
definition, absence of bitmap is not an error, and similar case handled
at start of qcow2_co_remove_persistent_dirty_bitmap, it returns 0 when
there is no bitmaps at all.

But when there are some bitmaps, but not the requested one, it return
error with errp unset.

Fix that.

Trigger:
1. create persistent bitmap A
2. shutdown vm  (bitmap A is synced)
3. start vm
4. create persistent bitmap B
5. remove bitmap B - it fails (and crashes if in transaction)

Potential workaround (rather invasive to ask clients to implement it):
1. create persistent bitmap A
2. shutdown vm
3. start vm
4. create persistent bitmap B
5. remember, that we want to remove bitmap B after vm shutdown
...
  some other operations
...
6. vm shutdown
7. start vm in stopped mode, and remove all bitmaps marked for removing
8. stop vm

Fixes: b56a1e31759b750
Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-Id: <20191205193049.30666-1-vsementsov@virtuozzo.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: John Snow <jsnow@redhat.com>
[eblake: commit message tweaks]
Signed-off-by: Eric Blake <eblake@redhat.com>
22 months agoMerge remote-tracking branch 'remotes/dgibson/tags/ppc-for-4.2-20191209' into staging
Peter Maydell [Mon, 9 Dec 2019 11:07:34 +0000 (11:07 +0000)] 
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-4.2-20191209' into staging

ppc patch queue 2019-12-09

This is a last minute pull request for ppc-for-4.2.  I know it's very
late in freeze, but this does fix a regression: a bad interaction
between the new qemu and SLOF device tree construction code means that
SLOF will crash if PCI to PCI bridges are included in the system.

This PR supersedes ppc-for-4.2-20191206.  This one has only a more
minimal change to the firmware addressed only at fixing this bug and
not incorporating some other unrelated changes that happened in the
meantime.

# gpg: Signature made Mon 09 Dec 2019 04:52:19 GMT
# gpg:                using RSA key 75F46586AE61A66CC44E87DC6C38CACA20D9B392
# gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>" [full]
# gpg:                 aka "David Gibson (Red Hat) <dgibson@redhat.com>" [full]
# gpg:                 aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>" [full]
# gpg:                 aka "David Gibson (kernel.org) <dwg@kernel.org>" [unknown]
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-4.2-20191209:
  pseries: Update SLOF firmware image

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agopseries: Update SLOF firmware image
Alexey Kardashevskiy [Mon, 9 Dec 2019 01:07:46 +0000 (12:07 +1100)] 
pseries: Update SLOF firmware image

This fixes PCI bridge regression.

Alexey Kardashevskiy (3):
      ibm,client-architecture-support: Fix stack handling
      fdt: Fix updating the tree at H_CAS
      version: update to 20191209

Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
22 months agoMerge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
Peter Maydell [Fri, 6 Dec 2019 15:05:20 +0000 (15:05 +0000)] 
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging

* fix for x86 KVM on older kernels (Yang Zhong)

# gpg: Signature made Fri 06 Dec 2019 11:36:08 GMT
# gpg:                using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg:                issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg:                 aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4  E2F7 7E15 100C CD36 69B1
#      Subkey fingerprint: F133 3857 4B66 2389 866C  7682 BFFB D25F 78C7 AE83

* remotes/bonzini/tags/for-upstream:
  target/i386: disable VMX features if nested=0

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agotarget/i386: disable VMX features if nested=0
Yang Zhong [Fri, 6 Dec 2019 07:11:11 +0000 (15:11 +0800)] 
target/i386: disable VMX features if nested=0

If kvm does not support VMX feature by nested=0, the kvm_vmx_basic
can't get the right value from MSR_IA32_VMX_BASIC register, which
make qemu coredump when qemu do KVM_SET_MSRS.

The coredump info:
error: failed to set MSR 0x480 to 0x0
kvm_put_msrs: Assertion `ret == cpu->kvm_msr_buf->nmsrs' failed.

Signed-off-by: Yang Zhong <yang.zhong@intel.com>
Message-Id: <20191206071111.12128-1-yang.zhong@intel.com>
Reported-by: Catherine Ho <catherine.hecx@gmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
22 months agoUpdate version for v4.2.0-rc4 release v4.2.0-rc4
Peter Maydell [Tue, 3 Dec 2019 17:56:30 +0000 (17:56 +0000)] 
Update version for v4.2.0-rc4 release

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agoMerge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
Peter Maydell [Tue, 3 Dec 2019 10:07:56 +0000 (10:07 +0000)] 
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging

* last HVF fix (Cameron)

# gpg: Signature made Tue 03 Dec 2019 08:11:51 GMT
# gpg:                using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg:                issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg:                 aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4  E2F7 7E15 100C CD36 69B1
#      Subkey fingerprint: F133 3857 4B66 2389 866C  7682 BFFB D25F 78C7 AE83

* remotes/bonzini/tags/for-upstream:
  hvf: correctly inject VMCS_INTR_T_HWINTR versus VMCS_INTR_T_SWINTR.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agohvf: correctly inject VMCS_INTR_T_HWINTR versus VMCS_INTR_T_SWINTR.
Cameron Esfahani [Mon, 2 Dec 2019 23:55:41 +0000 (15:55 -0800)] 
hvf: correctly inject VMCS_INTR_T_HWINTR versus VMCS_INTR_T_SWINTR.

Previous implementation in hvf_inject_interrupts() would always inject
VMCS_INTR_T_SWINTR even when VMCS_INTR_T_HWINTR was required.  Now
correctly determine when VMCS_INTR_T_HWINTR is appropriate versus
VMCS_INTR_T_SWINTR.

Make sure to clear ins_len and has_error_code when ins_len isn't
valid and error_code isn't set.

Signed-off-by: Cameron Esfahani <dirty@apple.com>
Message-Id: <bf8d945ea1b423786d7802bbcf769517d1fd01f8.1575330463.git.dirty@apple.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
22 months agoMerge remote-tracking branch 'remotes/armbru/tags/pull-error-2019-12-02' into staging
Peter Maydell [Mon, 2 Dec 2019 16:29:41 +0000 (16:29 +0000)] 
Merge remote-tracking branch 'remotes/armbru/tags/pull-error-2019-12-02' into staging

Error reporting patches for 2019-12-02

# gpg: Signature made Mon 02 Dec 2019 15:17:45 GMT
# gpg:                using RSA key 354BC8B3D7EB2A6B68674E5F3870B400EB918653
# gpg:                issuer "armbru@redhat.com"
# gpg: Good signature from "Markus Armbruster <armbru@redhat.com>" [full]
# gpg:                 aka "Markus Armbruster <armbru@pond.sub.org>" [full]
# Primary key fingerprint: 354B C8B3 D7EB 2A6B 6867  4E5F 3870 B400 EB91 8653

* remotes/armbru/tags/pull-error-2019-12-02:
  block/file-posix: Fix laio_init() error handling crash bug
  net/virtio: Fix failover error handling crash bugs
  net/virtio: Drop useless n->primary_dev not null checks

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agoblock/file-posix: Fix laio_init() error handling crash bug
Markus Armbruster [Sat, 30 Nov 2019 19:42:22 +0000 (20:42 +0100)] 
block/file-posix: Fix laio_init() error handling crash bug

raw_aio_attach_aio_context() passes uninitialized Error *local_err by
reference to laio_init() via aio_setup_linux_aio().  When laio_init()
fails, it passes it on to error_setg_errno(), tripping error_setv()'s
assertion unless @local_err is null by dumb luck.

Fix by initializing @local_err properly.

Fixes: ed6e2161715c527330f936d44af4c547f25f687e
Cc: Nishanth Aravamudan <naravamudan@digitalocean.com>
Cc: Stefan Hajnoczi <stefanha@redhat.com>
Cc: Kevin Wolf <kwolf@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20191130194240.10517-4-armbru@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Kevin Wolf <kwolf@redhat.com>
22 months agonet/virtio: Fix failover error handling crash bugs
Markus Armbruster [Sat, 30 Nov 2019 19:42:21 +0000 (20:42 +0100)] 
net/virtio: Fix failover error handling crash bugs

Functions that take an Error ** parameter to pass an error to the
caller expect the parameter to point to null.
failover_replug_primary() violates this precondition in several
places:

* After qemu_opts_from_qdict() failed, *errp is no longer null.
  Passing it to error_setg() is wrong, and will trip the assertion in
  error_setv().  Messed up in commit 150ab54aa6 "net/virtio: fix
  re-plugging of primary device".  Simply drop the error_setg().

* Passing @errp to qemu_opt_set_bool(), hotplug_handler_pre_plug(),
  and hotplug_handler_plug() is wrong.  If one of the first two fails,
  *errp is no longer null.  Risks tripping the same assertion.
  Moreover, continuing after such errors is unsafe.  Messed up in
  commit 9711cd0dfc "net/virtio: add failover support".  Fix by
  handling each error properly.

failover_replug_primary() crashes when passed a null @errp.  Also
messed up in commit 9711cd0dfc.  This bug can't bite as no caller
actually passes null.  Fix it anyway.

Fixes: 9711cd0dfc3fa414f7f64935713c07134ae67971
Fixes: 150ab54aa6934583180f88a2bd540bc6fc4fbff3
Cc: Jens Freimann <jfreimann@redhat.com>
Cc: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20191130194240.10517-3-armbru@redhat.com>
Reviewed-by: Jens Freimann <jfreimann@redhat.com>
22 months agonet/virtio: Drop useless n->primary_dev not null checks
Markus Armbruster [Sat, 30 Nov 2019 19:42:20 +0000 (20:42 +0100)] 
net/virtio: Drop useless n->primary_dev not null checks

virtio_net_handle_migration_primary() returns early when it can't
ensure n->primary_dev is non-null.  Checking it again right after that
early return is redundant.  Drop.

If n->primary_dev is null on entering failover_replug_primary(), @pdev
will become null, and pdev->partially_hotplugged will crash.  Checking
n->primary_dev later is useless.  It can't actually be null, because
its caller virtio_net_handle_migration_primary() ensures it isn't.
Drop the useless check.

Cc: Jens Freimann <jfreimann@redhat.com>
Cc: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
Message-Id: <20191130194240.10517-2-armbru@redhat.com>
Reviewed-by: Jens Freimann <jfreimann@redhat.com>
22 months agovirtfs-proxy-helper: switch from libcap to libcap-ng
Paolo Bonzini [Fri, 29 Nov 2019 11:16:32 +0000 (12:16 +0100)] 
virtfs-proxy-helper: switch from libcap to libcap-ng

virtfs-proxy-helper is the only user of libcap; everyone else is using
the simpler libcap-ng API.  Switch and remove the configure code to
detect libcap.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
[groug: - drop remaining -lcap from Makefile
        - fix error message in configure]
Signed-off-by: Greg Kurz <groug@kaod.org>
22 months ago.travis.yml: drop xcode9.4 from build matrix
Alex Bennée [Wed, 27 Nov 2019 13:24:30 +0000 (13:24 +0000)] 
.travis.yml: drop xcode9.4 from build matrix

It's broken so it's no longer helping. The latest Xcode is covered by
Cirrus.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-id: 20191127132430.3681-1-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agoMerge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2019-11-29' into...
Peter Maydell [Fri, 29 Nov 2019 11:41:54 +0000 (11:41 +0000)] 
Merge remote-tracking branch 'remotes/huth-gitlab/tags/pull-request-2019-11-29' into staging

A fix for regression in the s390-ccw bios

# gpg: Signature made Fri 29 Nov 2019 09:26:51 GMT
# gpg:                using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg:                issuer "thuth@redhat.com"
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [full]
# gpg:                 aka "Thomas Huth <thuth@redhat.com>" [full]
# gpg:                 aka "Thomas Huth <huth@tuxfamily.org>" [full]
# gpg:                 aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3  EAB9 2ED9 D774 FE70 2DB5

* remotes/huth-gitlab/tags/pull-request-2019-11-29:
  pc-bios/s390: Update firmware image with the "fix sclp_get_loadparm_ascii" patch
  pc-bios/s390-ccw: fix sclp_get_loadparm_ascii

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
22 months agopc-bios/s390: Update firmware image with the "fix sclp_get_loadparm_ascii" patch
Thomas Huth [Fri, 29 Nov 2019 09:12:33 +0000 (10:12 +0100)] 
pc-bios/s390: Update firmware image with the "fix sclp_get_loadparm_ascii" patch

This fixes various boot scenarios, e.g. the possibility to use
"-boot menu=on".

Signed-off-by: Thomas Huth <thuth@redhat.com>
22 months agopc-bios/s390-ccw: fix sclp_get_loadparm_ascii
Claudio Imbrenda [Thu, 28 Nov 2019 12:33:57 +0000 (13:33 +0100)] 
pc-bios/s390-ccw: fix sclp_get_loadparm_ascii

The existing s390 bios gets the LOADPARM information from the system using
an SCLP call that specifies a buffer length too small to contain all the
output.

The recent fixes in the SCLP code have exposed this bug, since now the
SCLP call will return an error (as per architecture) instead of
writing partially and completing successfully.

The solution is simply to specify the full page length as the SCCB
length instead of a smaller size.

Fixes: 832be0d8a3bb ("s390x: sclp: Report insufficient SCCB length")
Fixes: 9a22473c70f3 ("pc-bios/s390-ccw: get LOADPARM stored in SCP Read Info")

Reported-by: Marc Hartmayer <mhartmay@linux.ibm.com>
Signed-off-by: Claudio Imbrenda <imbrenda@linux.ibm.com>
Message-Id: <1574944437-31182-1-git-send-email-imbrenda@linux.ibm.com>
Acked-by: Christian Borntraeger <borntraeger@de.ibm.com>
Tested-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Janosch Frank <frankja@linux.ibm.com>
Tested-by: Marc Hartmayer <mhartmay@linux.ibm.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
23 months agoUpdate version for v4.2.0-rc3 release v4.2.0-rc3
Peter Maydell [Tue, 26 Nov 2019 21:52:26 +0000 (21:52 +0000)] 
Update version for v4.2.0-rc3 release

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23 months agoMerge remote-tracking branch 'remotes/stsquad/tags/pull-rc3-testing-261119-1' into...
Peter Maydell [Tue, 26 Nov 2019 20:43:46 +0000 (20:43 +0000)] 
Merge remote-tracking branch 'remotes/stsquad/tags/pull-rc3-testing-261119-1' into staging

A few vm-test updates

  - use Ubuntu 18.04 for i386 image
  - python3 for centos and docker
  - install locales for ubuntu

# gpg: Signature made Tue 26 Nov 2019 11:31:26 GMT
# gpg:                using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44
# gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full]
# Primary key fingerprint: 6685 AE99 E751 67BC AFC8  DF35 FBD0 DB09 5A9E 2A44

* remotes/stsquad/tags/pull-rc3-testing-261119-1:
  tests/vm/ubuntu: update i386 image to 18.04
  tests/vm/ubuntu: include language pack to silence locale warnings
  tests/vm/centos: fix centos build target

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
23 months agoMerge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
Peter Maydell [Tue, 26 Nov 2019 19:48:01 +0000 (19:48 +0000)] 
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging

* VMX feature fix (myself)
* HVF fixes (Cameron)

# gpg: Signature made Tue 26 Nov 2019 08:58:43 GMT
# gpg:                using RSA key F13338574B662389866C7682BFFBD25F78C7AE83
# gpg:                issuer "pbonzini@redhat.com"
# gpg: Good signature from "Paolo Bonzini <bonzini@gnu.org>" [full]
# gpg:                 aka "Paolo Bonzini <pbonzini@redhat.com>" [full]
# Primary key fingerprint: 46F5 9FBD 57D6 12E7 BFD4  E2F7 7E15 100C CD36 69B1
#      Subkey fingerprint: F133 3857 4B66 2389 866C  7682 BFFB D25F 78C7 AE83

* remotes/bonzini/tags/for-upstream:
  hvf: more accurately match SDM when setting CR0 and PDPTE registers
  hvf: correctly handle REX prefix in relation to legacy prefixes
  hvf: remove TSC synchronization code because it isn't fully complete
  hvf: non-RAM, non-ROMD memory ranges are now correctly mapped in
  target/i386: add two missing VMX features for Skylake and CascadeLake Server

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>