qemu.git
6 months agovhost-user-gpu: fix resource leak in 'vg_resource_create_2d' (CVE-2021-3544)
Li Qiang [Sun, 16 May 2021 03:03:57 +0000 (20:03 -0700)] 
vhost-user-gpu: fix resource leak in 'vg_resource_create_2d' (CVE-2021-3544)

Call 'vugbm_buffer_destroy' in error path to avoid resource leak.

Fixes: CVE-2021-3544
Reported-by: Li Qiang <liq3ea@163.com>
Reviewed-by: Prasad J Pandit <pjp@fedoraproject.org>
Signed-off-by: Li Qiang <liq3ea@163.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20210516030403.107723-3-liq3ea@163.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
6 months agovhost-user-gpu: fix memory disclosure in virgl_cmd_get_capset_info (CVE-2021-3545)
Li Qiang [Sun, 16 May 2021 03:03:56 +0000 (20:03 -0700)] 
vhost-user-gpu: fix memory disclosure in virgl_cmd_get_capset_info (CVE-2021-3545)

Otherwise some of the 'resp' will be leaked to guest.

Fixes: CVE-2021-3545
Reported-by: Li Qiang <liq3ea@163.com>
virtio-gpu fix: 42a8dadc74 ("virtio-gpu: fix information leak
in getting capset info dispatch")

Signed-off-by: Li Qiang <liq3ea@163.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20210516030403.107723-2-liq3ea@163.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
6 months agoMerge remote-tracking branch 'remotes/kraxel/tags/input-20210526-pull-request' into... 309921307 310113928
Peter Maydell [Wed, 26 May 2021 14:27:20 +0000 (15:27 +0100)] 
Merge remote-tracking branch 'remotes/kraxel/tags/input-20210526-pull-request' into staging

input: a bunch of ps2 fixes.

# gpg: Signature made Wed 26 May 2021 15:06:12 BST
# gpg:                using RSA key A0328CFFB93A17A79901FE7D4CB6D8EED3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>" [full]
# gpg:                 aka "Gerd Hoffmann <gerd@kraxel.org>" [full]
# gpg:                 aka "Gerd Hoffmann (private) <kraxel@gmail.com>" [full]
# Primary key fingerprint: A032 8CFF B93A 17A7 9901  FE7D 4CB6 D8EE D3E8 7138

* remotes/kraxel/tags/input-20210526-pull-request:
  hw/input/ps2: Use ps2_raise_irq() instead of open coding it
  pckbd: clear outport_present in outer pre_load()
  pckbd: remove duplicated keyboard and mouse defines
  pckbd: correctly disable PS/2 communication
  pckbd: add function kbd_pending()
  pckbd: add controller response queue
  pckbd: add state variable for interrupt source
  pckbd: PS/2 keyboard throttle
  pckbd: don't update OBF flags if KBD_STAT_OBF is set
  pckbd: split out interrupt line changing code
  ps2: don't deassert irq twice if queue is empty
  ps2: don't raise an interrupt if queue is full
  ps2: fix mouse stream corruption
  hw/input: expand trace info reported for ps2 device

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agohw/input/ps2: Use ps2_raise_irq() instead of open coding it
Philippe Mathieu-Daudé [Thu, 13 May 2021 17:12:44 +0000 (19:12 +0200)] 
hw/input/ps2: Use ps2_raise_irq() instead of open coding it

Inspired-by: Volker Rümelin <vr_qemu@t-online.de>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Volker Rümelin <vr_qemu@t-online.de>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20210513171244.3940519-1-f4bug@amsat.org>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
6 months agopckbd: clear outport_present in outer pre_load()
Volker Rümelin [Tue, 25 May 2021 18:14:41 +0000 (20:14 +0200)] 
pckbd: clear outport_present in outer pre_load()

The variable outport_present is a flag to show if the outport
subsection was loaded. Clear the outport_present flag in the
outer pre_load() function. This method is recommended in the QEMU
manual for developers in the chapter "Migration, Subsections".

Signed-off-by: Volker Rümelin <vr_qemu@t-online.de>
Message-Id: <20210525181441.27768-12-vr_qemu@t-online.de>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
6 months agopckbd: remove duplicated keyboard and mouse defines
Volker Rümelin [Tue, 25 May 2021 18:14:40 +0000 (20:14 +0200)] 
pckbd: remove duplicated keyboard and mouse defines

In 2005 the author of commit daa579632d "PS2 mouse and keyboard
separation (Paul Brook)" and 0e43e99c04 "PS2 mouse and keyboard
separation (Paul Brook)" separated the PS/2 controller code and
the PS/2 keyboard and mouse code. It seems he forgot to remove
a few defines. Remove them now.

Signed-off-by: Volker Rümelin <vr_qemu@t-online.de>
Message-Id: <20210525181441.27768-11-vr_qemu@t-online.de>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
6 months agopckbd: correctly disable PS/2 communication
Volker Rümelin [Tue, 25 May 2021 18:14:39 +0000 (20:14 +0200)] 
pckbd: correctly disable PS/2 communication

Currently the PS/2 controller command KBD_CCMD_MOUSE_DISABLE
doesn't disable the PS/2 mouse communication at all, and the
PS/2 controller commands KBD_CCMD_KBD_DISABLE and
KBD_CCMD_KBD_ENABLE only disable and enable the keyboard
interrupt, which is very different from what a real PS/2
controller does. A guest may notice the difference.

Mask out pending data on disabled queues to correctly disable
the PS/2 controller communication.

Signed-off-by: Volker Rümelin <vr_qemu@t-online.de>
Message-Id: <20210525181441.27768-10-vr_qemu@t-online.de>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
6 months agopckbd: add function kbd_pending()
Volker Rümelin [Tue, 25 May 2021 18:14:38 +0000 (20:14 +0200)] 
pckbd: add function kbd_pending()

Replace reads of the variable s->pending with a call to a new
function kbd_pending() to ease the review of the next patch.
There is no functional change.

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Volker Rümelin <vr_qemu@t-online.de>
Message-Id: <20210525181441.27768-9-vr_qemu@t-online.de>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
6 months agopckbd: add controller response queue
Volker Rümelin [Tue, 25 May 2021 18:14:37 +0000 (20:14 +0200)] 
pckbd: add controller response queue

Add a separate queue for PS/2 controller responses. The
responses no longer get queued in the keyboard or mouse queues.
The advantage of this can be seen after the next two patches,
where the guest can disable the PS/2 communication with keyboard
and mouse and still talk to the PS/2 controller.

Signed-off-by: Volker Rümelin <vr_qemu@t-online.de>
Message-Id: <20210525181441.27768-8-vr_qemu@t-online.de>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
6 months agopckbd: add state variable for interrupt source
Volker Rümelin [Tue, 25 May 2021 18:14:36 +0000 (20:14 +0200)] 
pckbd: add state variable for interrupt source

Currently there is only one flag to distinguish between two
interrupt sources and there are no available flags for more
sources. Add an internal state variable to store the interrupt
source. The next patch will introduce an additional interrupt
source. There is no functional change.

Signed-off-by: Volker Rümelin <vr_qemu@t-online.de>
Message-Id: <20210525181441.27768-7-vr_qemu@t-online.de>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
6 months agopckbd: PS/2 keyboard throttle
Volker Rümelin [Tue, 25 May 2021 18:14:35 +0000 (20:14 +0200)] 
pckbd: PS/2 keyboard throttle

Limit the keyboard data rate to the serial link speed. Some old
DOS software relies on being able to read an incoming scan-code
more than once. After reading keyboard data from the i8042
controller, the guest software has 1ms to read the same data
again.

Use -global i8042.kbd-throttle=on to enable this feature.

To see how this patch works, start a FreeDOS 1.2 guest with the
qemu option -global i8042.kbd-throttle=on and open a text file
with the vim 7.3 32 bit for DOS executable. Then use the cursor
keys (not the cursor keys on the numeric keypad) to move through
the text. Without the kbd-throttle option enabled each keystroke
will move the cursor two positions.

Buglink: https://bugs.launchpad.net/bugs/1895363
Buglink: https://bugs.launchpad.net/bugs/1897568
Signed-off-by: Volker Rümelin <vr_qemu@t-online.de>
Message-Id: <20210525181441.27768-6-vr_qemu@t-online.de>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
6 months agopckbd: don't update OBF flags if KBD_STAT_OBF is set
Volker Rümelin [Tue, 25 May 2021 18:14:34 +0000 (20:14 +0200)] 
pckbd: don't update OBF flags if KBD_STAT_OBF is set

Don't update the OBF flags in the status register and the cor-
responding IRQ lines if KBD_STAT_OBF is set. Otherwise this
may change the PS/2 event type. If the guest ISR was already
scheduled, the changed event type will be rather surprising for
the guest.

This fixes a mouse event stream corruption. To reproduce the
problem start a FreeDOS 1.2 guest with -machine pc,accel=kvm
and -display gtk. The KVM in-kernel irqchip has to be enabled.
Now open a text file with edit.exe in the guest and hold down
the cursor right key and at the same time move the mouse around.
You will quickly notice erratic mouse movements and unexpected
mouse clicks.

A trace file shows the mouse event stream corruption. Guest
rip 0xce93 (f000:ce93) is the in al,0x60 instruction in the
seabios mouse ISR, guest rip 0xceca (f000:ceca) is the
in al,0x60 instruction in the seabios keyboard ISR.

qemu-system-x86-5659  [007] ....   280.971116:
 tracing_mark_write: pckbd_kbd_update_irq kbd=0 aux=1
 # gtk queues a mouse event

qemu-system-x86-5665  [000] ....   280.971121:
 kvm_exit: reason EXTERNAL_INTERRUPT rip 0x22da info 0 800000fd
qemu-system-x86-5665  [000] d..1   280.971122:
 kvm_entry: vcpu 0, rip 0x22da
qemu-system-x86-5665  [000] ....   280.971123:
 kvm_exit: reason EXTERNAL_INTERRUPT rip 0x22da info 0 800000fd
qemu-system-x86-5665  [000] d..1   280.971124:
 kvm_entry: vcpu 0, rip 0x22da
qemu-system-x86-5665  [000] ....   280.971126:
 kvm_exit: reason IO_INSTRUCTION rip 0x110c8c info 640008 0
qemu-system-x86-5665  [000] ....   280.971176:
 tracing_mark_write: pckbd_kbd_read_status 0x3d
 # KBD_STAT_OBF and KBD_STAT_MOUSE_OBF set, the mouse ISR will
 # read data from the PS/2 controller.

qemu-system-x86-5665  [000] d..1   280.971180:
 kvm_entry: vcpu 0, rip 0x110c8d
qemu-system-x86-5665  [000] ....   280.971191:
 kvm_exit: reason EXTERNAL_INTERRUPT rip 0x110c8d info 0 800000f6
qemu-system-x86-5665  [000] d..1   280.971191:
 kvm_entry: vcpu 0, rip 0x110c8d
qemu-system-x86-5665  [000] ....   280.971193:
 kvm_exit: reason IO_INSTRUCTION rip 0xce93 info 600048 0
 # the mouse ISR wants to read data from the PS/2 controller

qemu-system-x86-5659  [007] ....   280.971231:
 tracing_mark_write: pckbd_kbd_update_irq kbd=1 aux=0
qemu-system-x86-5659  [007] ....   280.971238:
 tracing_mark_write: pckbd_kbd_update_irq kbd=1 aux=0
 # gtk queues a keyboard event 0xe0 0x4d (key right)

qemu-system-x86-5665  [000] ....   280.971257:
 tracing_mark_write: pckbd_kbd_update_irq kbd=0 aux=1
qemu-system-x86-5665  [000] ....   280.971262:
 tracing_mark_write: pckbd_kbd_update_irq kbd=1 aux=0
 # ps2_read_data() deasserts and reasserts the keyboard IRQ

qemu-system-x86-5665  [000] ....   280.971266:
 tracing_mark_write: pckbd_kbd_read_data 0xe0 kbd
 # -> the mouse ISR receives keyboard data

qemu-system-x86-5665  [000] d..1   280.971268:
 kvm_entry: vcpu 0, rip 0xce95
qemu-system-x86-5665  [000] ....   280.971269:
 kvm_exit: reason IO_INSTRUCTION rip 0xe828 info a00040 0
qemu-system-x86-5665  [000] ....   280.971270:
 kvm_ack_irq: irqchip PIC slave pin 12
qemu-system-x86-5665  [000] d..1   280.971270:
 kvm_entry: vcpu 0, rip 0xe82a
qemu-system-x86-5665  [000] ....   280.971271:
 kvm_exit: reason IO_INSTRUCTION rip 0xe82a info 200040 0
qemu-system-x86-5665  [000] ....   280.971271:
 kvm_ack_irq: irqchip PIC master pin 2
qemu-system-x86-5665  [000] d..1   280.971271:
 kvm_entry: vcpu 0, rip 0xe82c
qemu-system-x86-5665  [000] ....   280.971272:
 kvm_exit: reason PENDING_INTERRUPT rip 0x22da info 0 0
qemu-system-x86-5665  [000] d..1   280.971273:
 kvm_entry: vcpu 0, rip 0x22da
qemu-system-x86-5665  [000] ....   280.971274:
 kvm_exit: reason IO_INSTRUCTION rip 0x110c8c info 640008 0
qemu-system-x86-5665  [000] ....   280.971275:
 tracing_mark_write: pckbd_kbd_read_status 0x1d
qemu-system-x86-5665  [000] d..1   280.971276:
 kvm_entry: vcpu 0, rip 0x110c8d
qemu-system-x86-5665  [000] ....   280.971277:
 kvm_exit: reason IO_INSTRUCTION rip 0xceca info 600048 0
 # the keyboard ISR wants to read data from the PS/2 controller

qemu-system-x86-5665  [000] ....   280.971279:
 tracing_mark_write: pckbd_kbd_update_irq kbd=0 aux=1
qemu-system-x86-5665  [000] ....   280.971282:
 tracing_mark_write: pckbd_kbd_read_data 0x4d kbd
 # the keyboard ISR receives the second byte of the keyboard event

Signed-off-by: Volker Rümelin <vr_qemu@t-online.de>
Message-Id: <20210525181441.27768-5-vr_qemu@t-online.de>

[ kraxel: add missing include ]

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
6 months agopckbd: split out interrupt line changing code
Volker Rümelin [Tue, 25 May 2021 18:14:33 +0000 (20:14 +0200)] 
pckbd: split out interrupt line changing code

Split out the interrupt line changing code from kbd_update_irq().
This is a preparation for the next patch. There is no functional
change.

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Volker Rümelin <vr_qemu@t-online.de>
Message-Id: <20210525181441.27768-4-vr_qemu@t-online.de>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
6 months agops2: don't deassert irq twice if queue is empty
Volker Rümelin [Tue, 25 May 2021 18:14:32 +0000 (20:14 +0200)] 
ps2: don't deassert irq twice if queue is empty

Don't deassert the irq twice if the queue is empty. While the
second deassertion doesn't do any harm, it's unnecessary.

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Volker Rümelin <vr_qemu@t-online.de>
Message-Id: <20210525181441.27768-3-vr_qemu@t-online.de>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
6 months agops2: don't raise an interrupt if queue is full
Volker Rümelin [Tue, 25 May 2021 18:14:31 +0000 (20:14 +0200)] 
ps2: don't raise an interrupt if queue is full

ps2_queue() behaves differently than the very similar functions
ps2_queue_2() to ps2_queue_4(). The first one calls update_irq()
even if the queue is full, the others don't. Change ps2_queue()
to be consistent with the others.

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Volker Rümelin <vr_qemu@t-online.de>
Message-Id: <20210525181441.27768-2-vr_qemu@t-online.de>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
6 months agops2: fix mouse stream corruption
Volker Rümelin [Tue, 25 May 2021 18:14:30 +0000 (20:14 +0200)] 
ps2: fix mouse stream corruption

Commit 7abe7eb294 "ps2: Fix mouse stream corruption due to lost data"
added code to avoid mouse stream corruptions but the calculation of
the needed free queue size was wrong. Fix this.

To reproduce, open a text file with the vim 7.3 32 bit for DOS exe-
cutable in a FreeDOS client started with -display sdl and move the
mouse around for a few seconds. You will quickly see erratic mouse
movements and unexpected mouse clicks. CuteMouse (ctmouse.exe) in
FreeDOS doesn't try to re-sync the mouse stream.

Fixes: 7abe7eb294 ("ps2: Fix mouse stream corruption due to lost data")
Signed-off-by: Volker Rümelin <vr_qemu@t-online.de>
Message-Id: <20210525181441.27768-1-vr_qemu@t-online.de>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
6 months agohw/input: expand trace info reported for ps2 device
Daniel P. Berrangé [Tue, 9 Mar 2021 15:58:04 +0000 (15:58 +0000)] 
hw/input: expand trace info reported for ps2 device

It is interesting to know if the PS2 keyboard is in translated mode, and
which of the three scancode sets are in use.

Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20210309155804.306051-1-berrange@redhat.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
6 months agoMerge remote-tracking branch 'remotes/stsquad/tags/pull-testing-and-misc-updates... 309313632 309920659
Peter Maydell [Tue, 25 May 2021 16:31:04 +0000 (17:31 +0100)] 
Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-and-misc-updates-250521-2' into staging

Testing, gdbstub and plugin updates

  - ensure gitlab references master registry
  - add special rule for hexagon image
  - clean-up gdbstub's argument handling
  - fix replay HMP commands to accept long icount
  - minor re-factor of gdbstub replay handling
  - update syscall plugin to be more useful

# gpg: Signature made Tue 25 May 2021 16:55:16 BST
# gpg:                using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44
# gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full]
# Primary key fingerprint: 6685 AE99 E751 67BC AFC8  DF35 FBD0 DB09 5A9E 2A44

* remotes/stsquad/tags/pull-testing-and-misc-updates-250521-2:
  plugins/syscall: Added a table-like summary output
  gdbstub: tidy away reverse debugging check into function
  hmp-commands: expand type of icount to "l" in replay commands
  gdbstub: Replace GdbCmdContext with plain g_array()
  gdbstub: Constify GdbCmdParseEntry
  gitlab: add special rule for the hexagon container
  gitlab: explicitly reference the upstream registry

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agoplugins/syscall: Added a table-like summary output
Mahmoud Mandour [Thu, 20 May 2021 17:43:03 +0000 (18:43 +0100)] 
plugins/syscall: Added a table-like summary output

Added a table-like output which contains the total number of calls
for each used syscall along with the number of errors that occurred.

Per-call tracing is still available through supplying the argument
``print`` to the plugin.

Signed-off-by: Mahmoud Mandour <ma.mandourr@gmail.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20210519032409.3041-1-ma.mandourr@gmail.com>
Message-Id: <20210520174303.12310-9-alex.bennee@linaro.org>

6 months agogdbstub: tidy away reverse debugging check into function
Alex Bennée [Thu, 20 May 2021 17:43:02 +0000 (18:43 +0100)] 
gdbstub: tidy away reverse debugging check into function

In theory we don't need an actual record/replay to enact reverse
debugging on a purely deterministic system (i.e one with no external
inputs running under icount). Tidy away the logic into a little
function.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210520174303.12310-8-alex.bennee@linaro.org>

6 months agohmp-commands: expand type of icount to "l" in replay commands
Alex Bennée [Thu, 20 May 2021 17:43:01 +0000 (18:43 +0100)] 
hmp-commands: expand type of icount to "l" in replay commands

This is not a 32 bit number, it can (and most likely will) be quite a
big one.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210520174303.12310-7-alex.bennee@linaro.org>

6 months agogdbstub: Replace GdbCmdContext with plain g_array()
Alex Bennée [Tue, 25 May 2021 08:24:14 +0000 (09:24 +0100)] 
gdbstub: Replace GdbCmdContext with plain g_array()

Instead of jumping through hoops let glib deal with both tracking the
number of elements and auto freeing the memory once we are done. This
allows is to drop the usage of ALLOCA(3) which the man-page mentions
its "use is discouraged".

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20210520174303.12310-6-alex.bennee@linaro.org>

6 months agogdbstub: Constify GdbCmdParseEntry
Philippe Mathieu-Daudé [Thu, 20 May 2021 17:42:59 +0000 (18:42 +0100)] 
gdbstub: Constify GdbCmdParseEntry

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20210505170055.1415360-3-philmd@redhat.com>
Message-Id: <20210520174303.12310-5-alex.bennee@linaro.org>

6 months agogitlab: add special rule for the hexagon container
Alex Bennée [Thu, 20 May 2021 17:42:58 +0000 (18:42 +0100)] 
gitlab: add special rule for the hexagon container

The hexagon container is always manually built but of course not
everyone will be building it themselves and pushing to their
registries. We still need to create a "local" registry copy for the
actual gitlab tests to run. We don't build it in this case, just pull
it across from the upstream registry. We disable this rule from
running on the qemu-project itself so it doesn't accidentally wipe out
our master copy.

Fixes: 910c40ee94 ("gitlab: add build-user-hexagon test")
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Willian Rampazzo <willianr@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Cc: Cornelia Huck <cohuck@redhat.com>
Message-Id: <20210520174303.12310-4-alex.bennee@linaro.org>

6 months agoMerge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210525' into... 309268411 309313098
Peter Maydell [Tue, 25 May 2021 15:17:06 +0000 (16:17 +0100)] 
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20210525' into staging

target-arm queue:
 * Implement SVE2 emulation
 * Implement integer matrix multiply accumulate
 * Implement FEAT_TLBIOS
 * Implement FEAT_TLBRANGE
 * disas/libvixl: Protect C system header for C++ compiler
 * Use correct SP in M-profile exception return
 * AN524, AN547: Correct modelling of internal SRAMs
 * hw/intc/arm_gicv3_cpuif: Fix EOIR write access check logic
 * hw/arm/smmuv3: Another range invalidation fix

# gpg: Signature made Tue 25 May 2021 16:02:25 BST
# gpg:                using RSA key E1A5C593CD419DE28E8315CF3C2525ED14360CDE
# gpg:                issuer "peter.maydell@linaro.org"
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>" [ultimate]
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>" [ultimate]
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20210525: (114 commits)
  target/arm: Enable SVE2 and related extensions
  linux-user/aarch64: Enable hwcap bits for sve2 and related extensions
  target/arm: Implement integer matrix multiply accumulate
  target/arm: Implement aarch32 VSUDOT, VUSDOT
  target/arm: Split decode of VSDOT and VUDOT
  target/arm: Split out do_neon_ddda
  target/arm: Fix decode for VDOT (indexed)
  target/arm: Remove unused fpst from VDOT_scalar
  target/arm: Split out do_neon_ddda_fpst
  target/arm: Implement aarch64 SUDOT, USDOT
  target/arm: Implement SVE2 fp multiply-add long
  target/arm: Move endian adjustment macros to vec_internal.h
  target/arm: Implement SVE2 bitwise shift immediate
  target/arm: Implement 128-bit ZIP, UZP, TRN
  target/arm: Implement SVE2 LD1RO
  target/arm: Tidy do_ldrq
  target/arm: Share table of sve load functions
  target/arm: Implement SVE2 FLOGB
  target/arm: Implement SVE2 FCVTXNT, FCVTX
  target/arm: Implement SVE2 FCVTLT
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Enable SVE2 and related extensions
Richard Henderson [Tue, 25 May 2021 01:03:58 +0000 (18:03 -0700)] 
target/arm: Enable SVE2 and related extensions

Disable I8MM again for !have_neon during realize.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-93-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agolinux-user/aarch64: Enable hwcap bits for sve2 and related extensions
Richard Henderson [Tue, 25 May 2021 01:03:57 +0000 (18:03 -0700)] 
linux-user/aarch64: Enable hwcap bits for sve2 and related extensions

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-92-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement integer matrix multiply accumulate
Richard Henderson [Tue, 25 May 2021 01:03:56 +0000 (18:03 -0700)] 
target/arm: Implement integer matrix multiply accumulate

This is {S,U,US}MMLA for both AArch64 AdvSIMD and SVE,
and V{S,U,US}MMLA.S8 for AArch32 NEON.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-91-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement aarch32 VSUDOT, VUSDOT
Richard Henderson [Tue, 25 May 2021 01:03:55 +0000 (18:03 -0700)] 
target/arm: Implement aarch32 VSUDOT, VUSDOT

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-90-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Split decode of VSDOT and VUDOT
Richard Henderson [Tue, 25 May 2021 01:03:54 +0000 (18:03 -0700)] 
target/arm: Split decode of VSDOT and VUDOT

Now that we have a common helper, sharing decode does not
save much.  Also, this will solve an upcoming naming problem.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-89-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Split out do_neon_ddda
Richard Henderson [Tue, 25 May 2021 01:03:53 +0000 (18:03 -0700)] 
target/arm: Split out do_neon_ddda

Split out a helper that can handle the 4-register
format for helpers shared with SVE.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-88-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Fix decode for VDOT (indexed)
Richard Henderson [Tue, 25 May 2021 01:03:52 +0000 (18:03 -0700)] 
target/arm: Fix decode for VDOT (indexed)

We were extracting the M register twice, once incorrectly
as M:vm and once correctly as rm.  Remove the incorrect
name and remove the incorrect decode.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-87-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Remove unused fpst from VDOT_scalar
Richard Henderson [Tue, 25 May 2021 01:03:51 +0000 (18:03 -0700)] 
target/arm: Remove unused fpst from VDOT_scalar

Cut and paste error from another pattern.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-86-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Split out do_neon_ddda_fpst
Richard Henderson [Tue, 25 May 2021 01:03:50 +0000 (18:03 -0700)] 
target/arm: Split out do_neon_ddda_fpst

Split out a helper that can handle the 4-register
format for helpers shared with SVE.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-85-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement aarch64 SUDOT, USDOT
Richard Henderson [Tue, 25 May 2021 01:03:49 +0000 (18:03 -0700)] 
target/arm: Implement aarch64 SUDOT, USDOT

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-84-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 fp multiply-add long
Stephen Long [Tue, 25 May 2021 01:03:48 +0000 (18:03 -0700)] 
target/arm: Implement SVE2 fp multiply-add long

Implements both vectored and indexed FMLALB, FMLALT, FMLSLB, FMLSLT

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-83-richard.henderson@linaro.org
Message-Id: <20200504171240.11220-1-steplong@quicinc.com>
[rth: Rearrange to use float16_to_float32_by_bits.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Move endian adjustment macros to vec_internal.h
Richard Henderson [Tue, 25 May 2021 01:03:47 +0000 (18:03 -0700)] 
target/arm: Move endian adjustment macros to vec_internal.h

We have two copies of these, one set of which is not complete.
Move them to a common header.

Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-82-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 bitwise shift immediate
Stephen Long [Tue, 25 May 2021 01:03:46 +0000 (18:03 -0700)] 
target/arm: Implement SVE2 bitwise shift immediate

Implements SQSHL/UQSHL, SRSHR/URSHR, and SQSHLU

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-81-richard.henderson@linaro.org
Message-Id: <20200430194159.24064-1-steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement 128-bit ZIP, UZP, TRN
Richard Henderson [Tue, 25 May 2021 01:03:45 +0000 (18:03 -0700)] 
target/arm: Implement 128-bit ZIP, UZP, TRN

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-80-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 LD1RO
Richard Henderson [Tue, 25 May 2021 01:03:44 +0000 (18:03 -0700)] 
target/arm: Implement SVE2 LD1RO

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-79-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Tidy do_ldrq
Richard Henderson [Tue, 25 May 2021 01:03:43 +0000 (18:03 -0700)] 
target/arm: Tidy do_ldrq

Use tcg_constant_i32 for passing the simd descriptor,
as this hashed value does not need to be freed.
Rename dofs to doff to match poff.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-78-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Share table of sve load functions
Richard Henderson [Tue, 25 May 2021 01:03:42 +0000 (18:03 -0700)] 
target/arm: Share table of sve load functions

The table used by do_ldrq is a subset of the table used by do_ld_zpa;
we can share them by passing dtype instead of msz to do_ldrq.

The lack of MTE handling in do_ldrq was a bug, fixed by this change.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-77-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 FLOGB
Stephen Long [Tue, 25 May 2021 01:03:41 +0000 (18:03 -0700)] 
target/arm: Implement SVE2 FLOGB

Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-76-richard.henderson@linaro.org
Message-Id: <20200430191405.21641-1-steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 FCVTXNT, FCVTX
Stephen Long [Tue, 25 May 2021 01:03:40 +0000 (18:03 -0700)] 
target/arm: Implement SVE2 FCVTXNT, FCVTX

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-75-richard.henderson@linaro.org
Message-Id: <20200428174332.17162-4-steplong@quicinc.com>
[rth: Use do_frint_mode, which avoids a specific runtime helper.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 FCVTLT
Stephen Long [Tue, 25 May 2021 01:03:39 +0000 (18:03 -0700)] 
target/arm: Implement SVE2 FCVTLT

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-74-richard.henderson@linaro.org
Message-Id: <20200428174332.17162-3-steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 FCVTNT
Richard Henderson [Tue, 25 May 2021 01:03:38 +0000 (18:03 -0700)] 
target/arm: Implement SVE2 FCVTNT

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-73-richard.henderson@linaro.org
Message-Id: <20200428174332.17162-2-steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 TBL, TBX
Stephen Long [Tue, 25 May 2021 01:03:37 +0000 (18:03 -0700)] 
target/arm: Implement SVE2 TBL, TBX

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-72-richard.henderson@linaro.org
Message-Id: <20200428144352.9275-1-steplong@quicinc.com>
[rth: rearrange the macros a little and rebase]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 crypto constructive binary operations
Richard Henderson [Tue, 25 May 2021 01:03:36 +0000 (18:03 -0700)] 
target/arm: Implement SVE2 crypto constructive binary operations

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-71-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 crypto destructive binary operations
Richard Henderson [Tue, 25 May 2021 01:03:35 +0000 (18:03 -0700)] 
target/arm: Implement SVE2 crypto destructive binary operations

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-70-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 crypto unary operations
Richard Henderson [Tue, 25 May 2021 01:03:34 +0000 (18:03 -0700)] 
target/arm: Implement SVE2 crypto unary operations

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-69-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE mixed sign dot product
Richard Henderson [Tue, 25 May 2021 01:03:33 +0000 (18:03 -0700)] 
target/arm: Implement SVE mixed sign dot product

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-68-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE mixed sign dot product (indexed)
Richard Henderson [Tue, 25 May 2021 01:03:32 +0000 (18:03 -0700)] 
target/arm: Implement SVE mixed sign dot product (indexed)

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-67-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Macroize helper_gvec_{s,u}dot_idx_{b,h}
Richard Henderson [Tue, 25 May 2021 01:03:31 +0000 (18:03 -0700)] 
target/arm: Macroize helper_gvec_{s,u}dot_idx_{b,h}

We're about to add more variations on this theme.
Accept the inner loop for the _h variants, rather
than keep it unrolled.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-66-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Macroize helper_gvec_{s,u}dot_{b,h}
Richard Henderson [Tue, 25 May 2021 01:03:30 +0000 (18:03 -0700)] 
target/arm: Macroize helper_gvec_{s,u}dot_{b,h}

We're about to add more variations on this theme.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-65-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 complex integer dot product
Richard Henderson [Tue, 25 May 2021 01:03:29 +0000 (18:03 -0700)] 
target/arm: Implement SVE2 complex integer dot product

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-64-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 complex integer multiply-add (indexed)
Richard Henderson [Tue, 25 May 2021 01:03:28 +0000 (18:03 -0700)] 
target/arm: Implement SVE2 complex integer multiply-add (indexed)

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-63-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 integer multiply long (indexed)
Richard Henderson [Tue, 25 May 2021 01:03:27 +0000 (18:03 -0700)] 
target/arm: Implement SVE2 integer multiply long (indexed)

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-62-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 multiply-add long (indexed)
Richard Henderson [Tue, 25 May 2021 01:03:26 +0000 (18:03 -0700)] 
target/arm: Implement SVE2 multiply-add long (indexed)

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-61-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 saturating multiply high (indexed)
Richard Henderson [Tue, 25 May 2021 01:03:25 +0000 (18:03 -0700)] 
target/arm: Implement SVE2 saturating multiply high (indexed)

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-60-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 signed saturating doubling multiply high
Richard Henderson [Tue, 25 May 2021 01:03:24 +0000 (18:03 -0700)] 
target/arm: Implement SVE2 signed saturating doubling multiply high

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-59-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 saturating multiply (indexed)
Richard Henderson [Tue, 25 May 2021 01:03:23 +0000 (18:03 -0700)] 
target/arm: Implement SVE2 saturating multiply (indexed)

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-58-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 saturating multiply-add (indexed)
Richard Henderson [Tue, 25 May 2021 01:03:22 +0000 (18:03 -0700)] 
target/arm: Implement SVE2 saturating multiply-add (indexed)

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-57-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 saturating multiply-add high (indexed)
Richard Henderson [Tue, 25 May 2021 01:03:21 +0000 (18:03 -0700)] 
target/arm: Implement SVE2 saturating multiply-add high (indexed)

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-56-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 integer multiply-add (indexed)
Richard Henderson [Tue, 25 May 2021 01:03:20 +0000 (18:03 -0700)] 
target/arm: Implement SVE2 integer multiply-add (indexed)

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-55-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 integer multiply (indexed)
Richard Henderson [Tue, 25 May 2021 01:03:19 +0000 (18:03 -0700)] 
target/arm: Implement SVE2 integer multiply (indexed)

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-54-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Split out formats for 3 vectors + 1 index
Richard Henderson [Tue, 25 May 2021 01:03:18 +0000 (18:03 -0700)] 
target/arm: Split out formats for 3 vectors + 1 index

Used by FMLA and DOT, but will shortly be used more.
Split FMLA from FMLS to avoid an extra sub field;
similarly for SDOT from UDOT.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-53-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Split out formats for 2 vectors + 1 index
Richard Henderson [Tue, 25 May 2021 01:03:17 +0000 (18:03 -0700)] 
target/arm: Split out formats for 2 vectors + 1 index

Currently only used by FMUL, but will shortly be used more.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-52-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Pass separate addend to FCMLA helpers
Richard Henderson [Tue, 25 May 2021 01:03:16 +0000 (18:03 -0700)] 
target/arm: Pass separate addend to FCMLA helpers

For SVE, we potentially have a 4th argument coming from the
movprfx instruction.  Currently we do not optimize movprfx,
so the problem is not visible.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-51-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Pass separate addend to {U, S}DOT helpers
Richard Henderson [Tue, 25 May 2021 01:03:15 +0000 (18:03 -0700)] 
target/arm: Pass separate addend to {U, S}DOT helpers

For SVE, we potentially have a 4th argument coming from the
movprfx instruction.  Currently we do not optimize movprfx,
so the problem is not visible.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-50-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Use correct output type for gvec_sdot_*_b
Richard Henderson [Tue, 25 May 2021 01:03:14 +0000 (18:03 -0700)] 
target/arm: Use correct output type for gvec_sdot_*_b

The signed dot product routines produce a signed result.
Since we use -fwrapv, there is no functional change.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-49-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 SPLICE, EXT
Stephen Long [Tue, 25 May 2021 01:03:13 +0000 (18:03 -0700)] 
target/arm: Implement SVE2 SPLICE, EXT

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-48-richard.henderson@linaro.org
Message-Id: <20200423180347.9403-1-steplong@quicinc.com>
[rth: Rename the trans_* functions to *_sve2.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 FMMLA
Stephen Long [Tue, 25 May 2021 01:03:12 +0000 (18:03 -0700)] 
target/arm: Implement SVE2 FMMLA

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-47-richard.henderson@linaro.org
Message-Id: <20200422165503.13511-1-steplong@quicinc.com>
[rth: Fix indexing in helpers, expand macro to straight functions.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 gather load insns
Stephen Long [Tue, 25 May 2021 01:03:11 +0000 (18:03 -0700)] 
target/arm: Implement SVE2 gather load insns

Add decoding logic for SVE2 64-bit/32-bit gather non-temporal
load insns.

64-bit
* LDNT1SB
* LDNT1B (vector plus scalar)
* LDNT1SH
* LDNT1H (vector plus scalar)
* LDNT1SW
* LDNT1W (vector plus scalar)
* LDNT1D (vector plus scalar)

32-bit
* LDNT1SB
* LDNT1B (vector plus scalar)
* LDNT1SH
* LDNT1H (vector plus scalar)
* LDNT1W (vector plus scalar)

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-46-richard.henderson@linaro.org
Message-Id: <20200422152343.12493-1-steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 scatter store insns
Stephen Long [Tue, 25 May 2021 01:03:10 +0000 (18:03 -0700)] 
target/arm: Implement SVE2 scatter store insns

Add decoding logic for SVE2 64-bit/32-bit scatter non-temporal
store insns.

64-bit
* STNT1B (vector plus scalar)
* STNT1H (vector plus scalar)
* STNT1W (vector plus scalar)
* STNT1D (vector plus scalar)

32-bit
* STNT1B (vector plus scalar)
* STNT1H (vector plus scalar)
* STNT1W (vector plus scalar)

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-45-richard.henderson@linaro.org
Message-Id: <20200422141553.8037-1-steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 XAR
Richard Henderson [Tue, 25 May 2021 01:03:09 +0000 (18:03 -0700)] 
target/arm: Implement SVE2 XAR

In addition, use the same vector generator interface for AdvSIMD.
This fixes a bug in which the AdvSIMD insn failed to clear the
high bits of the SVE register.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-44-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 HISTCNT, HISTSEG
Stephen Long [Tue, 25 May 2021 01:03:08 +0000 (18:03 -0700)] 
target/arm: Implement SVE2 HISTCNT, HISTSEG

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-43-richard.henderson@linaro.org
Message-Id: <20200416173109.8856-1-steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 RSUBHNB, RSUBHNT
Stephen Long [Tue, 25 May 2021 01:03:07 +0000 (18:03 -0700)] 
target/arm: Implement SVE2 RSUBHNB, RSUBHNT

This completes the section 'SVE2 integer add/subtract narrow high part'

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-42-richard.henderson@linaro.org
Message-Id: <20200417162231.10374-5-steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 SUBHNB, SUBHNT
Stephen Long [Tue, 25 May 2021 01:03:06 +0000 (18:03 -0700)] 
target/arm: Implement SVE2 SUBHNB, SUBHNT

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-41-richard.henderson@linaro.org
Message-Id: <20200417162231.10374-4-steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 RADDHNB, RADDHNT
Stephen Long [Tue, 25 May 2021 01:03:05 +0000 (18:03 -0700)] 
target/arm: Implement SVE2 RADDHNB, RADDHNT

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-40-richard.henderson@linaro.org
Message-Id: <20200417162231.10374-3-steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 ADDHNB, ADDHNT
Stephen Long [Tue, 25 May 2021 01:03:04 +0000 (18:03 -0700)] 
target/arm: Implement SVE2 ADDHNB, ADDHNT

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-39-richard.henderson@linaro.org
Message-Id: <20200417162231.10374-2-steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 complex integer multiply-add
Richard Henderson [Tue, 25 May 2021 01:03:03 +0000 (18:03 -0700)] 
target/arm: Implement SVE2 complex integer multiply-add

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-38-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 integer multiply-add long
Richard Henderson [Tue, 25 May 2021 01:03:02 +0000 (18:03 -0700)] 
target/arm: Implement SVE2 integer multiply-add long

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-37-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 saturating multiply-add high
Richard Henderson [Tue, 25 May 2021 01:03:01 +0000 (18:03 -0700)] 
target/arm: Implement SVE2 saturating multiply-add high

SVE2 has two additional sizes of the operation and unlike NEON,
there is no saturation flag.  Create new entry points for SVE2
that do not set QC.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-36-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 saturating multiply-add long
Richard Henderson [Tue, 25 May 2021 01:03:00 +0000 (18:03 -0700)] 
target/arm: Implement SVE2 saturating multiply-add long

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-35-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 MATCH, NMATCH
Stephen Long [Tue, 25 May 2021 01:02:59 +0000 (18:02 -0700)] 
target/arm: Implement SVE2 MATCH, NMATCH

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-34-richard.henderson@linaro.org
Message-Id: <20200415145915.2859-1-steplong@quicinc.com>
[rth: Expanded comment for do_match2]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 bitwise ternary operations
Richard Henderson [Tue, 25 May 2021 01:02:58 +0000 (18:02 -0700)] 
target/arm: Implement SVE2 bitwise ternary operations

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-33-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 WHILERW, WHILEWR
Richard Henderson [Tue, 25 May 2021 01:02:57 +0000 (18:02 -0700)] 
target/arm: Implement SVE2 WHILERW, WHILEWR

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-32-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 WHILEGT, WHILEGE, WHILEHI, WHILEHS
Richard Henderson [Tue, 25 May 2021 01:02:56 +0000 (18:02 -0700)] 
target/arm: Implement SVE2 WHILEGT, WHILEGE, WHILEHI, WHILEHS

Rename the existing sve_while (less-than) helper to sve_whilel
to make room for a new sve_whileg helper for greater-than.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-31-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 SQSHRN, SQRSHRN
Richard Henderson [Tue, 25 May 2021 01:02:55 +0000 (18:02 -0700)] 
target/arm: Implement SVE2 SQSHRN, SQRSHRN

This completes the section "SVE2 bitwise shift right narrow".

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-30-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 UQSHRN, UQRSHRN
Richard Henderson [Tue, 25 May 2021 01:02:54 +0000 (18:02 -0700)] 
target/arm: Implement SVE2 UQSHRN, UQRSHRN

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-29-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 SQSHRUN, SQRSHRUN
Richard Henderson [Tue, 25 May 2021 01:02:53 +0000 (18:02 -0700)] 
target/arm: Implement SVE2 SQSHRUN, SQRSHRUN

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-28-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 SHRN, RSHRN
Richard Henderson [Tue, 25 May 2021 01:02:52 +0000 (18:02 -0700)] 
target/arm: Implement SVE2 SHRN, RSHRN

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-27-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 floating-point pairwise
Stephen Long [Tue, 25 May 2021 01:02:51 +0000 (18:02 -0700)] 
target/arm: Implement SVE2 floating-point pairwise

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Stephen Long <steplong@quicinc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-26-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 saturating extract narrow
Richard Henderson [Tue, 25 May 2021 01:02:50 +0000 (18:02 -0700)] 
target/arm: Implement SVE2 saturating extract narrow

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-25-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 integer absolute difference and accumulate
Richard Henderson [Tue, 25 May 2021 01:02:49 +0000 (18:02 -0700)] 
target/arm: Implement SVE2 integer absolute difference and accumulate

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-24-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 bitwise shift and insert
Richard Henderson [Tue, 25 May 2021 01:02:48 +0000 (18:02 -0700)] 
target/arm: Implement SVE2 bitwise shift and insert

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-23-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 bitwise shift right and accumulate
Richard Henderson [Tue, 25 May 2021 01:02:47 +0000 (18:02 -0700)] 
target/arm: Implement SVE2 bitwise shift right and accumulate

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-22-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 integer add/subtract long with carry
Richard Henderson [Tue, 25 May 2021 01:02:46 +0000 (18:02 -0700)] 
target/arm: Implement SVE2 integer add/subtract long with carry

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-21-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 integer absolute difference and accumulate long
Richard Henderson [Tue, 25 May 2021 01:02:45 +0000 (18:02 -0700)] 
target/arm: Implement SVE2 integer absolute difference and accumulate long

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
6 months agotarget/arm: Implement SVE2 complex integer add
Richard Henderson [Tue, 25 May 2021 01:02:44 +0000 (18:02 -0700)] 
target/arm: Implement SVE2 complex integer add

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20210525010358.152808-19-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>