qemu.git
7 years agoqcow2: Correct comment for realloc_refcount_block()
Max Reitz [Mon, 17 Mar 2014 22:04:51 +0000 (23:04 +0100)] 
qcow2: Correct comment for realloc_refcount_block()

Contrary to the comment describing this function's behavior, it does not
return 0 on success, but rather the offset of the newly allocated
cluster. This patch adjusts the comment accordingly to reflect the
actual behavior.

Signed-off-by: Max Reitz <mreitz@redhat.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
7 years agoqemu-io: Extended "--cmd" description in usage text
Maria Kustova [Tue, 18 Mar 2014 05:59:19 +0000 (09:59 +0400)] 
qemu-io: Extended "--cmd" description in usage text

It's not clear from the usage description that "--cmd" option accepts
its argument as a string, so any special symbols have to be quoted from
the shell.

Updates in usage text:
 - Specified parameter format for "--cmd" option.
 - Added an instruction how to get help for "--cmd" option.

Signed-off-by: Maria Kustova <maria.k@catit.be>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
7 years agoqemu-io-cmds: Fixed typo in example for writev.
Maria Kustova [Tue, 18 Mar 2014 05:59:17 +0000 (09:59 +0400)] 
qemu-io-cmds: Fixed typo in example for writev.

Signed-off-by: Maria Kustova <maria.k@catit.be>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
7 years agoblock: Add error handling to bdrv_invalidate_cache()
Kevin Wolf [Wed, 12 Mar 2014 14:59:16 +0000 (15:59 +0100)] 
block: Add error handling to bdrv_invalidate_cache()

If it returns an error, the migrated VM will not be started, but qemu
exits with an error message.

Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Juan Quintela <quintela@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Benoit Canet <benoit@irqsave.net>
7 years agoMerge remote-tracking branch 'remotes/kraxel/tags/pull-vnc-2' into staging
Peter Maydell [Tue, 18 Mar 2014 16:39:29 +0000 (16:39 +0000)] 
Merge remote-tracking branch 'remotes/kraxel/tags/pull-vnc-2' into staging

vnc: fix vmware VGA incompatiblities

# gpg: Signature made Tue 18 Mar 2014 07:23:10 GMT using RSA key ID D3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>"
# gpg:                 aka "Gerd Hoffmann <gerd@kraxel.org>"
# gpg:                 aka "Gerd Hoffmann (private) <kraxel@gmail.com>"

* remotes/kraxel/tags/pull-vnc-2:
  ui/vnc: fix vmware VGA incompatiblities

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7 years agoMerge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140317' into...
Peter Maydell [Tue, 18 Mar 2014 14:31:42 +0000 (14:31 +0000)] 
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140317' into staging

target-arm queue:
 * more A64 Neon instructions
 * fixes to reset CBAR values for A9 and A15 boards
 * fix accesses to PMCR register in -icount mode

# gpg: Signature made Mon 17 Mar 2014 22:04:52 GMT using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"

* remotes/pmaydell/tags/pull-target-arm-20140317: (30 commits)
  scripts/qemu-binfmt-conf.sh: Add AArch64 registration
  target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate)
  target-arm: A64: Implement FCVTXN
  target-arm: A64: Implement scalar saturating narrow ops
  target-arm: A64: Move handle_2misc_narrow function
  target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPE
  softfloat: export squash_input_denormal functions
  target-arm: A64: Implement FCVTZS, FCVTZU in the shift-imm categories
  target-arm: A64: Handle saturating left shifts SQSHL, SQSHLU, UQSHL
  exec-all.h: Increase MAX_OP_PER_INSTR for ARM A64 decoder
  target-arm: A64: Implement FRINT*
  target-arm: A64: Implement SRI
  target-arm: A64: Add FRECPX (reciprocal exponent)
  target-arm: A64: List unsupported shift-imm opcodes
  target-arm: A64: Implement FCVTL
  target-arm: A64: Implement FCVTN
  target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructions
  target-arm: A64: Implement SHLL, SHLL2
  target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALP
  target-arm: A64: Saturating and narrowing shift ops
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7 years agoui/vnc: fix vmware VGA incompatiblities
Peter Lieven [Mon, 17 Mar 2014 17:38:58 +0000 (18:38 +0100)] 
ui/vnc: fix vmware VGA incompatiblities

this fixes invalid rectangle updates observed after commit 12b316d
with the vmware VGA driver. The issues occured because the server
and client surface update seems to be out of sync at some points
and the max width of the surface is not dividable by
VNC_DIRTY_BITS_PER_PIXEL (16).

Reported-by: Serge Hallyn <serge.hallyn@ubuntu.com>
Signed-off-by: Peter Lieven <pl@kamp.de>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
7 years agoMerge remote-tracking branch 'remotes/borntraeger/tags/kvm-s390-20140317' into staging
Peter Maydell [Mon, 17 Mar 2014 22:31:32 +0000 (22:31 +0000)] 
Merge remote-tracking branch 'remotes/borntraeger/tags/kvm-s390-20140317' into staging

4 small patches:
- Fixing findings of valgrind regarding minor memory leaks:
  Currently we forget the pointer of qemu_allocate_irqs. Since we never
  free the irqs, this is not critical, but obviously not good programming
  style. While we are at it, we dont need the irq infrastructure for
  the sclp consoles.
- Handle new ELF error codes for BIOS loading

# gpg: Signature made Mon 17 Mar 2014 21:34:12 GMT using RSA key ID B5A61C7C
# gpg: Can't check signature: public key not found

* remotes/borntraeger/tags/kvm-s390-20140317:
  s390x/sclpconsole-lm: Fix and simplify irq setup
  s390x/sclpconsole: Fix and simplify interrupt injection
  s390x/cpu hotplug: Fix memory leak
  s390/ipl: Fix error path on BIOS loading

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7 years agoMerge remote-tracking branch 'remotes/rth/tcg-v8p-2' into staging
Peter Maydell [Mon, 17 Mar 2014 22:15:52 +0000 (22:15 +0000)] 
Merge remote-tracking branch 'remotes/rth/tcg-v8p-2' into staging

* remotes/rth/tcg-v8p-2:
  tcg-sparc: Convert to new ldst opcodes
  tcg-sparc: Convert to new ldst helpers
  tcg-sparc: Tidy tcg_out_tlb_load interface
  tcg-sparc: Use TCGMemOp within qemu_ldst routines
  tcg-sparc: Improve tcg_out_movi
  tcg-sparc: Dont handle constant arguments to ext32 ops
  tcg-sparc: Don't handle remainder
  tcg-sparc: Use intptr_t as appropriate
  tcg-sparc: Tidy call+jump patterns
  tcg-sparc: Fix tlb read
  tcg-sparc: Fix ld64 for 32-bit mode

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7 years agos390x/sclpconsole-lm: Fix and simplify irq setup
Christian Borntraeger [Mon, 10 Mar 2014 13:19:52 +0000 (14:19 +0100)] 
s390x/sclpconsole-lm: Fix and simplify irq setup

valgrind complains about a memory leak in irq setup of sclpconsole:

==42117== 8 bytes in 1 blocks are definitely lost in loss record 89of 833
==42117==    at 0x4031AFE: malloc (vg_replace_malloc.c:292)
==42117==    by 0x8022F855: malloc_and_trace (vl.c:2715)
==42117==    by 0x4145569: g_malloc (in /usr/lib64/libglib-2.0.so.0.3400.2)
==42117==    by 0x800F696D: qemu_extend_irqs (irq.c:51)
==42117==    by 0x800F6AF7: qemu_allocate_irqs (irq.c:68)
==42117==    by 0x800F5685: console_init (sclpconsole.c:235)
==42117==    by 0x80297C79: event_realize (event-facility.c:386)
==42117==    by 0x80105071: device_set_realized (qdev.c:693)
==42117==    by 0x801CDC4B: property_set_bool (object.c:1337)
 ==42117==    by 0x801CBD7F: object_property_set (object.c:819)
[...]

We dont need the indirection of an qemu irq to inject an slcp interrupt.
Fixes a valgrind error and makes the code simpler.

Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
Acked-by: Heinz Graalfs <graalfs@linux.vnet.ibm.com>
7 years agos390x/sclpconsole: Fix and simplify interrupt injection
Christian Borntraeger [Mon, 10 Mar 2014 13:17:04 +0000 (14:17 +0100)] 
s390x/sclpconsole: Fix and simplify interrupt injection

valgrind complains about a memory leak in irq setup of sclpconsole:

==42117== 8 bytes in 1 blocks are definitely lost in loss record 89 of 833
==42117==    at 0x4031AFE: malloc (vg_replace_malloc.c:292)
==42117==    by 0x8022F855: malloc_and_trace (vl.c:2715)
==42117==    by 0x4145569: g_malloc (in /usr/lib64/libglib-2.0.so.0.3400.2)
==42117==    by 0x800F696D: qemu_extend_irqs (irq.c:51)
==42117==    by 0x800F6AF7: qemu_allocate_irqs (irq.c:68)
==42117==    by 0x800F5685: console_init (sclpconsole.c:235)
==42117==    by 0x80297C79: event_realize (event-facility.c:386)
==42117==    by 0x80105071: device_set_realized (qdev.c:693)
==42117==    by 0x801CDC4B: property_set_bool (object.c:1337)
==42117==    by 0x801CBD7F: object_property_set (object.c:819)
[...]

Turns out that we actually dont need the indirection, so trigger the
sclp interrupt directly.

Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
Acked-by: Heinz Graalfs <graalfs@linux.vnet.ibm.com>
7 years agos390x/cpu hotplug: Fix memory leak
Christian Borntraeger [Mon, 10 Mar 2014 14:03:16 +0000 (15:03 +0100)] 
s390x/cpu hotplug: Fix memory leak

valgrind complains about the following:
==42117== 8 bytes in 1 blocks are definitely lost in loss record 88 of 833
==42117==    at 0x4031AFE: malloc (vg_replace_malloc.c:292)
==42117==    by 0x8022F855: malloc_and_trace (vl.c:2715)
==42117==    by 0x4145569: g_malloc (in /usr/lib64/libglib-2.0.so.0.3400.2)
==42117==    by 0x800F696D: qemu_extend_irqs (irq.c:51)
==42117==    by 0x800F6AF7: qemu_allocate_irqs (irq.c:68)
==42117==    by 0x8029FA4B: irq_cpu_hotplug_init (sclpcpu.c:84)
==42117==    by 0x80297C79: event_realize (event-facility.c:386)
==42117==    by 0x80105071: device_set_realized (qdev.c:693)
[...]

Right it is. Don't drop the pointer of the irq.

Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
Reviewed-by: Jason J. Herne <jjherne@us.ibm.com>
7 years agos390/ipl: Fix error path on BIOS loading
Christian Borntraeger [Fri, 14 Mar 2014 12:38:57 +0000 (13:38 +0100)] 
s390/ipl: Fix error path on BIOS loading

commit 18674b26788a9e47f1157170234e32ece2044367
(elf-loader: add more return codes) enabled the elf loader to return
other errors than -1.

Lets also handle that case for our "BIOS" on s390.

Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
CC: Alexey Kardashevskiy <aik@ozlabs.ru>
CC: Alexander Graf <agraf@suse.de>
7 years agotcg-sparc: Convert to new ldst opcodes
Richard Henderson [Tue, 10 Sep 2013 02:51:21 +0000 (19:51 -0700)] 
tcg-sparc: Convert to new ldst opcodes

Signed-off-by: Richard Henderson <rth@twiddle.net>
7 years agotcg-sparc: Convert to new ldst helpers
Richard Henderson [Wed, 5 Mar 2014 17:42:08 +0000 (09:42 -0800)] 
tcg-sparc: Convert to new ldst helpers

All of the helpers with the explicit big/little endian option
require the return address as a parameter.  Acquire this via
a trampoline.

Move the load of areg0 into the trampoline.

Signed-off-by: Richard Henderson <rth@twiddle.net>
7 years agotcg-sparc: Tidy tcg_out_tlb_load interface
Richard Henderson [Fri, 6 Sep 2013 22:01:14 +0000 (15:01 -0700)] 
tcg-sparc: Tidy tcg_out_tlb_load interface

Pass address registers explicitly, rather than as indicies of args[].
It's two argument registers either way.  Use more TCGReg as appropriate.

Signed-off-by: Richard Henderson <rth@twiddle.net>
7 years agotcg-sparc: Use TCGMemOp within qemu_ldst routines
Richard Henderson [Wed, 4 Sep 2013 03:12:01 +0000 (20:12 -0700)] 
tcg-sparc: Use TCGMemOp within qemu_ldst routines

Signed-off-by: Richard Henderson <rth@twiddle.net>
7 years agotcg-sparc: Improve tcg_out_movi
Richard Henderson [Tue, 10 Sep 2013 04:07:09 +0000 (21:07 -0700)] 
tcg-sparc: Improve tcg_out_movi

If bits 31:13 are zero, reduce the insn count by one.

Signed-off-by: Richard Henderson <rth@twiddle.net>
7 years agotcg-sparc: Dont handle constant arguments to ext32 ops
Richard Henderson [Tue, 4 Mar 2014 23:24:04 +0000 (15:24 -0800)] 
tcg-sparc: Dont handle constant arguments to ext32 ops

Signed-off-by: Richard Henderson <rth@twiddle.net>
7 years agotcg-sparc: Don't handle remainder
Richard Henderson [Wed, 21 Aug 2013 02:22:15 +0000 (19:22 -0700)] 
tcg-sparc: Don't handle remainder

The generic fallback is exactly what we implemented.

Signed-off-by: Richard Henderson <rth@twiddle.net>
7 years agotcg-sparc: Use intptr_t as appropriate
Richard Henderson [Wed, 21 Aug 2013 01:31:45 +0000 (18:31 -0700)] 
tcg-sparc: Use intptr_t as appropriate

Signed-off-by: Richard Henderson <rth@twiddle.net>
7 years agotcg-sparc: Tidy call+jump patterns
Richard Henderson [Wed, 21 Aug 2013 01:25:38 +0000 (18:25 -0700)] 
tcg-sparc: Tidy call+jump patterns

Signed-off-by: Richard Henderson <rth@twiddle.net>
7 years agotcg-sparc: Fix tlb read
Richard Henderson [Sat, 7 Sep 2013 00:19:12 +0000 (17:19 -0700)] 
tcg-sparc: Fix tlb read

We were computing the full address into %o0 and then not using it.
Adjust some of the computation to rely less on having to pull immediate
values into registers.

Signed-off-by: Richard Henderson <rth@twiddle.net>
7 years agotcg-sparc: Fix ld64 for 32-bit mode
Richard Henderson [Fri, 6 Sep 2013 21:20:00 +0000 (14:20 -0700)] 
tcg-sparc: Fix ld64 for 32-bit mode

Since were not using an annulled branch, we need to put a nop
in the delay slot.

Signed-off-by: Richard Henderson <rth@twiddle.net>
7 years agoscripts/qemu-binfmt-conf.sh: Add AArch64 registration
Peter Maydell [Mon, 17 Mar 2014 16:31:53 +0000 (16:31 +0000)] 
scripts/qemu-binfmt-conf.sh: Add AArch64 registration

Add the binfmt-misc magic needed to register QEMU for handling AArch64
ELF binaries.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1394822294-14837-26-git-send-email-peter.maydell@linaro.org

7 years agotarget-arm: A64: Add [UF]RSQRTE (reciprocal root estimate)
Alex Bennée [Mon, 17 Mar 2014 16:31:53 +0000 (16:31 +0000)] 
target-arm: A64: Add [UF]RSQRTE (reciprocal root estimate)

This adds support for [UF]RSQRTE instructions. It utilises the existing
NEON helpers with some changes. The changes include an explicit passing
of fpstatus (so the correct one is used between arm32 and aarch64),
denormilzation, more correct error handling and also proper scaling of
the fraction going into the estimate.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1394822294-14837-25-git-send-email-peter.maydell@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7 years agotarget-arm: A64: Implement FCVTXN
Peter Maydell [Mon, 17 Mar 2014 16:31:53 +0000 (16:31 +0000)] 
target-arm: A64: Implement FCVTXN

Implement the FCVTXN operation, which does a narrowing fp precision
conversion using the "round to odd" (von Neumann) mode. This can
conveniently be implemented as "do operation using round to zero;
then set the LSB of the mantissa to 1 if the Inexact flag was set".

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1394822294-14837-24-git-send-email-peter.maydell@linaro.org

7 years agotarget-arm: A64: Implement scalar saturating narrow ops
Alex Bennée [Mon, 17 Mar 2014 16:31:52 +0000 (16:31 +0000)] 
target-arm: A64: Implement scalar saturating narrow ops

This completes the set of integer narrowing saturating ops including:
     SQXTN, SQXTN2
     SQXTUN, SQXTUN2
     UQXTN, UQXTN2

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1394822294-14837-23-git-send-email-peter.maydell@linaro.org

7 years agotarget-arm: A64: Move handle_2misc_narrow function
Alex Bennée [Mon, 17 Mar 2014 16:31:52 +0000 (16:31 +0000)] 
target-arm: A64: Move handle_2misc_narrow function

Move the handle_2misc_narrow() function up the file so that it can
be called from disas_simd_scalar_two_reg_misc().

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1394822294-14837-22-git-send-email-peter.maydell@linaro.org

7 years agotarget-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPE
Alex Bennée [Mon, 17 Mar 2014 16:31:52 +0000 (16:31 +0000)] 
target-arm: A64: Implement AdvSIMD reciprocal estimate insns URECPE, FRECPE

Implement URECPE and FRECPE instructions in both scalar and vector forms.
The actual reciprocal estimate function is shared with the A32/T32 Neon
code. However in A64 we aren't using the Neon "standard FPSCR value"
so extra checks are necessary to handle non-squashed denormal inputs
which can never happen for A32/T32. Calling conventions for the helpers
are thus modified to pass the fpst directly; we mark the helpers as
TCG_CALL_NO_RWG since we're changing the declarations anyway.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1394822294-14837-21-git-send-email-peter.maydell@linaro.org

7 years agosoftfloat: export squash_input_denormal functions
Alex Bennée [Mon, 17 Mar 2014 16:31:51 +0000 (16:31 +0000)] 
softfloat: export squash_input_denormal functions

I need these available outside of softfloat for some of the reciprocal
processing in aarch64 helper functions.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1394822294-14837-20-git-send-email-peter.maydell@linaro.org

7 years agotarget-arm: A64: Implement FCVTZS, FCVTZU in the shift-imm categories
Peter Maydell [Mon, 17 Mar 2014 16:31:51 +0000 (16:31 +0000)] 
target-arm: A64: Implement FCVTZS, FCVTZU in the shift-imm categories

Implement FCVTZS and FCVTZU in the shift-imm and scalar-shift-imm
categories; this completes the implementation of those two groups.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1394822294-14837-19-git-send-email-peter.maydell@linaro.org

7 years agotarget-arm: A64: Handle saturating left shifts SQSHL, SQSHLU, UQSHL
Peter Maydell [Mon, 17 Mar 2014 16:31:51 +0000 (16:31 +0000)] 
target-arm: A64: Handle saturating left shifts SQSHL, SQSHLU, UQSHL

Implement the saturating left shift instructions SQSHL, SQSHLU
and UQSHL for the scalar-shift-imm and shift-imm categories.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1394822294-14837-18-git-send-email-peter.maydell@linaro.org

7 years agoexec-all.h: Increase MAX_OP_PER_INSTR for ARM A64 decoder
Peter Maydell [Mon, 17 Mar 2014 16:31:51 +0000 (16:31 +0000)] 
exec-all.h: Increase MAX_OP_PER_INSTR for ARM A64 decoder

The ARM A64 decoder's worst case number of TCG ops per instruction
is 266 (for insn 0x4c800000, a post-indexed ST4 multiple-structures
store). Raise the MAX_OP_PER_INSTR define accordingly.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1394822294-14837-17-git-send-email-peter.maydell@linaro.org

7 years agotarget-arm: A64: Implement FRINT*
Peter Maydell [Mon, 17 Mar 2014 16:31:50 +0000 (16:31 +0000)] 
target-arm: A64: Implement FRINT*

Implement the FRINT* round-to-integral operations from
the 2-reg-misc category.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1394822294-14837-16-git-send-email-peter.maydell@linaro.org

7 years agotarget-arm: A64: Implement SRI
Peter Maydell [Mon, 17 Mar 2014 16:31:50 +0000 (16:31 +0000)] 
target-arm: A64: Implement SRI

Implement SRI (shift right and insert).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1394822294-14837-15-git-send-email-peter.maydell@linaro.org

7 years agotarget-arm: A64: Add FRECPX (reciprocal exponent)
Alex Bennée [Mon, 17 Mar 2014 16:31:50 +0000 (16:31 +0000)] 
target-arm: A64: Add FRECPX (reciprocal exponent)

These are fairly simple exponent only estimation functions using helpers.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1394822294-14837-14-git-send-email-peter.maydell@linaro.org

7 years agotarget-arm: A64: List unsupported shift-imm opcodes
Peter Maydell [Mon, 17 Mar 2014 16:31:50 +0000 (16:31 +0000)] 
target-arm: A64: List unsupported shift-imm opcodes

Add the remaining unsupported opcodes to the decode switches
for the shift-imm and scalar shift-imm categories so we can
see what is still to be implemented.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1394822294-14837-13-git-send-email-peter.maydell@linaro.org

7 years agotarget-arm: A64: Implement FCVTL
Peter Maydell [Mon, 17 Mar 2014 16:31:49 +0000 (16:31 +0000)] 
target-arm: A64: Implement FCVTL

Implement FCVTL, the only instruction in the 2-reg-misc group
which widens from size to 2*size elements.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1394822294-14837-12-git-send-email-peter.maydell@linaro.org

7 years agotarget-arm: A64: Implement FCVTN
Peter Maydell [Mon, 17 Mar 2014 16:31:49 +0000 (16:31 +0000)] 
target-arm: A64: Implement FCVTN

Implement FCVTN (narrowing fp-to-fp conversions) from the SIMD
2-reg-misc category.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1394822294-14837-11-git-send-email-peter.maydell@linaro.org

7 years agotarget-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructions
Peter Maydell [Mon, 17 Mar 2014 16:31:49 +0000 (16:31 +0000)] 
target-arm: A64: Implement FCVT[NMAPZ][SU] SIMD instructions

Implement the floating-point-to-integer conversion instructions
FCVT[NMAPZ][SU] in the 2-reg-misc and scalar-2-reg-misc
categories.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1394822294-14837-10-git-send-email-peter.maydell@linaro.org

7 years agotarget-arm: A64: Implement SHLL, SHLL2
Peter Maydell [Mon, 17 Mar 2014 16:31:49 +0000 (16:31 +0000)] 
target-arm: A64: Implement SHLL, SHLL2

Implement the SHLL and SHLL2 instructions from the 2-reg-misc
category.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1394822294-14837-9-git-send-email-peter.maydell@linaro.org

7 years agotarget-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALP
Peter Maydell [Mon, 17 Mar 2014 16:31:48 +0000 (16:31 +0000)] 
target-arm: A64: Implement SADDLP, UADDLP, SADALP, UADALP

Implement the SADDLP, UADDLP, SADALP and UADALP instructions
in the SIMD 2-reg misc category.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1394822294-14837-8-git-send-email-peter.maydell@linaro.org

7 years agotarget-arm: A64: Saturating and narrowing shift ops
Alex Bennée [Mon, 17 Mar 2014 16:31:48 +0000 (16:31 +0000)] 
target-arm: A64: Saturating and narrowing shift ops

This implements the remaining [US][Q][R]SHR[U][N][2] opcodes, which are
saturating and narrowing shift right operations. These are used in
things like libav. Note signed shifts can have an "unsigned" saturating
narrow operation which will floor negative values.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1394822294-14837-7-git-send-email-peter.maydell@linaro.org
[PMM: Added the scalar encodings, style tweaks]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7 years agotarget-arm: A64: Add remaining CLS/Z vector ops
Alex Bennée [Mon, 17 Mar 2014 16:31:48 +0000 (16:31 +0000)] 
target-arm: A64: Add remaining CLS/Z vector ops

Implement the CLS, CLZ operations in the 2-reg-misc category.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1394822294-14837-6-git-send-email-peter.maydell@linaro.org

7 years agotarget-arm: A64: Add FSQRT to C3.6.17 (two misc)
Alex Bennée [Mon, 17 Mar 2014 16:31:47 +0000 (16:31 +0000)] 
target-arm: A64: Add FSQRT to C3.6.17 (two misc)

Implement FSQRT in the two-reg-misc category.
GCC uses this instruction form.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1394822294-14837-5-git-send-email-peter.maydell@linaro.org

7 years agotarget-arm: A64: Add last AdvSIMD Integer to FP ops
Alex Bennée [Mon, 17 Mar 2014 16:31:47 +0000 (16:31 +0000)] 
target-arm: A64: Add last AdvSIMD Integer to FP ops

This adds the remaining [US]CVTF operations to the SIMD
shift-immediate, scalar-shift-immediate, two-reg-misc and
scalar-two-reg-misc groups of opcodes.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1394822294-14837-4-git-send-email-peter.maydell@linaro.org
[PMM: added scalar 2-misc and scalar-shift-imm encodings]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7 years agotarget-arm: A64: Fix bug in add_sub_ext handling of rn
Alex Bennée [Mon, 17 Mar 2014 16:31:47 +0000 (16:31 +0000)] 
target-arm: A64: Fix bug in add_sub_ext handling of rn

rn == 31 always means SP (not XZR) whether an add_sub_ext
instruction is setting the flags or not; only rd has behaviour
dependent on whether we are setting flags.

Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1394822294-14837-3-git-send-email-peter.maydell@linaro.org

7 years agotarget-arm: A64: Implement PMULL instruction
Peter Maydell [Mon, 17 Mar 2014 16:31:47 +0000 (16:31 +0000)] 
target-arm: A64: Implement PMULL instruction

Implement the PMULL instruction; this is the last unimplemented insn
in the three-reg-diff group.

Note that PMULL with size 3 is considered part of the AES part
of the crypto extensions (see the ID_AA64ISAR0_EL1 register definition
in the v8 ARM ARM), so it isn't necessary to burn an extra feature
bit on it, even though we're using more feature bits than a single
"crypto extension present/not present" toggle.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1394822294-14837-2-git-send-email-peter.maydell@linaro.org

7 years agotarget-arm: Add ARM_CP_IO notation to PMCR reginfo
Peter Maydell [Mon, 17 Mar 2014 16:31:46 +0000 (16:31 +0000)] 
target-arm: Add ARM_CP_IO notation to PMCR reginfo

Now that the PMCR writefn makes timer accesses, its reginfo needs
the ARM_CP_IO flag, so that icount mode works correctly. (Fixes
the bug accidentally introduced in commit 7c2cb42b).

Reported-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1394908291-16546-1-git-send-email-peter.maydell@linaro.org

7 years agovirt: Set reset-cbar on CPUs
Peter Maydell [Mon, 17 Mar 2014 16:31:46 +0000 (16:31 +0000)] 
virt: Set reset-cbar on CPUs

Set the reset-cbar property on CPUs used by the virt board,
if they have it. This isn't necessary for correct functioning
under Linux (since the A9 isn't a valid CPU for the virt board),
but it is the correct behaviour.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 1394462692-8871-5-git-send-email-peter.maydell@linaro.org

7 years agoexynos4210: Set reset-cbar property of Cortex-A9 CPUs
Peter Maydell [Mon, 17 Mar 2014 16:31:46 +0000 (16:31 +0000)] 
exynos4210: Set reset-cbar property of Cortex-A9 CPUs

Set the reset-cbar property of the Exynos4210 SoC's Cortex-A9
CPUs, so that Linux doesn't misrecognize them as a broken
uniprocessor SoC.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 1394462692-8871-4-git-send-email-peter.maydell@linaro.org

7 years agorealview-pbx-a9: Set reset-cbar property for CPUs
Peter Maydell [Mon, 17 Mar 2014 16:31:45 +0000 (16:31 +0000)] 
realview-pbx-a9: Set reset-cbar property for CPUs

If the CPU is a Cortex-A9 then we should set its reset-cbar property
so that the guest can read the correct PERIPHBASE/CBAR register value;
newer versions of the Linux kernel (as of commit bc41b8724 in 3.12)
will otherwise assume the CPU is a buggy single core A9 SoC. The
realview-pbx-a9 is the only one of the cluster of boards in realview.c
which works with the Cortex-A9 (ie which gets an a9mpcore_priv device);
make sure it also has reset-cbar set correctly.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 1394462692-8871-3-git-send-email-peter.maydell@linaro.org

7 years agovexpress: Set reset-cbar property for CPUs
Peter Maydell [Mon, 17 Mar 2014 16:31:45 +0000 (16:31 +0000)] 
vexpress: Set reset-cbar property for CPUs

Newer versions of the Linux kernel (as of commit bc41b8724 in 3.12)
now assume that if the CPU is a Cortex-A9 and the reset value of the
PERIPHBASE/CBAR register is zero then the CPU is a specific buggy
single core A9 SoC, and will not try to start other cores. Since we
now have a CPU property for the reset value of the CBAR, we can
just fix the vexpress board model to correctly set CBAR so SMP
works again. To avoid duplicate boilerplate code in both the A9
and A15 daughterboard init functions, we split out the CPU and
private memory region init to its own function.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reported-by: Rob Herring <rob.herring@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 1394462692-8871-2-git-send-email-peter.maydell@linaro.org

7 years agoMerge remote-tracking branch 'remotes/kraxel/tags/pull-gtk-3' into staging
Peter Maydell [Mon, 17 Mar 2014 15:51:57 +0000 (15:51 +0000)] 
Merge remote-tracking branch 'remotes/kraxel/tags/pull-gtk-3' into staging

gtk: warp bugfixes.
gtk: Allow to activate grab-on-hover from the command line

# gpg: Signature made Mon 17 Mar 2014 13:35:35 GMT using RSA key ID D3E87138
# gpg: Good signature from "Gerd Hoffmann (work) <kraxel@redhat.com>"
# gpg:                 aka "Gerd Hoffmann <gerd@kraxel.org>"
# gpg:                 aka "Gerd Hoffmann (private) <kraxel@gmail.com>"

* remotes/kraxel/tags/pull-gtk-3:
  gtk: Don't warp absolute pointer
  gtk: Fix mouse warping with gtk3
  gtk: Allow to activate grab-on-hover from the command line

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7 years agogtk: Don't warp absolute pointer
Cole Robinson [Thu, 13 Mar 2014 19:30:24 +0000 (15:30 -0400)] 
gtk: Don't warp absolute pointer

This matches the behavior of SDL, and makes the mouse usable when
using -display gtk -vga qxl

https://bugzilla.redhat.com/show_bug.cgi?id=1051724
Signed-off-by: Cole Robinson <crobinso@redhat.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
7 years agogtk: Fix mouse warping with gtk3
Cole Robinson [Thu, 13 Mar 2014 19:30:23 +0000 (15:30 -0400)] 
gtk: Fix mouse warping with gtk3

We were using the wrong coordinates, this fixes things to match the
original gtk2 implementation.

You can see this error in action by using -vga qxl, however even after this
patch the mouse warps in small increments up and to the left, -7x and -3y
pixels at a time, until the pointer is warped off the widget. I think it's
a qxl bug, but the next patch covers it up.

Signed-off-by: Cole Robinson <crobinso@redhat.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
7 years agogtk: Allow to activate grab-on-hover from the command line
Jan Kiszka [Wed, 12 Mar 2014 07:33:50 +0000 (08:33 +0100)] 
gtk: Allow to activate grab-on-hover from the command line

As long as we have no persistent GTK configuration, this allows to
enable the useful grab-on-hover feature already when starting the VM.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
[ kraxel: fix warning with CONFIG_GTK=n ]

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
7 years agoMerge remote-tracking branch 'remotes/bonzini/fixes-for-2.0' into staging
Peter Maydell [Mon, 17 Mar 2014 13:05:48 +0000 (13:05 +0000)] 
Merge remote-tracking branch 'remotes/bonzini/fixes-for-2.0' into staging

* remotes/bonzini/fixes-for-2.0:
  vl.c: Output error on invalid machine type
  target-alpha: fix subl and s8subl indentation
  qemu-nbd: Fix coverity issues
  rules.mak: Fix per object libs extraction

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7 years agovl.c: Output error on invalid machine type
Miroslav Rezanina [Fri, 14 Mar 2014 12:06:54 +0000 (13:06 +0100)] 
vl.c: Output error on invalid machine type

Output error message using qemu's error_report() function when user
provides the invalid machine type on the command line. This also saves
time to find what issue is when you downgrade from one version of qemu
to another that doesn't support required machine type yet (the version
user downgraded to have to have this patch applied too, of course).

Signed-off-by: Miroslav Rezanina <mrezanin@redhat.com>
[Replace printf with error_printf, suggested by Markus Armbruster. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
7 years agotarget-alpha: fix subl and s8subl indentation
Paolo Bonzini [Sat, 15 Mar 2014 18:33:15 +0000 (19:33 +0100)] 
target-alpha: fix subl and s8subl indentation

Two missing braces, one close and one open, fabulously let the code
compile.

Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
7 years agoqemu-nbd: Fix coverity issues
Paolo Bonzini [Fri, 14 Mar 2014 17:10:54 +0000 (18:10 +0100)] 
qemu-nbd: Fix coverity issues

There are two issues in qemu-nbd: a missing return value check after
calling accept(), and file descriptor leaks in nbd_client_thread.

Reviewed-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
7 years agorules.mak: Fix per object libs extraction
Fam Zheng [Fri, 14 Mar 2014 02:21:05 +0000 (10:21 +0800)] 
rules.mak: Fix per object libs extraction

Don't sort the extracted options, sort the objects.

Reported-by: Christian Mahnke <cmahnke@googlemail.com>
Signed-off-by: Fam Zheng <famz@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
7 years agoMakefile: Fix "make clean"
Fam Zheng [Mon, 17 Mar 2014 01:35:22 +0000 (09:35 +0800)] 
Makefile: Fix "make clean"

This fixes a dangerous bug: "make clean" after "make distclean" will
delete every single file including those under .git, if you do in-tree
build!

Rationale: A first "make distclean" will unset $(DSOSUF), a following
"make distclean" or "make clean" will find all the files and delete it.

Fix it by explicitly typing the file extensions here, and combine
multiple find invocations into one.

Signed-off-by: Fam Zheng <famz@redhat.com>
Message-id: 1395020122-4957-1-git-send-email-famz@redhat.com
Reviewed-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7 years agoMerge remote-tracking branch 'remotes/mjt/tags/trivial-patches-2014-03-15' into staging
Peter Maydell [Sat, 15 Mar 2014 18:22:10 +0000 (18:22 +0000)] 
Merge remote-tracking branch 'remotes/mjt/tags/trivial-patches-2014-03-15' into staging

trivial patches for 2014-03-15

# gpg: Signature made Sat 15 Mar 2014 09:54:30 GMT using RSA key ID 74F0C838
# gpg: Good signature from "Michael Tokarev <mjt@tls.msk.ru>"
# gpg:                 aka "Michael Tokarev <mjt@corpit.ru>"
# gpg:                 aka "Michael Tokarev <mjt@debian.org>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6EE1 95D1 886E 8FFB 810D  4324 457C E0A0 8044 65C5
#      Subkey fingerprint: E190 8639 3B10 B51B AC2C  8B73 5253 C5AD 74F0 C838

* remotes/mjt/tags/trivial-patches-2014-03-15:
  FSL eTSEC: Fix typo in rx ring
  scripts/make-release: Don't distribute .git directories
  configure: Don't use __int128_t for clang versions before 3.2
  audio: Add 'static' attributes to several variables
  tests: Fix 'make test' for i686 hosts (build regression)
  misc: Fix typos in comments
  Add qga/qapi-generated to .gitignore
  hw/timer/grlib_gptimer: Avoid integer overflows
  .travis.yml: add IRC notifications for build failures
  .travis.yml: trivial whitespace fixup
  .travis.yml: re-enable lttng user space trace test
  .travis.yml: add a new build target with non-core devlibs
  sasl: Avoid 'Could not find keytab file' in syslog

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7 years agoMerge remote-tracking branch 'remotes/rth/tcg-aarch-6-2' into staging
Peter Maydell [Sat, 15 Mar 2014 18:03:15 +0000 (18:03 +0000)] 
Merge remote-tracking branch 'remotes/rth/tcg-aarch-6-2' into staging

* remotes/rth/tcg-aarch-6-2:
  tcg-aarch64: Introduce tcg_out_insn_3405
  tcg-aarch64: Support div, rem
  tcg-aarch64: Support muluh, mulsh
  tcg-aarch64: Support add2, sub2
  tcg-aarch64: Support deposit
  tcg-aarch64: Use tcg_out_insn for setcond
  tcg-aarch64: Support movcond
  tcg-aarch64: Support andc, orc, eqv, not, neg
  tcg-aarch64: Handle constant operands to and, or, xor
  tcg-aarch64: Handle constant operands to add, sub, and compare
  tcg-aarch64: Implement mov with tcg_out_insn
  tcg-aarch64: Introduce tcg_out_insn_3401
  tcg-aarch64: Convert shift insns to tcg_out_insn
  tcg-aarch64: Introduce tcg_out_insn

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7 years agoFSL eTSEC: Fix typo in rx ring
Fabien Chouteau [Fri, 14 Mar 2014 16:51:41 +0000 (17:51 +0100)] 
FSL eTSEC: Fix typo in rx ring

Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
7 years agoscripts/make-release: Don't distribute .git directories
Cole Robinson [Fri, 14 Mar 2014 16:49:13 +0000 (12:49 -0400)] 
scripts/make-release: Don't distribute .git directories

[crobinso@localhost qemu-2.0.0-rc0]$ find . -name .git
./dtc/.git
./pixman/.git

This is already done for the rom submodules.

https://bugs.launchpad.net/qemu/+bug/1224414
Signed-off-by: Cole Robinson <crobinso@redhat.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
7 years agoconfigure: Don't use __int128_t for clang versions before 3.2
Stefan Weil [Fri, 7 Mar 2014 09:43:38 +0000 (10:43 +0100)] 
configure: Don't use __int128_t for clang versions before 3.2

Those versions don't fully support __int128_t.

Cc: qemu-stable@nongnu.org
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
7 years agoaudio: Add 'static' attributes to several variables
Stefan Weil [Wed, 5 Mar 2014 21:21:32 +0000 (22:21 +0100)] 
audio: Add 'static' attributes to several variables

Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
7 years agotests: Fix 'make test' for i686 hosts (build regression)
Stefan Weil [Fri, 7 Mar 2014 10:11:22 +0000 (11:11 +0100)] 
tests: Fix 'make test' for i686 hosts (build regression)

'make test' is broken at least since commit
baacf04799ace72a9c735dd9306a1ceaf305e7cf. Several source files were moved
to util/, and some of them there split, so add the missing prefix and new
files to fix the compiler and linker errors.

There remain more issues, but these changes allow running the test on a
Linux i686 host.

Cc: qemu-stable@nongnu.org
Signed-off-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
7 years agomisc: Fix typos in comments
Stefan Weil [Fri, 7 Mar 2014 18:48:59 +0000 (19:48 +0100)] 
misc: Fix typos in comments

Codespell found and fixed these new typos:

* doesnt -> doesn't
* funtion -> function
* perfomance -> performance
* remaing -> remaining

A coding style issue (line too long) was fixed manually.

Signed-off-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
7 years agoAdd qga/qapi-generated to .gitignore
Gabriel L. Somlo [Mon, 10 Mar 2014 18:08:59 +0000 (14:08 -0400)] 
Add qga/qapi-generated to .gitignore

The folder "qga/qapi-generated" shows up after building QEMU, and
gets in the way during e.g. "git add ."; Add it to .gitignore to
keep it from accidentally ending up in the wrong place.

Signed-off-by: Gabriel Somlo <somlo@cmu.edu>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
7 years agohw/timer/grlib_gptimer: Avoid integer overflows
Sebastian Huber [Sun, 16 Feb 2014 11:12:38 +0000 (12:12 +0100)] 
hw/timer/grlib_gptimer: Avoid integer overflows

The GPTIMER uses 32-bit registers.  Use a 64-bit operation to get the
ptimer count, otherwise we end up with a count of 0 for GPTIMER counter
values of 0xffffffff.

Use the GPTIMER counter value for tracing to avoid an overflow of the
32-bit value passed to trace_grlib_gptimer_enable().

Reviewed-by: Fabien Chouteau <chouteau@adacore.com>
Signed-off-by: Sebastian Huber <sebastian.huber@embedded-brains.de>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
7 years ago.travis.yml: add IRC notifications for build failures
Alex Bennée [Wed, 12 Mar 2014 14:13:53 +0000 (14:13 +0000)] 
.travis.yml: add IRC notifications for build failures

I'm trying to avoid spamming the IRC channel (not overly likely as
builds take a while). So failure will always be reported but if the
build continues to work then the IRC notifications will be quiet.

Note any GitHub based repository with Travis enabled will use this
notification. If it proves to be too spammy we may want to ask users not
to use Travis themselves although this seems sub-optimal.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
7 years ago.travis.yml: trivial whitespace fixup
Alex Bennée [Wed, 12 Mar 2014 14:13:52 +0000 (14:13 +0000)] 
.travis.yml: trivial whitespace fixup

Purely cosmetic but satisfies my OCD.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
7 years ago.travis.yml: re-enable lttng user space trace test
Alex Bennée [Wed, 12 Mar 2014 14:13:51 +0000 (14:13 +0000)] 
.travis.yml: re-enable lttng user space trace test

This build was disabled while the lttng tracing was broken. Stefan has
recently submitted a pull request with it re-enabled.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
7 years ago.travis.yml: add a new build target with non-core devlibs
Alex Bennée [Wed, 12 Mar 2014 14:13:50 +0000 (14:13 +0000)] 
.travis.yml: add a new build target with non-core devlibs

The current builds don't include all the features which are
auto-detected and then disabled when the appropriate test packages don't
exist. I've added another target that enables all known additional
packages for increased coverage. I didn't add it to the core package
list to reduce build time.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
7 years agosasl: Avoid 'Could not find keytab file' in syslog
Laszlo Ersek [Fri, 14 Mar 2014 14:39:36 +0000 (15:39 +0100)] 
sasl: Avoid 'Could not find keytab file' in syslog

The "keytab" specification in "qemu.sasl" only makes sense if "gssapi" is
selected in "mech_list". Even if the latter is not done (ie. "gssapi" is
not selected), the cyrus-sasl library tries to open the specified keytab
file, although nothing has a use for it outside the gssapi backend.

Since the default keytab file "/etc/qemu/krb5.tab" is usually absent, the
cyrus-sasl library emits a warning to syslog at startup, which tends to
annoy users (who didn't ask for gssapi in the first place).

Comment out the keytab specification per default.

"qemu-doc.texi" already correctly explains how to use "mech_list: gssapi"
together with "keytab:".

See also:
- upstream libvirt commit fe772f24,
- Red Hat Bugzilla <https://bugzilla.redhat.com/show_bug.cgi?id=1018434>.

Signed-off-by: Laszlo Ersek <lersek@redhat.com>
ACKed-By: Cole Robinson <crobinso@redhat.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
7 years agoMerge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging
Peter Maydell [Fri, 14 Mar 2014 18:44:22 +0000 (18:44 +0000)] 
Merge remote-tracking branch 'remotes/stefanha/tags/block-pull-request' into staging

Block pull request

# gpg: Signature made Fri 14 Mar 2014 16:12:14 GMT using RSA key ID 81AB73C8
# gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>"
# gpg:                 aka "Stefan Hajnoczi <stefanha@gmail.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35  775A 9CA4 ABB3 81AB 73C8

* remotes/stefanha/tags/block-pull-request:
  qemu-iotests: remove 085 and 087 from 'quick' group
  qemu-iotests: add 083 NBD client disconnect tests
  tests: add nbd-fault-injector.py utility
  nbd: close socket if connection breaks
  block: Explicitly specify 'unsigned long long' for VHDX 64-bit constants
  blockdev: Refuse to open encrypted image unless paused

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7 years agoMerge remote-tracking branch 'remotes/bonzini/scsi-next' into staging
Peter Maydell [Fri, 14 Mar 2014 18:17:25 +0000 (18:17 +0000)] 
Merge remote-tracking branch 'remotes/bonzini/scsi-next' into staging

* remotes/bonzini/scsi-next:
  virtio-scsi: actually honor sense_size from configuration space
  scsi: Fix migration of scsi sense data
  spapr-vscsi: fix CRQ status

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
7 years agotcg-aarch64: Introduce tcg_out_insn_3405
Richard Henderson [Wed, 14 Aug 2013 22:57:36 +0000 (15:57 -0700)] 
tcg-aarch64: Introduce tcg_out_insn_3405

Cleaning up the implementation of tcg_out_movi at the same time.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
Tested-by: Claudio Fontana <claudio.fontana@huawei.com>
7 years agotcg-aarch64: Support div, rem
Richard Henderson [Wed, 14 Aug 2013 22:29:18 +0000 (15:29 -0700)] 
tcg-aarch64: Support div, rem

Clean up multiply at the same time.

For remainder, generic code will produce mul+sub,
whereas we can implement with msub.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
Tested-by: Claudio Fontana <claudio.fontana@huawei.com>
7 years agotcg-aarch64: Support muluh, mulsh
Richard Henderson [Wed, 14 Aug 2013 22:03:27 +0000 (15:03 -0700)] 
tcg-aarch64: Support muluh, mulsh

Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
Tested-by: Claudio Fontana <claudio.fontana@huawei.com>
7 years agotcg-aarch64: Support add2, sub2
Richard Henderson [Wed, 14 Aug 2013 20:30:07 +0000 (13:30 -0700)] 
tcg-aarch64: Support add2, sub2

Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
Tested-by: Claudio Fontana <claudio.fontana@huawei.com>
7 years agotcg-aarch64: Support deposit
Richard Henderson [Wed, 14 Aug 2013 20:05:07 +0000 (13:05 -0700)] 
tcg-aarch64: Support deposit

Also tidy the implementation of ubfm, sbfm, extr in order to share code.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
Tested-by: Claudio Fontana <claudio.fontana@huawei.com>
7 years agotcg-aarch64: Use tcg_out_insn for setcond
Richard Henderson [Thu, 12 Sep 2013 01:54:46 +0000 (18:54 -0700)] 
tcg-aarch64: Use tcg_out_insn for setcond

Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
Tested-by: Claudio Fontana <claudio.fontana@huawei.com>
7 years agotcg-aarch64: Support movcond
Richard Henderson [Sat, 10 Aug 2013 03:58:19 +0000 (23:58 -0400)] 
tcg-aarch64: Support movcond

Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
Tested-by: Claudio Fontana <claudio.fontana@huawei.com>
7 years agotcg-aarch64: Support andc, orc, eqv, not, neg
Richard Henderson [Sat, 10 Aug 2013 03:15:44 +0000 (23:15 -0400)] 
tcg-aarch64: Support andc, orc, eqv, not, neg

Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
Tested-by: Claudio Fontana <claudio.fontana@huawei.com>
7 years agotcg-aarch64: Handle constant operands to and, or, xor
Richard Henderson [Wed, 14 Aug 2013 18:27:03 +0000 (11:27 -0700)] 
tcg-aarch64: Handle constant operands to and, or, xor

Handle a simplified set of logical immediates for the moment.

The way gcc and binutils do it, with 52k worth of tables, and
a binary search depth of log2(5334) = 13, seems slow for the
most common cases.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
Tested-by: Claudio Fontana <claudio.fontana@huawei.com>
7 years agotcg-aarch64: Handle constant operands to add, sub, and compare
Richard Henderson [Wed, 14 Aug 2013 16:56:14 +0000 (09:56 -0700)] 
tcg-aarch64: Handle constant operands to add, sub, and compare

Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
Tested-by: Claudio Fontana <claudio.fontana@huawei.com>
7 years agotcg-aarch64: Implement mov with tcg_out_insn
Richard Henderson [Tue, 13 Aug 2013 21:49:18 +0000 (14:49 -0700)] 
tcg-aarch64: Implement mov with tcg_out_insn

Avoid the magic numbers in the current implementation.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
Tested-by: Claudio Fontana <claudio.fontana@huawei.com>
7 years agotcg-aarch64: Introduce tcg_out_insn_3401
Richard Henderson [Tue, 13 Aug 2013 21:37:08 +0000 (14:37 -0700)] 
tcg-aarch64: Introduce tcg_out_insn_3401

This merges the implementation of tcg_out_addi and tcg_out_subi.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
Tested-by: Claudio Fontana <claudio.fontana@huawei.com>
7 years agotcg-aarch64: Convert shift insns to tcg_out_insn
Richard Henderson [Tue, 13 Aug 2013 20:49:17 +0000 (13:49 -0700)] 
tcg-aarch64: Convert shift insns to tcg_out_insn

Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
Tested-by: Claudio Fontana <claudio.fontana@huawei.com>
7 years agotcg-aarch64: Introduce tcg_out_insn
Richard Henderson [Tue, 13 Aug 2013 19:10:08 +0000 (12:10 -0700)] 
tcg-aarch64: Introduce tcg_out_insn

Converting the add/sub (3.5.2) and logical shifted (3.5.10) instruction
groups to the new scheme.

Signed-off-by: Richard Henderson <rth@twiddle.net>
Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com>
Tested-by: Claudio Fontana <claudio.fontana@huawei.com>
7 years agoqemu-iotests: remove 085 and 087 from 'quick' group
Stefan Hajnoczi [Thu, 13 Mar 2014 09:28:01 +0000 (10:28 +0100)] 
qemu-iotests: remove 085 and 087 from 'quick' group

The 'quick' group in qemu-iotests are not allowed to run QEMU since we
don't know which targets are available.  In other words, they may only
use qemu-img, qemu-io, and qemu-nbd.

Drop 085 and 087 from the 'quick' group since they run QEMU.  This
makes "make check-block" pass again.

Reported-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
7 years agoqemu-iotests: add 083 NBD client disconnect tests
Stefan Hajnoczi [Wed, 26 Feb 2014 14:30:20 +0000 (15:30 +0100)] 
qemu-iotests: add 083 NBD client disconnect tests

This new test case uses nbd-fault-injector.py to simulate broken TCP
connections at each stage in the NBD protocol.  This way we can exercise
block/nbd-client.c's socket error handling code paths.

In particular, this serves as a regression test to make sure
nbd-client.c doesn't cause an infinite loop by leaving its
nbd_receive_reply() fd handler registered after the connection has been
closed.  This bug was fixed in an earlier patch.

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
7 years agotests: add nbd-fault-injector.py utility
Stefan Hajnoczi [Wed, 26 Feb 2014 14:30:19 +0000 (15:30 +0100)] 
tests: add nbd-fault-injector.py utility

The nbd-fault-injector.py script is a special kind of NBD server.  It
throws away all writes and produces zeroes for reads.  Given a list of
fault injection rules, it can simulate NBD protocol errors and is useful
for testing NBD client error handling code paths.

See the patch for documentation.  This scripts is modelled after Kevin
Wolf <kwolf@redhat.com>'s blkdebug block driver.

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
7 years agonbd: close socket if connection breaks
Stefan Hajnoczi [Wed, 26 Feb 2014 14:30:18 +0000 (15:30 +0100)] 
nbd: close socket if connection breaks

nbd_receive_reply() is called by the event loop whenever data is
available or the socket has been closed by the remote side.

This patch closes the socket when an error occurs to prevent the
nbd_receive_reply() handler from being called indefinitely after the
connection has failed.

Note that we were already correctly returning EIO for pending requests
but leaving the nbd_receive_reply() handler registered resulted in high
CPU consumption and a flood of error messages.

Reuse nbd_teardown_connection() to close the socket.

Reported-by: Zhifeng Cai <bluewindow@h3c.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
7 years agoblock: Explicitly specify 'unsigned long long' for VHDX 64-bit constants
Jeff Cody [Fri, 14 Mar 2014 10:50:37 +0000 (06:50 -0400)] 
block: Explicitly specify 'unsigned long long' for VHDX 64-bit constants

On 32-bit hosts, some compilers will warn on too large integer constants
for constants that are 64-bit in length.  Explicitly put a 'ULL' suffix
on those defines.

Reported-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Jeff Cody <jcody@redhat.com>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>