qemu.git
12 months agotarget/microblaze: Split out BTR from env->sregs
Richard Henderson [Thu, 20 Aug 2020 04:58:40 +0000 (21:58 -0700)] 
target/microblaze: Split out BTR from env->sregs

Continue eliminating the sregs array in favor of individual members.
Does not correct the width of BTR, yet.

Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotarget/microblaze: Split out FSR from env->sregs
Richard Henderson [Thu, 20 Aug 2020 04:54:38 +0000 (21:54 -0700)] 
target/microblaze: Split out FSR from env->sregs

Continue eliminating the sregs array in favor of individual members.
Does not correct the width of FSR, yet.

Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotarget/microblaze: Split out ESR from env->sregs
Richard Henderson [Thu, 20 Aug 2020 04:50:35 +0000 (21:50 -0700)] 
target/microblaze: Split out ESR from env->sregs

Continue eliminating the sregs array in favor of individual members.
Does not correct the width of ESR, yet.

Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotarget/microblaze: Split out EAR from env->sregs
Richard Henderson [Thu, 20 Aug 2020 04:46:10 +0000 (21:46 -0700)] 
target/microblaze: Split out EAR from env->sregs

Continue eliminating the sregs array in favor of individual members.

Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotarget/microblaze: Split out MSR from env->sregs
Richard Henderson [Thu, 20 Aug 2020 04:41:10 +0000 (21:41 -0700)] 
target/microblaze: Split out MSR from env->sregs

Continue eliminating the sregs array in favor of individual members.
Does not correct the width of MSR, yet.

Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotarget/microblaze: Split out PC from env->sregs
Richard Henderson [Thu, 20 Aug 2020 04:33:32 +0000 (21:33 -0700)] 
target/microblaze: Split out PC from env->sregs

Begin eliminating the sregs array in favor of individual members.
Does not correct the width of pc, yet.

Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotarget/microblaze: Tidy gdbstub
Richard Henderson [Tue, 18 Aug 2020 18:26:59 +0000 (11:26 -0700)] 
target/microblaze: Tidy gdbstub

Use an enumeration for the gdb register mapping.  Use one
switch statement for the entire dispatch.  Drop sreg_map
and simply enumerate those cases explicitly.  Force r0 to
have value 0 and ignore writes.

Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotests/tcg: Do not require FE_* exception bits
Richard Henderson [Tue, 25 Aug 2020 20:12:53 +0000 (13:12 -0700)] 
tests/tcg: Do not require FE_* exception bits

Define anything that is missing as 0, so that flags & FE_FOO
is false for any missing FOO.

Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotests/tcg: Do not require FE_TOWARDZERO
Richard Henderson [Tue, 25 Aug 2020 20:11:43 +0000 (13:11 -0700)] 
tests/tcg: Do not require FE_TOWARDZERO

This is optional in ISO C, and not all cpus provide it.

Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agotests/tcg: Add microblaze to arches filter
Richard Henderson [Tue, 25 Aug 2020 20:10:47 +0000 (13:10 -0700)] 
tests/tcg: Add microblaze to arches filter

Not attempting to use a single cross-compiler for both
big-endian and little-endian at this time.

Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
12 months agoMerge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-5.2-pull-reques...
Peter Maydell [Tue, 1 Sep 2020 14:19:33 +0000 (15:19 +0100)] 
Merge remote-tracking branch 'remotes/vivier2/tags/trivial-branch-for-5.2-pull-request' into staging

Pull request trivial patches 20200901

# gpg: Signature made Tue 01 Sep 2020 15:08:59 BST
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# gpg:                issuer "laurent@vivier.eu"
# gpg: Good signature from "Laurent Vivier <lvivier@redhat.com>" [full]
# gpg:                 aka "Laurent Vivier <laurent@vivier.eu>" [full]
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# Primary key fingerprint: CD2F 75DD C8E3 A4DC 2E4F  5173 F30C 38BD 3F2F BE3C

* remotes/vivier2/tags/trivial-branch-for-5.2-pull-request: (44 commits)
  docs/system: Fix grammar in documentation
  main-loop: Fix comment
  hw/display/vga:Remove redundant statement in vga_draw_graphic()
  hw/intc: fix default registers value in exynos4210_combiner_read()
  usb/bus: Remove dead assignment in usb_get_fw_dev_path()
  vfio/platform: Remove dead assignment in vfio_intp_interrupt()
  hw/net/virtio-net:Remove redundant statement in virtio_net_rsc_tcp_ctrl_check()
  hw/virtio/vhost-user:Remove dead assignment in scrub_shadow_regions()
  target/arm/translate-a64:Remove redundant statement in disas_simd_two_reg_misc_fp16()
  target/arm/translate-a64:Remove dead assignment in handle_scalar_simd_shli()
  hw/arm/omap1:Remove redundant statement in omap_clkdsp_read()
  hw/arm/virt-acpi-build:Remove dead assignment in build_madt()
  linux-user: Add strace support for printing OFD fcntl operations
  util/vfio-helpers: Unify trace-events size format
  hw/net/xilinx_axienet: Remove unused code
  hw/scsi/scsi-disk: Replace magic '512' value by BDRV_SECTOR_SIZE
  hw/ide/pci: Replace magic '512' value by BDRV_SECTOR_SIZE
  hw/ide/atapi: Replace magic '512' value by BDRV_SECTOR_SIZE
  hw/ide/ahci: Replace magic '512' value by BDRV_SECTOR_SIZE
  hw/ide/core: Trivial typo fix
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12 months agohw/arm/sbsa-ref : Add embedded controller in secure memory
Graeme Gregory [Wed, 26 Aug 2020 14:19:52 +0000 (15:19 +0100)] 
hw/arm/sbsa-ref : Add embedded controller in secure memory

Add the previously created sbsa-ec device to the sbsa-ref machine in
secure memory so the PSCI implementation in ARM-TF can access it, but
not expose it to non secure firmware or OS except by via ARM-TF.

Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
Tested-by: Leif Lindholm <leif@nuviainc.com>
Message-id: 20200826141952.136164-3-graeme@nuviainc.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12 months agohw/misc/sbsa_ec : Add an embedded controller for sbsa-ref
Graeme Gregory [Wed, 26 Aug 2020 14:19:51 +0000 (15:19 +0100)] 
hw/misc/sbsa_ec : Add an embedded controller for sbsa-ref

A difference between sbsa platform and the virt platform is PSCI is
handled by ARM-TF in the sbsa platform. This means that the PSCI code
there needs to communicate some of the platform power changes down
to the qemu code for things like shutdown/reset control.

Space has been left to extend the EC if we find other use cases in
future where ARM-TF and qemu need to communicate.

Signed-off-by: Graeme Gregory <graeme@nuviainc.com>
Reviewed-by: Leif Lindholm <leif@nuviainc.com>
Tested-by: Leif Lindholm <leif@nuviainc.com>
Message-id: 20200826141952.136164-2-graeme@nuviainc.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12 months agomeson: add description to options
Paolo Bonzini [Tue, 1 Sep 2020 05:59:23 +0000 (01:59 -0400)] 
meson: add description to options

This will be useful in the future to generate configure
command line parsing from meson_options.txt.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 months agobuild: fix recurse-all target
Paolo Bonzini [Mon, 31 Aug 2020 12:36:27 +0000 (08:36 -0400)] 
build: fix recurse-all target

The missing "/all" suffix prevents the pc-bios/ parts of the build
from running.

In the meanwhile, -Wall has moved from QEMU_CFLAGS to CFLAGS.  Simplify
everything by not passing down CFLAGS, and add -Wall in the recursive
Makefiles.

Reported-by: Miroslav Rezanina <mrezanin@redhat.com>
Reviewed-by: Miroslav Rezanina <mrezanin@redhat.com>
Tested-by: Thomas Huth <thuth@redhat.com>
Fixes: 5e6d1573b4 ("remove Makefile.target", 2020-08-21)
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 months agomeson: use pkg-config method to find dependencies
Paolo Bonzini [Mon, 31 Aug 2020 10:27:00 +0000 (06:27 -0400)] 
meson: use pkg-config method to find dependencies

We do not need to ask cmake for the dependencies, so just use the
pkg-config mechanism.  Keep "auto" for SDL so that it tries using
sdl-config too.

The documentation is adjusted to use SDL2_image as the example,
rather than SDL which does not use the "pkg-config" method.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 months agoconfigure: do not include ${prefix} in firmwarepath
Paolo Bonzini [Mon, 31 Aug 2020 08:48:07 +0000 (04:48 -0400)] 
configure: do not include ${prefix} in firmwarepath

Left out in commit 22a87800e6 ("configure: expand path variables for
meson configure", 2020-08-21), do it now.

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 months agomeson: add pixman dependency to UI modules
Paolo Bonzini [Sun, 30 Aug 2020 15:45:07 +0000 (17:45 +0200)] 
meson: add pixman dependency to UI modules

Pixman used to be included directly in QEMU_CFLAGS and therefore the
include path was added to every compiler invocation.  Now that (just
like basically everything else) it is a separate dependency, we
need to add it to all build target, especially UI modules that need
it due to their including ui/console.h.

Reported-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 months agomeson: add pixman dependency to chardev/baum module
Stefan Weil [Sun, 30 Aug 2020 20:46:40 +0000 (22:46 +0200)] 
meson: add pixman dependency to chardev/baum module

Signed-off-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20200830204640.482214-1-sw@weilnetz.de>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 months agomeson: add NSIS building
Marc-André Lureau [Wed, 26 Aug 2020 11:04:19 +0000 (15:04 +0400)] 
meson: add NSIS building

Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Message-Id: <20200826110419.528931-9-marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 months agomeson: use meson mandir instead of qemu_mandir
Marc-André Lureau [Wed, 26 Aug 2020 11:04:18 +0000 (15:04 +0400)] 
meson: use meson mandir instead of qemu_mandir

When cross-compiling, by default qemu_mandir is 'c:\Program
Files\QEMU', which is not recognized as being an absolute path, and
meson will end up adding the prefix again.

Use the pre-prefixed meson mandir option instead.

Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20200826110419.528931-8-marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 months agomeson: pass docdir option
Marc-André Lureau [Wed, 26 Aug 2020 11:04:17 +0000 (15:04 +0400)] 
meson: pass docdir option

When cross-compiling, by default qemu_docdir is 'c:\Program Files\QEMU\'
which is not recognized as being an absolute path, and meson will end up
adding the prefix again.

Add an option to pass docdir location to meson, pre-prefixed like we do
with other directories, build qemu_docdir with the common suffix and use
that instead of config_host['qemu_docdir'].

Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20200826110419.528931-7-marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 months agomeson: use meson datadir instead of qemu_datadir
Marc-André Lureau [Wed, 26 Aug 2020 11:04:16 +0000 (15:04 +0400)] 
meson: use meson datadir instead of qemu_datadir

When cross-compiling, by default qemu_datadir is 'c:\Program
Files\QEMU', which is not recognized as being an absolute path, and
meson will end up adding the prefix again.

Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20200826110419.528931-6-marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 months agomeson: pass qemu_suffix option
Marc-André Lureau [Wed, 26 Aug 2020 11:04:15 +0000 (15:04 +0400)] 
meson: pass qemu_suffix option

The following patches will make use of it to fix installation paths.

Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20200826110419.528931-5-marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 months agoconfigure: build docdir like other suffixed directories
Marc-André Lureau [Wed, 26 Aug 2020 11:04:14 +0000 (15:04 +0400)] 
configure: build docdir like other suffixed directories

As documented in --help for --docdir.

Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20200826110419.528931-4-marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 months agoconfigure: always /-seperate directory from qemu_suffix
Marc-André Lureau [Wed, 26 Aug 2020 11:04:13 +0000 (15:04 +0400)] 
configure: always /-seperate directory from qemu_suffix

Otherwise, we may accept very strange directory names...

While at it, quote the variables.

Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20200826110419.528931-3-marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 months agoconfigure: rename confsuffix option
Marc-André Lureau [Wed, 26 Aug 2020 11:04:12 +0000 (15:04 +0400)] 
configure: rename confsuffix option

The value is used to construct conf/mod/data directories.

Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20200826110419.528931-2-marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 months agomeson: move zlib detection to meson
Paolo Bonzini [Fri, 28 Aug 2020 17:33:54 +0000 (19:33 +0200)] 
meson: move zlib detection to meson

Meson includes the same logic that tries to look for -lz if
pkg-config (and cmake) cannot find zlib.  The undocumented
--disable-zlib-test option becomes a no-op.

There is still an instance of "-lz" in the LIBS directory.
It will go away as soon as tests are converted to meson,
because the zlib dependency does not propagate from libblock.fa
to the Makefile-build unit tests.

Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
12 months agohw/arm/sbsa-ref: add "reg" property to DT cpu nodes
Leif Lindholm [Thu, 27 Aug 2020 12:43:35 +0000 (13:43 +0100)] 
hw/arm/sbsa-ref: add "reg" property to DT cpu nodes

The sbsa-ref platform uses a minimal device tree to pass amount of memory
as well as number of cpus to the firmware. However, when dumping that
minimal dtb (with -M sbsa-virt,dumpdtb=<file>), the resulting blob
generates a warning when decompiled by dtc due to lack of reg property.

Add a simple reg property per cpu, representing a 64-bit MPIDR_EL1.

This also ends up being cleaner than having the firmware calculating its
own IDs for generating APCI.

Signed-off-by: Leif Lindholm <leif@nuviainc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20200827124335.30586-1-leif@nuviainc.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
12 months agotarget/arm: Enable FP16 in '-cpu max'
Peter Maydell [Fri, 28 Aug 2020 18:33:54 +0000 (19:33 +0100)] 
target/arm: Enable FP16 in '-cpu max'

Set the MVFR1 ID register FPHP and SIMDHP fields to indicate
that our "-cpu max" has v8.2-FP16.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-46-peter.maydell@linaro.org

12 months agotarget/arm: Implement fp16 for Neon VMUL, VMLA, VMLS
Peter Maydell [Fri, 28 Aug 2020 18:33:53 +0000 (19:33 +0100)] 
target/arm: Implement fp16 for Neon VMUL, VMLA, VMLS

Convert the Neon floating-point VMUL, VMLA and VMLS to use gvec,
and use this to implement fp16 support.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-45-peter.maydell@linaro.org

12 months agotarget/arm/vec_helper: Add gvec fp indexed multiply-and-add operations
Peter Maydell [Fri, 28 Aug 2020 18:33:52 +0000 (19:33 +0100)] 
target/arm/vec_helper: Add gvec fp indexed multiply-and-add operations

Add gvec helpers for doing Neon-style indexed non-fused fp
multiply-and-accumulate operations.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20200828183354.27913-44-peter.maydell@linaro.org

12 months agotarget/arm/vec_helper: Handle oprsz less than 16 bytes in indexed operations
Peter Maydell [Fri, 28 Aug 2020 18:33:51 +0000 (19:33 +0100)] 
target/arm/vec_helper: Handle oprsz less than 16 bytes in indexed operations

In the gvec helper functions for indexed operations, for AArch32
Neon the oprsz (total size of the vector) can be less than 16 bytes
if the operation is on a D reg. Since the inner loop in these
helpers always goes from 0 to segment, we must clamp it based
on oprsz to avoid processing a full 16 byte segment when asked to
handle an 8 byte wide vector.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-43-peter.maydell@linaro.org

12 months agotarget/arm: Implement fp16 for Neon VRINTX
Peter Maydell [Fri, 28 Aug 2020 18:33:50 +0000 (19:33 +0100)] 
target/arm: Implement fp16 for Neon VRINTX

Convert the Neon VRINTX insn to use gvec, and use this to implement
fp16 support for it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-42-peter.maydell@linaro.org

12 months agotarget/arm: Implement fp16 for Neon VRINT-with-specified-rounding-mode
Peter Maydell [Fri, 28 Aug 2020 18:33:49 +0000 (19:33 +0100)] 
target/arm: Implement fp16 for Neon VRINT-with-specified-rounding-mode

Convert the Neon VRINT-with-specified-rounding-mode insns to gvec,
and use this to implement the fp16 versions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-41-peter.maydell@linaro.org

12 months agotarget/arm: Implement fp16 for Neon VCVT with rounding modes
Peter Maydell [Fri, 28 Aug 2020 18:33:48 +0000 (19:33 +0100)] 
target/arm: Implement fp16 for Neon VCVT with rounding modes

Convert the Neon VCVT with-specified-rounding-mode instructions
to gvec, and use this to implement fp16 support for them.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-40-peter.maydell@linaro.org

12 months agotarget/arm: Implement fp16 for Neon VCVT fixed-point
Peter Maydell [Fri, 28 Aug 2020 18:33:47 +0000 (19:33 +0100)] 
target/arm: Implement fp16 for Neon VCVT fixed-point

Implement fp16 for the Neon VCVT insns which convert between
float and fixed-point.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-39-peter.maydell@linaro.org

12 months agotarget/arm: Convert Neon VCVT fixed-point to gvec
Peter Maydell [Fri, 28 Aug 2020 18:33:46 +0000 (19:33 +0100)] 
target/arm: Convert Neon VCVT fixed-point to gvec

Convert the Neon VCVT float<->fixed-point insns to a
gvec style, in preparation for adding fp16 support.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-38-peter.maydell@linaro.org

12 months agotarget/arm: Implement fp16 for Neon float-integer VCVT
Peter Maydell [Fri, 28 Aug 2020 18:33:45 +0000 (19:33 +0100)] 
target/arm: Implement fp16 for Neon float-integer VCVT

Convert the Neon float-integer VCVT insns to gvec, and use this
to implement fp16 support for them.

Note that unlike the VFP int<->fp16 VCVT insns we converted
earlier and which convert to/from a 32-bit integer, these
Neon insns convert to/from 16-bit integers. So we can use
the existing vfp conversion helpers for the f32<->u32/i32
case but need to provide our own for f16<->u16/i16.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-37-peter.maydell@linaro.org

12 months agotarget/arm: Implement fp16 for Neon pairwise fp ops
Peter Maydell [Fri, 28 Aug 2020 18:33:44 +0000 (19:33 +0100)] 
target/arm: Implement fp16 for Neon pairwise fp ops

Convert the Neon pairwise fp ops to use a single gvic-style
helper to do the full operation instead of one helper call
for each 32-bit part. This allows us to use the same
framework to implement the fp16.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-36-peter.maydell@linaro.org

12 months agotarget/arm: Implement fp16 for Neon VRSQRTS
Peter Maydell [Fri, 28 Aug 2020 18:33:43 +0000 (19:33 +0100)] 
target/arm: Implement fp16 for Neon VRSQRTS

Convert the Neon VRSQRTS insn to using a gvec helper,
and use this to implement the fp16 case.

As with VRECPS, we adjust the phrasing of the new implementation
slightly so that the fp32 version parallels the fp16 one.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-35-peter.maydell@linaro.org

12 months agotarget/arm: Implement fp16 for Neon VRECPS
Peter Maydell [Fri, 28 Aug 2020 18:33:42 +0000 (19:33 +0100)] 
target/arm: Implement fp16 for Neon VRECPS

Convert the Neon VRECPS insn to using a gvec helper, and
use this to implement the fp16 case.

The phrasing of the new float32_recps_nf() is slightly different from
the old recps_f32() so that it parallels the f16 version; for f16 we
can't assume that flush-to-zero is always enabled.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-34-peter.maydell@linaro.org

12 months agotarget/arm: Implement fp16 for Neon fp compare-vs-0
Peter Maydell [Fri, 28 Aug 2020 18:33:41 +0000 (19:33 +0100)] 
target/arm: Implement fp16 for Neon fp compare-vs-0

Convert the neon floating-point vector compare-vs-0 insns VCEQ0,
VCGT0, VCLE0, VCGE0 and VCLT0 to use a gvec helper, and use this to
implement the fp16 case.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-33-peter.maydell@linaro.org

12 months agotarget/arm: Implement fp16 for Neon VFMA, VMFS
Peter Maydell [Fri, 28 Aug 2020 18:33:40 +0000 (19:33 +0100)] 
target/arm: Implement fp16 for Neon VFMA, VMFS

Convert the neon floating-point vector operations VFMA and VFMS
to use a gvec helper, and use this to implement the fp16 case.

This is the last use of do_3same_fp() so we can now delete
that function.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-32-peter.maydell@linaro.org

12 months agotarget/arm: Implement fp16 for Neon VMLA, VMLS operations
Peter Maydell [Fri, 28 Aug 2020 18:33:39 +0000 (19:33 +0100)] 
target/arm: Implement fp16 for Neon VMLA, VMLS operations

Convert the Neon floating-point VMLA and VMLS insns over to using a
gvec helper, and use this to implement the fp16 case.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-31-peter.maydell@linaro.org

12 months agotarget/arm: Implement fp16 for Neon VMAXNM, VMINNM
Peter Maydell [Fri, 28 Aug 2020 18:33:38 +0000 (19:33 +0100)] 
target/arm: Implement fp16 for Neon VMAXNM, VMINNM

Convert the Neon floating point VMAXNM and VMINNM insns to
using a gvec helper and use this to implement the fp16 case.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-30-peter.maydell@linaro.org

12 months agotarget/arm: Implement fp16 for Neon VMAX, VMIN
Peter Maydell [Fri, 28 Aug 2020 18:33:37 +0000 (19:33 +0100)] 
target/arm: Implement fp16 for Neon VMAX, VMIN

Convert the Neon float-point VMAX and VMIN insns over to using
a gvec helper, and use this to implement the fp16 case.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-29-peter.maydell@linaro.org

12 months agotarget/arm: Implement fp16 for VACGE, VACGT
Peter Maydell [Fri, 28 Aug 2020 18:33:36 +0000 (19:33 +0100)] 
target/arm: Implement fp16 for VACGE, VACGT

Convert the neon floating-point vector absolute comparison ops
VACGE and VACGT over to using a gvec hepler and use this to
implement the fp16 case.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-28-peter.maydell@linaro.org

12 months agotarget/arm: Implement fp16 for VCEQ, VCGE, VCGT comparisons
Peter Maydell [Fri, 28 Aug 2020 18:33:35 +0000 (19:33 +0100)] 
target/arm: Implement fp16 for VCEQ, VCGE, VCGT comparisons

Convert the Neon floating-point vector comparison ops VCEQ,
VCGE and VCGT over to using a gvec helper and use this to
implement the fp16 case.

(We put the float16_ceq() etc functions above the DO_2OP()
macro definition because later when we convert the
compare-against-zero instructions we'll want their
definitions to be visible at that point in the source file.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-27-peter.maydell@linaro.org

12 months agotarget/arm: Implement fp16 for Neon VABS, VNEG of floats
Peter Maydell [Fri, 28 Aug 2020 18:33:34 +0000 (19:33 +0100)] 
target/arm: Implement fp16 for Neon VABS, VNEG of floats

Rewrite Neon VABS/VNEG of floats to use gvec logical AND and XOR, so
that we can implement the fp16 version of the insns.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-26-peter.maydell@linaro.org

12 months agotarget/arm: Implement fp16 for Neon VRECPE, VRSQRTE using gvec
Peter Maydell [Fri, 28 Aug 2020 18:33:33 +0000 (19:33 +0100)] 
target/arm: Implement fp16 for Neon VRECPE, VRSQRTE using gvec

We already have gvec helpers for floating point VRECPE and
VRQSRTE, so convert the Neon decoder to use them and
add the fp16 support.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-25-peter.maydell@linaro.org

12 months agotarget/arm: Implement FP16 for Neon VADD, VSUB, VABD, VMUL
Peter Maydell [Fri, 28 Aug 2020 18:33:32 +0000 (19:33 +0100)] 
target/arm: Implement FP16 for Neon VADD, VSUB, VABD, VMUL

Implement FP16 support for the Neon insns which use the DO_3S_FP_GVEC
macro: VADD, VSUB, VABD, VMUL.

For VABD this requires us to implement a new gvec_fabd_h helper
using the machinery we have already for the other helpers.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-24-peter.maydell@linaro.org

12 months agotarget/arm: Implement VFP fp16 VMOV between gp and halfprec registers
Peter Maydell [Fri, 28 Aug 2020 18:33:30 +0000 (19:33 +0100)] 
target/arm: Implement VFP fp16 VMOV between gp and halfprec registers

Implement the VFP fp16 variant of VMOV that transfers a 16-bit
value between a general purpose register and a VFP register.

Note that Rt == 15 is UNPREDICTABLE; since this insn is v8 and later
only we have no need to replicate the old "updates CPSR.NZCV"
behaviour that the singleprec version of this insn does.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-22-peter.maydell@linaro.org

12 months agotarget/arm: Implement new VFP fp16 insn VMOVX
Peter Maydell [Fri, 28 Aug 2020 18:33:29 +0000 (19:33 +0100)] 
target/arm: Implement new VFP fp16 insn VMOVX

The fp16 extension includes a new instruction VMOVX, which copies the
upper 16 bits of a 32-bit source VFP register into the lower 16
bits of the destination and zeroes the high half of the destination.
Implement it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-21-peter.maydell@linaro.org

12 months agotarget/arm: Implement new VFP fp16 insn VINS
Peter Maydell [Fri, 28 Aug 2020 18:33:28 +0000 (19:33 +0100)] 
target/arm: Implement new VFP fp16 insn VINS

The fp16 extension includes a new instruction VINS, which copies the
lower 16 bits of a 32-bit source VFP register into the upper 16 bits
of the destination.  Implement it.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-20-peter.maydell@linaro.org

12 months agotarget/arm: Implement VFP fp16 VRINT*
Peter Maydell [Fri, 28 Aug 2020 18:33:27 +0000 (19:33 +0100)] 
target/arm: Implement VFP fp16 VRINT*

Implement the fp16 version of the VFP VRINT* insns.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-19-peter.maydell@linaro.org

12 months agotarget/arm: Implement VFP fp16 VSEL
Peter Maydell [Fri, 28 Aug 2020 18:33:26 +0000 (19:33 +0100)] 
target/arm: Implement VFP fp16 VSEL

Implement the fp16 versions of the VFP VSEL instruction.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-18-peter.maydell@linaro.org

12 months agotarget/arm: Implement VFP vp16 VCVT-with-specified-rounding-mode
Peter Maydell [Fri, 28 Aug 2020 18:33:25 +0000 (19:33 +0100)] 
target/arm: Implement VFP vp16 VCVT-with-specified-rounding-mode

Implement the fp16 versions of the VFP VCVT instruction forms
which convert between floating point and integer with a specified
rounding mode.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-17-peter.maydell@linaro.org

12 months agotarget/arm: Implement VFP fp16 VCVT between float and fixed-point
Peter Maydell [Fri, 28 Aug 2020 18:33:24 +0000 (19:33 +0100)] 
target/arm: Implement VFP fp16 VCVT between float and fixed-point

Implement the fp16 versions of the VFP VCVT instruction forms which
convert between floating point and fixed-point.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-16-peter.maydell@linaro.org

12 months agotarget/arm: Use macros instead of open-coding fp16 conversion helpers
Peter Maydell [Fri, 28 Aug 2020 18:33:23 +0000 (19:33 +0100)] 
target/arm: Use macros instead of open-coding fp16 conversion helpers

Now the VFP_CONV_FIX macros can handle fp16's distinction between the
width of the operation and the width of the type used to pass operands,
use the macros rather than the open-coded functions.

This creates an extra six helper functions, all of which we are going
to need for the AArch32 VFP fp16 instructions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-15-peter.maydell@linaro.org

12 months agotarget/arm: Make VFP_CONV_FIX macros take separate float type and float size
Peter Maydell [Fri, 28 Aug 2020 18:33:22 +0000 (19:33 +0100)] 
target/arm: Make VFP_CONV_FIX macros take separate float type and float size

Currently the VFP_CONV_FIX macros take a single fsz argument for the
size of the float type, which is used both to select the name of
the functions to call (eg float32_is_any_nan()) and also for the
type to use for the float inputs and outputs (eg float32).

Separate these into fsz and ftype arguments, so that we can use them
for fp16, which uses 'float16' in the function names but is still
passing inputs and outputs in a 32-bit sized type.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-14-peter.maydell@linaro.org

12 months agotarget/arm: Implement VFP fp16 VCVT between float and integer
Peter Maydell [Fri, 28 Aug 2020 18:33:21 +0000 (19:33 +0100)] 
target/arm: Implement VFP fp16 VCVT between float and integer

Implement the fp16 versions of the VFP VCVT instruction forms which
convert between floating point and integer.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-13-peter.maydell@linaro.org

12 months agotarget/arm: Implement VFP fp16 VLDR and VSTR
Peter Maydell [Fri, 28 Aug 2020 18:33:20 +0000 (19:33 +0100)] 
target/arm: Implement VFP fp16 VLDR and VSTR

Implement the fp16 versions of the VFP VLDR/VSTR (immediate).

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-12-peter.maydell@linaro.org

12 months agotarget/arm: Implement VFP fp16 VCMP
Peter Maydell [Fri, 28 Aug 2020 18:33:19 +0000 (19:33 +0100)] 
target/arm: Implement VFP fp16 VCMP

Implement fp16 version of VCMP.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-11-peter.maydell@linaro.org

12 months agotarget/arm: Implement VFP fp16 for VMOV immediate
Peter Maydell [Fri, 28 Aug 2020 18:33:18 +0000 (19:33 +0100)] 
target/arm: Implement VFP fp16 for VMOV immediate

Implement VFP fp16 support for the VMOV immediate insn.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-10-peter.maydell@linaro.org

12 months agotarget/arm: Implement VFP fp16 for VABS, VNEG, VSQRT
Peter Maydell [Fri, 28 Aug 2020 18:33:17 +0000 (19:33 +0100)] 
target/arm: Implement VFP fp16 for VABS, VNEG, VSQRT

Implement VFP fp16 for VABS, VNEG and VSQRT. This is all
the fp16 insns that use the DO_VFP_2OP macro, because there
is no fp16 version of VMOV_reg.

Notes:
 * the gen_helper_vfp_negh already exists as we needed to create
   it for the fp16 multiply-add insns
 * as usual we need to use the f16 version of the fp_status;
   this is only relevant for VSQRT

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-9-peter.maydell@linaro.org

12 months agotarget/arm: Macroify uses of do_vfp_2op_sp() and do_vfp_2op_dp()
Peter Maydell [Fri, 28 Aug 2020 18:33:16 +0000 (19:33 +0100)] 
target/arm: Macroify uses of do_vfp_2op_sp() and do_vfp_2op_dp()

Macroify the uses of do_vfp_2op_sp() and do_vfp_2op_dp(); this will
make it easier to add the halfprec support.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-8-peter.maydell@linaro.org

12 months agotarget/arm: Implement VFP fp16 for fused-multiply-add
Peter Maydell [Fri, 28 Aug 2020 18:33:15 +0000 (19:33 +0100)] 
target/arm: Implement VFP fp16 for fused-multiply-add

Implement VFP fp16 support for fused multiply-add insns
VFNMA, VFNMS, VFMA, VFMS.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-7-peter.maydell@linaro.org

12 months agotarget/arm: Macroify trans functions for VFMA, VFMS, VFNMA, VFNMS
Peter Maydell [Fri, 28 Aug 2020 18:33:14 +0000 (19:33 +0100)] 
target/arm: Macroify trans functions for VFMA, VFMS, VFNMA, VFNMS

Macroify creation of the trans functions for single and double
precision VFMA, VFMS, VFNMA, VFNMS. The repetition was OK for
two sizes, but we're about to add halfprec and it will get a bit
more than seems reasonable.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-6-peter.maydell@linaro.org

12 months agotarget/arm: Implement VFP fp16 VMLA, VMLS, VNMLS, VNMLA, VNMUL
Peter Maydell [Fri, 28 Aug 2020 18:33:13 +0000 (19:33 +0100)] 
target/arm: Implement VFP fp16 VMLA, VMLS, VNMLS, VNMLA, VNMUL

Implement fp16 versions of the VFP VMLA, VMLS, VNMLS, VNMLA, VNMUL
instructions. (These are all the remaining ones which we implement
via do_vfp_3op_[hsd]p().)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-5-peter.maydell@linaro.org

12 months agotarget/arm: Implement VFP fp16 for VFP_BINOP operations
Peter Maydell [Fri, 28 Aug 2020 18:33:12 +0000 (19:33 +0100)] 
target/arm: Implement VFP fp16 for VFP_BINOP operations

Implmeent VFP fp16 support for simple binary-operator VFP insns VADD,
VSUB, VMUL, VDIV, VMINNM and VMAXNM:

 * make the VFP_BINOP() macro generate float16 helpers as well as
   float32 and float64
 * implement a do_vfp_3op_hp() function similar to the existing
   do_vfp_3op_sp()
 * add decode for the half-precision insn patterns

Note that the VFP_BINOP macro use creates a couple of unused helper
functions vfp_maxh and vfp_minh, but they're small so it's not worth
splitting the BINOP operations into "needs halfprec" and "no
halfprec" groups.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-4-peter.maydell@linaro.org

12 months agotarget/arm: Use correct ID register check for aa32_fp16_arith
Peter Maydell [Fri, 28 Aug 2020 18:33:11 +0000 (19:33 +0100)] 
target/arm: Use correct ID register check for aa32_fp16_arith

The aa32_fp16_arith feature check function currently looks at the
AArch64 ID_AA64PFR0 register. This is (as the comment notes) not
correct. The bogus check was put in mostly to allow testing of the
fp16 variants of the VCMLA instructions and it was something of
a mistake that we allowed them to exist in master.

Switch the feature check function to testing VMFR1.FPHP, which is
what it ought to be.

This will remove emulation of the VCMLA and VCADD insns from
AArch32 code running on an AArch64 '-cpu max' using system emulation.
(They were never enabled for aarch32 linux-user and system-emulation.)
Since we weren't advertising their existence via the AArch32 ID
register, well-behaved guests wouldn't have been using them anyway.

Once we have implemented all the AArch32 support for the FP16 extension
we will advertise it in the MVFR1 ID register field, which will reenable
these insns along with all the others.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-3-peter.maydell@linaro.org

12 months agotarget/arm: Remove local definitions of float constants
Peter Maydell [Fri, 28 Aug 2020 18:33:10 +0000 (19:33 +0100)] 
target/arm: Remove local definitions of float constants

In several places the target/arm code defines local float constants
for 2, 3 and 1.5, which are also provided by include/fpu/softfloat.h.
Remove the unnecessary local duplicate versions.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200828183354.27913-2-peter.maydell@linaro.org

12 months agodocs/system: Fix grammar in documentation
Stefan Weil [Thu, 27 Aug 2020 17:30:51 +0000 (19:30 +0200)] 
docs/system: Fix grammar in documentation

Signed-off-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20200827173051.31050-1-sw@weilnetz.de>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
12 months agomain-loop: Fix comment
Stefan Weil [Thu, 27 Aug 2020 17:55:20 +0000 (19:55 +0200)] 
main-loop: Fix comment

Signed-off-by: Stefan Weil <sw@weilnetz.de>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20200827175520.32355-1-sw@weilnetz.de>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
12 months agohw/display/vga:Remove redundant statement in vga_draw_graphic()
Chen Qun [Thu, 27 Aug 2020 11:03:11 +0000 (19:03 +0800)] 
hw/display/vga:Remove redundant statement in vga_draw_graphic()

Clang static code analyzer show warning:
hw/display/vga.c:1677:9: warning: Value stored to 'update' is never read
        update = full_update;
        ^        ~~~~~~~~~~~

Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Chen Qun <kuhn.chenqun@huawei.com>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Li Qiang <liq3ea@gmail.com>
Message-Id: <20200827110311.164316-11-kuhn.chenqun@huawei.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
12 months agohw/intc: fix default registers value in exynos4210_combiner_read()
Chen Qun [Thu, 27 Aug 2020 11:03:10 +0000 (19:03 +0800)] 
hw/intc: fix default registers value in exynos4210_combiner_read()

Clang static code analyzer show warning:
hw/intc/exynos4210_combiner.c:231:9: warning: Value stored to 'val' is never read
        val = s->reg_set[offset >> 2];

The default register return value should be return 'val'.

Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Chen Qun <kuhn.chenqun@huawei.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20200827110311.164316-10-kuhn.chenqun@huawei.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
12 months agousb/bus: Remove dead assignment in usb_get_fw_dev_path()
Chen Qun [Thu, 27 Aug 2020 11:03:09 +0000 (19:03 +0800)] 
usb/bus: Remove dead assignment in usb_get_fw_dev_path()

Clang static code analyzer show warning:
qemu/hw/usb/bus.c:615:13: warning: Value stored to 'pos' is never read
            pos += snprintf(fw_path + pos, fw_len - pos, "%s@%lx",

Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Chen Qun <kuhn.chenqun@huawei.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
Message-Id: <20200827110311.164316-9-kuhn.chenqun@huawei.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
12 months agovfio/platform: Remove dead assignment in vfio_intp_interrupt()
Chen Qun [Thu, 27 Aug 2020 11:03:08 +0000 (19:03 +0800)] 
vfio/platform: Remove dead assignment in vfio_intp_interrupt()

Clang static code analyzer show warning:
hw/vfio/platform.c:239:9: warning: Value stored to 'ret' is never read
        ret = event_notifier_test_and_clear(intp->interrupt);
        ^     ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Chen Qun <kuhn.chenqun@huawei.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Li Qiang <liq3ea@gmail.com>
Message-Id: <20200827110311.164316-8-kuhn.chenqun@huawei.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
12 months agohw/net/virtio-net:Remove redundant statement in virtio_net_rsc_tcp_ctrl_check()
Chen Qun [Thu, 27 Aug 2020 11:03:07 +0000 (19:03 +0800)] 
hw/net/virtio-net:Remove redundant statement in virtio_net_rsc_tcp_ctrl_check()

Clang static code analyzer show warning:
hw/net/virtio-net.c:2077:5: warning: Value stored to 'tcp_flag' is never read
    tcp_flag &= VIRTIO_NET_TCP_FLAG;
    ^           ~~~~~~~~~~~~~~~~~~~

The 'VIRTIO_NET_TCP_FLAG' is '0x3F'. The last ‘tcp_flag’ assignment statement is
 the same as that of the first two statements.

Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Chen Qun <kuhn.chenqun@huawei.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Li Qiang <liq3ea@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20200827110311.164316-7-kuhn.chenqun@huawei.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
12 months agohw/virtio/vhost-user:Remove dead assignment in scrub_shadow_regions()
Chen Qun [Thu, 27 Aug 2020 11:03:06 +0000 (19:03 +0800)] 
hw/virtio/vhost-user:Remove dead assignment in scrub_shadow_regions()

Clang static code analyzer show warning:
hw/virtio/vhost-user.c:606:9: warning: Value stored to 'mr' is never read
        mr = vhost_user_get_mr_data(reg->userspace_addr, &offset, &fd);
        ^    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Chen Qun <kuhn.chenqun@huawei.com>
Reviewed-by: Raphael Norwitz <raphael.norwitz@nutanix.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20200827110311.164316-6-kuhn.chenqun@huawei.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
12 months agotarget/arm/translate-a64:Remove redundant statement in disas_simd_two_reg_misc_fp16()
Chen Qun [Thu, 27 Aug 2020 11:03:05 +0000 (19:03 +0800)] 
target/arm/translate-a64:Remove redundant statement in disas_simd_two_reg_misc_fp16()

Clang static code analyzer show warning:
target/arm/translate-a64.c:13007:5: warning: Value stored to 'rd' is never read
    rd = extract32(insn, 0, 5);
    ^    ~~~~~~~~~~~~~~~~~~~~~
target/arm/translate-a64.c:13008:5: warning: Value stored to 'rn' is never read
    rn = extract32(insn, 5, 5);
    ^    ~~~~~~~~~~~~~~~~~~~~~

Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Chen Qun <kuhn.chenqun@huawei.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20200827110311.164316-5-kuhn.chenqun@huawei.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
12 months agotarget/arm/translate-a64:Remove dead assignment in handle_scalar_simd_shli()
Chen Qun [Thu, 27 Aug 2020 11:03:04 +0000 (19:03 +0800)] 
target/arm/translate-a64:Remove dead assignment in handle_scalar_simd_shli()

Clang static code analyzer show warning:
target/arm/translate-a64.c:8635:14: warning: Value stored to 'tcg_rn' during its
 initialization is never read
    TCGv_i64 tcg_rn = new_tmp_a64(s);
             ^~~~~~   ~~~~~~~~~~~~~~
target/arm/translate-a64.c:8636:14: warning: Value stored to 'tcg_rd' during its
 initialization is never read
    TCGv_i64 tcg_rd = new_tmp_a64(s);
             ^~~~~~   ~~~~~~~~~~~~~~

Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Chen Qun <kuhn.chenqun@huawei.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20200827110311.164316-4-kuhn.chenqun@huawei.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
12 months agohw/arm/omap1:Remove redundant statement in omap_clkdsp_read()
Chen Qun [Thu, 27 Aug 2020 11:03:03 +0000 (19:03 +0800)] 
hw/arm/omap1:Remove redundant statement in omap_clkdsp_read()

Clang static code analyzer show warning:
hw/arm/omap1.c:1760:15: warning: Value stored to 'cpu' during its
initialization is never read
    CPUState *cpu = CPU(s->cpu);
              ^~~   ~~~~~~~~~~~

Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Chen Qun <kuhn.chenqun@huawei.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Li Qiang <liq3ea@gmail.com>
Message-Id: <20200827110311.164316-3-kuhn.chenqun@huawei.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
12 months agohw/arm/virt-acpi-build:Remove dead assignment in build_madt()
Chen Qun [Thu, 27 Aug 2020 11:03:02 +0000 (19:03 +0800)] 
hw/arm/virt-acpi-build:Remove dead assignment in build_madt()

Clang static code analyzer show warning:
hw/arm/virt-acpi-build.c:641:5: warning: Value stored to 'madt' is never read
    madt = acpi_data_push(table_data, sizeof *madt);
    ^      ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Reported-by: Euler Robot <euler.robot@huawei.com>
Signed-off-by: Chen Qun <kuhn.chenqun@huawei.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Li Qiang <liq3ea@gmail.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20200827110311.164316-2-kuhn.chenqun@huawei.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
12 months agolinux-user: Add strace support for printing OFD fcntl operations
Mike Gelfand [Sun, 30 Aug 2020 09:22:42 +0000 (12:22 +0300)] 
linux-user: Add strace support for printing OFD fcntl operations

Signed-off-by: Mike Gelfand <mikedld@mikedld.com>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Message-Id: <20200830092242.31506-1-mikedld@mikedld.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
12 months agoutil/vfio-helpers: Unify trace-events size format
Philippe Mathieu-Daudé [Thu, 20 Aug 2020 17:10:06 +0000 (19:10 +0200)] 
util/vfio-helpers: Unify trace-events size format

Some 'qemu_vfio_*' trace events sizes are displayed using
decimal notation, other using hexadecimal notation:

  qemu_vfio_ram_block_added s 0xaaaaf2448d90 host 0xffff5bc00000 size 0x4000000
  qemu_vfio_dma_map s 0xaaaaf2448d90 host 0xffff5bc00000 size 67108864 temporary 0 iova (nil)
  qemu_vfio_find_mapping s 0xaaaaf2448d90 host 0xffff5bc00000
  qemu_vfio_new_mapping s 0xaaaaf2448d90 host 0xffff5bc00000 size 67108864 index 4 iova 0x114000
  qemu_vfio_do_mapping s 0xaaaaf2448d90 host 0xffff5bc00000 size 67108864 iova 0x114000

As it is hard to follow, unify using hexadecimal for all sizes:

  qemu_vfio_ram_block_added s 0xaaaaf1c60d90 host 0xffff2bc00000 size 0x4000000
  qemu_vfio_dma_map s 0xaaaaf1c60d90 host 0xffff2bc00000 size 0x4000000 temporary 0 iova (nil)
  qemu_vfio_find_mapping s 0xaaaaf1c60d90 host 0xffff2bc00000
  qemu_vfio_new_mapping s 0xaaaaf1c60d90 host 0xffff2bc00000 size 0x4000000 index 4 iova 0x114000
  qemu_vfio_do_mapping s 0xaaaaf1c60d90 host 0xffff2bc00000 size 0x4000000 iova 0x114000

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Li Qiang <liq3ea@gmail.com>
Message-Id: <20200820171006.1140228-1-philmd@redhat.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
12 months agohw/net/xilinx_axienet: Remove unused code
Philippe Mathieu-Daudé [Fri, 14 Aug 2020 13:30:07 +0000 (15:30 +0200)] 
hw/net/xilinx_axienet: Remove unused code

Most of the MDIOBus fields are unused.  The ADVERTISE_10HALF
definition is unused.  Remove unused code.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-Id: <20200814133007.16850-1-f4bug@amsat.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
12 months agohw/scsi/scsi-disk: Replace magic '512' value by BDRV_SECTOR_SIZE
Philippe Mathieu-Daudé [Fri, 14 Aug 2020 08:28:41 +0000 (10:28 +0200)] 
hw/scsi/scsi-disk: Replace magic '512' value by BDRV_SECTOR_SIZE

Use self-explicit definitions instead of magic '512' value.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Li Qiang <liq3ea@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Message-Id: <20200814082841.27000-8-f4bug@amsat.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
12 months agohw/ide/pci: Replace magic '512' value by BDRV_SECTOR_SIZE
Philippe Mathieu-Daudé [Fri, 14 Aug 2020 08:28:40 +0000 (10:28 +0200)] 
hw/ide/pci: Replace magic '512' value by BDRV_SECTOR_SIZE

Use self-explicit definitions instead of magic '512' value.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Li Qiang <liq3ea@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Message-Id: <20200814082841.27000-7-f4bug@amsat.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
12 months agohw/ide/atapi: Replace magic '512' value by BDRV_SECTOR_SIZE
Philippe Mathieu-Daudé [Fri, 14 Aug 2020 08:28:39 +0000 (10:28 +0200)] 
hw/ide/atapi: Replace magic '512' value by BDRV_SECTOR_SIZE

Use self-explicit definitions instead of magic '512' value.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Li Qiang <liq3ea@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Message-Id: <20200814082841.27000-6-f4bug@amsat.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
12 months agohw/ide/ahci: Replace magic '512' value by BDRV_SECTOR_SIZE
Philippe Mathieu-Daudé [Fri, 14 Aug 2020 08:28:38 +0000 (10:28 +0200)] 
hw/ide/ahci: Replace magic '512' value by BDRV_SECTOR_SIZE

Use self-explicit definitions instead of magic '512' value.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Li Qiang <liq3ea@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Message-Id: <20200814082841.27000-5-f4bug@amsat.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
12 months agohw/ide/core: Trivial typo fix
Philippe Mathieu-Daudé [Fri, 14 Aug 2020 08:28:36 +0000 (10:28 +0200)] 
hw/ide/core: Trivial typo fix

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Li Qiang <liq3ea@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Message-Id: <20200814082841.27000-3-f4bug@amsat.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
12 months agodocs/system/target-avr: Improve the AVR docs and add to MAINTAINERS
Thomas Huth [Wed, 12 Aug 2020 15:53:04 +0000 (17:53 +0200)] 
docs/system/target-avr: Improve the AVR docs and add to MAINTAINERS

The examples look nicer when using "::" code blocks.
Also mention that "-d in_asm" only outputs instructions that have not
been translated by the JIT layer yet.
And while we're at it, also add the AVR doc file to the MAINTAINERS file.

Signed-off-by: Thomas Huth <huth@tuxfamily.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Michael Rolnik <mrolnik@gmail.com>
Message-Id: <20200812155304.18016-1-huth@tuxfamily.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
12 months agomailmap: Add entry for Greg Kurz
Greg Kurz [Wed, 12 Aug 2020 15:37:31 +0000 (17:37 +0200)] 
mailmap: Add entry for Greg Kurz

I had stopped using gkurz@linux.vnet.ibm.com a while back already but
this email address was shutdown last June when I quit IBM. It's about
time to map it to groug@kaod.org.

Signed-off-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <159724665142.75339.817685642171828648.stgit@bahia.lan>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
12 months agoutil/vfio-helpers: Fix typo in description
Philippe Mathieu-Daudé [Tue, 11 Aug 2020 15:16:43 +0000 (17:16 +0200)] 
util/vfio-helpers: Fix typo in description

Remove the second 'and' introduced in commit 418026ca43
("util: Introduce vfio helpers").

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Li Qiang <liq3ea@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20200811151643.21293-4-philmd@redhat.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
12 months agoutil/qemu-timer: Fix typo in description
Philippe Mathieu-Daudé [Tue, 11 Aug 2020 15:16:42 +0000 (17:16 +0200)] 
util/qemu-timer: Fix typo in description

Remove the second 'and' introduced in commit e81f86790f ("qemu-timer:
avoid checkpoints for virtual clock timers in external subsystems").

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Li Qiang <liq3ea@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20200811151643.21293-3-philmd@redhat.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
12 months agohw/i2c: Fix typo in description
Philippe Mathieu-Daudé [Tue, 11 Aug 2020 15:16:41 +0000 (17:16 +0200)] 
hw/i2c: Fix typo in description

Remove the second 'and' introduced in commit 73d5f22ecb
("hw/i2c: Document the I2C qdev helpers").

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Corey Minyard <cminyard@mvista.com>
Reviewed-by: Li Qiang <liq3ea@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20200811151643.21293-2-philmd@redhat.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
12 months ago.mailmap: Update Paul Burton email address
Philippe Mathieu-Daudé [Tue, 7 Jul 2020 02:25:44 +0000 (04:25 +0200)] 
.mailmap: Update Paul Burton email address

Following the Linux kernel equivalent patch posted on
linux-mips@vger.kernel.org [*], update Paul Burton email
address to avoid emails bouncing.

[*] 'MAINTAINERS: Use @kernel.org address for Paul Burton'
https://lore.kernel.org/patchwork/patch/1140341/

Cc: Paul Burton <paulburton@kernel.org>
Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Paul Burton <paulburton@kernel.org>
Message-Id: <20200707022544.24925-1-f4bug@amsat.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
12 months agodocs: Fix broken links
Han Han [Fri, 7 Aug 2020 10:17:36 +0000 (18:17 +0800)] 
docs: Fix broken links

Signed-off-by: Han Han <hhan@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20200807101736.3544506-1-hhan@redhat.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>