qemu.git
2 years agousb: ehci: fix memory leak in ehci_process_itd
Li Qiang [Mon, 19 Sep 2016 02:48:35 +0000 (19:48 -0700)] 
usb: ehci: fix memory leak in ehci_process_itd

While processing isochronous transfer descriptors(iTD), if the page
select(PG) field value is out of bands it will return. In this
situation the ehci's sg list is not freed thus leading to a memory
leak issue. This patch avoid this.

Signed-off-by: Li Qiang <liqiang6-s@360.cn>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2 years agoqapi: make the json schema files more regular.
David Anderson [Thu, 22 Sep 2016 04:00:19 +0000 (21:00 -0700)] 
qapi: make the json schema files more regular.

This makes it easier to parse the schema file for tool generation:
each paragraph is either a non-docstring comment, or a docstring
immediately followed by a Python dict describing an API item.

Signed-off-by: David Anderson <dave@natulte.net>
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2 years agomaint: Add module_block.h to .gitignore
Lin Ma [Fri, 23 Sep 2016 09:16:06 +0000 (17:16 +0800)] 
maint: Add module_block.h to .gitignore

Commit 0c0c1fd9 generated module_block.h automatically, Add it to .gitignore to
avoid checking in it by 'git add .'.

Signed-off-by: Lin Ma <lma@suse.com>
Reviewed-by: Fam Zheng <famz@redhat.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2 years agoMAINTAINERS: Some updates related to the SH4 machines
Thomas Huth [Fri, 30 Sep 2016 09:32:02 +0000 (11:32 +0200)] 
MAINTAINERS: Some updates related to the SH4 machines

hw/intc/sh_intc.c and hw/timer/sh_timer.c seem to belong to
the R2D machine, as far as I can see.
And concerning the Shix machine, it does not make much sense
to have a "M:" entry here and the "S:" set to "Orphan". So
I'd like to suggest to use "Odd Fixes" here instead.

Signed-off-by: Thomas Huth <huth@tuxfamily.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2 years agoMAINTAINERS: Add some more MIPS related files
Thomas Huth [Fri, 30 Sep 2016 07:26:51 +0000 (09:26 +0200)] 
MAINTAINERS: Add some more MIPS related files

The MIPS section is missing some related header files, and files
in the hw/misc/, hw/intc/ and hw/timer/ folders.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2 years agoMAINTAINERS: Add usermode related config files
Thomas Huth [Fri, 30 Sep 2016 07:07:15 +0000 (09:07 +0200)] 
MAINTAINERS: Add usermode related config files

The default-configs/*-linux-user.mak belong to Linux usermode
emulation, and default-configs/*-bsd-user.mak belong to BSD
usermode emulation.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2 years agoMAINTAINERS: Add some more pattern to recognize all win32 related files
Thomas Huth [Thu, 29 Sep 2016 07:43:31 +0000 (09:43 +0200)] 
MAINTAINERS: Add some more pattern to recognize all win32 related files

The get_maintainer.pl script currently thinks that the win32
related files in the util and include folders are currently
unmaintained. Thus let's add some additional wildcards to
match these files.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Stefan Weil <sw@weilnetz.de>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2 years agoMAINTAINERS: Add some more rocker related files
Thomas Huth [Tue, 27 Sep 2016 14:33:46 +0000 (16:33 +0200)] 
MAINTAINERS: Add some more rocker related files

The files in tests/rocker/ and docs/specs/rocker.txt
should be listed in the Rocker section of MAINTAINERS.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2 years agoMAINTAINERS: Add header files to CRIS section
Thomas Huth [Fri, 23 Sep 2016 16:08:46 +0000 (18:08 +0200)] 
MAINTAINERS: Add header files to CRIS section

etraxfs_dma.h and etraxfs.h in include/hw/cris/ obviously belong
to the CRIS section in MAINTAINERS.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2 years agoMAINTAINERS: Add some more files to the virtio section
Thomas Huth [Fri, 23 Sep 2016 16:11:21 +0000 (18:11 +0200)] 
MAINTAINERS: Add some more files to the virtio section

Makefile.objs and trace-events in hw/virtio/ were not covered
by MAINTAINERS yet.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2 years agoMAINTAINERS: Add some SPARC machine related files
Thomas Huth [Mon, 19 Sep 2016 19:58:34 +0000 (21:58 +0200)] 
MAINTAINERS: Add some SPARC machine related files

And while we're at it, remove Blue Swirl from the list
of maintainers. Blue has apparently been inactive for
quite a while now, so I assume he's unfortunately
not available as maintainer anymore.

Signed-off-by: Thomas Huth <huth@tuxfamily.org>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2 years agoMAINTAINERS: Add include/hw/audio/ to audio section
Thomas Huth [Fri, 23 Sep 2016 13:19:10 +0000 (15:19 +0200)] 
MAINTAINERS: Add include/hw/audio/ to audio section

audio.h and pcspk.h are recognized as maintained files now.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2 years agoMAINTAINERS: Add some more files to the HMP section
Thomas Huth [Thu, 22 Sep 2016 19:32:38 +0000 (21:32 +0200)] 
MAINTAINERS: Add some more files to the HMP section

The hmp-commands-info.hx, hmp.h and include/monitor/hmp-target.h
files were classified as unmaintained. Let's add them to the
HMP section.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Luiz Capitulino <lcapitulino@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2 years agoMAINTAINERS: Add files to the Moxie section.
Thomas Huth [Thu, 22 Sep 2016 19:16:33 +0000 (21:16 +0200)] 
MAINTAINERS: Add files to the Moxie section.

The hw/moxie/ folder and default-configs/moxie-softmmu.mak
obviously belong to the Moxie CPU.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2 years agotests: Ignore test executables
Eric Blake [Tue, 20 Sep 2016 14:43:01 +0000 (09:43 -0500)] 
tests: Ignore test executables

Commits 9ef8112a and efad6682 introduced new tests, but forgot
to ignore the built executables from an in-tree build.

Signed-off-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Alberto Garcia <berto@igalia.com>
Reviewed-by: Fam Zheng <famz@redhat.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2 years agobt-hci-csr: drop unused argument
Paolo Bonzini [Wed, 14 Sep 2016 09:57:53 +0000 (11:57 +0200)] 
bt-hci-csr: drop unused argument

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2 years agoqemu-options.hx: fix -chardev ringbuf typos
Stefan Hajnoczi [Mon, 19 Sep 2016 10:56:26 +0000 (11:56 +0100)] 
qemu-options.hx: fix -chardev ringbuf typos

Clean up the documentation for -chardev ringbuf.  There is a stray
closing parenthesis and the comma is unnecessary.

Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
2 years agobsd-user: fix FreeBSD build after d148d90e
Ed Maste [Tue, 4 Oct 2016 20:02:49 +0000 (16:02 -0400)] 
bsd-user: fix FreeBSD build after d148d90e

Signed-off-by: Ed Maste <emaste@freebsd.org>
Message-id: 1475611369-74971-1-git-send-email-emaste@freebsd.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoMerge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.8-20161006' into staging
Peter Maydell [Thu, 6 Oct 2016 12:34:00 +0000 (13:34 +0100)] 
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-2.8-20161006' into staging

ppc patch queue 2016-10-06

Currently accumulated target-ppc and spapr machine related patches.
  - More POWER9 instruction implementations
  - Additional test case / enabling of test cases for Power
  - Assorted fixes

# gpg: Signature made Thu 06 Oct 2016 07:05:07 BST
# gpg:                using RSA key 0x6C38CACA20D9B392
# gpg: Good signature from "David Gibson <david@gibson.dropbear.id.au>"
# gpg:                 aka "David Gibson (Red Hat) <dgibson@redhat.com>"
# gpg:                 aka "David Gibson (ozlabs.org) <dgibson@ozlabs.org>"
# gpg:                 aka "David Gibson (kernel.org) <dwg@kernel.org>"
# Primary key fingerprint: 75F4 6586 AE61 A66C C44E  87DC 6C38 CACA 20D9 B392

* remotes/dgibson/tags/ppc-for-2.8-20161006: (29 commits)
  hw/ppc/spapr: Use POWER8 by default for the pseries-2.8 machine
  tests/pxe: Use -nodefaults to speed up ppc64/ipv6 pxe test
  spapr: fix check of cpu alias name in spapr_get_cpu_core_type()
  tests: enable ohci/uhci/xhci tests on PPC64
  libqos: use generic qtest_shutdown()
  libqos: add PCI management in qtest_vboot()/qtest_shutdown()
  libqos: add PPC64 PCI support
  target-ppc: fix vmx instruction type/type2
  target-ppc/kvm: Enable transactional memory on POWER8 with KVM-HV, too
  target-ppc/kvm: Add a wrapper function to check for KVM-PR
  MAINTAINERS: Add two more ppc related files
  target-ppc: Implement mtvsrws instruction
  target-ppc: add vclzlsbb/vctzlsbb instructions
  target-ppc: add vector compare not equal instructions
  target-ppc: fix invalid mask - cmpl, bctar
  target-ppc: add stxvb16x instruction
  target-ppc: add lxvb16x instruction
  target-ppc: add stxvh8x instruction
  target-ppc: add lxvh8x instruction
  target-ppc: improve stxvw4x implementation
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agorules.mak: quiet-command: Split command name and args to print
Peter Maydell [Tue, 4 Oct 2016 16:27:21 +0000 (17:27 +0100)] 
rules.mak: quiet-command: Split command name and args to print

The quiet-command make rule currently takes two arguments:
the command and arguments to run, and a string to print if
the V flag is not set (ie we are not being verbose).
By convention, the string printed is of the form
"  NAME   some args". Unfortunately to get nicely lined up
output all the strings have to agree about what column the
arguments should start in, which means that if we add a
new quiet-command usage which wants a slightly longer CMD
name then we either put up with misalignment or change
every quiet-command string.

Split the quiet-mode string into two, the "NAME" and
the "same args" part, and use printf(1) to format the
string automatically. This means we only need to change
one place if we want to support a longer maximum name.

In particular, we can now print 7-character names lined
up properly (they are needed for the OSX "SETTOOL" invocation).

Change all the uses of quiet-command to the new syntax.
(Any which are missed or inadvertently reintroduced
via later merges will result in slightly misformatted
quiet output rather than disaster.)

A few places in the pc-bios/ makefiles are updated to use
"BUILD", "SIGN" and "STRIP" rather than "Building",
"Signing" and "Stripping" for consistency and to keep them
below 7 characters. Module .mo links now print "LD" rather
than the nonstandard "LD -r".

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Eric Blake <eblake@redhat.com>
Message-id: 1475598441-27908-1-git-send-email-peter.maydell@linaro.org

2 years agohw/ppc/spapr: Use POWER8 by default for the pseries-2.8 machine
Thomas Huth [Wed, 5 Oct 2016 07:44:51 +0000 (09:44 +0200)] 
hw/ppc/spapr: Use POWER8 by default for the pseries-2.8 machine

A couple of distributors are compiling their distributions
with "-mcpu=power8" for ppc64le these days, so the user sooner
or later runs into a crash there when not explicitely specifying
the "-cpu POWER8" option to QEMU (which is currently using POWER7
for the "pseries" machine by default). Due to this reason, the
linux-user target already switched to POWER8 a while ago (see commit
de3f1b98410e0d5b406a0df3a48547b559d18602). Since the softmmu target
of course has the same problem, we should switch there to POWER8 for
the newer machine types, too.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2 years agotests/pxe: Use -nodefaults to speed up ppc64/ipv6 pxe test
Thomas Huth [Wed, 5 Oct 2016 12:52:09 +0000 (14:52 +0200)] 
tests/pxe: Use -nodefaults to speed up ppc64/ipv6 pxe test

SLOF is unfortunately quite slow when running with TCG, so
the pxe test is also performing rather slow here. By using
"-nodefaults" we can disable some devices (vscsi) that we
are not interested in here, so that SLOF does not have to
scan them during boot and thus starts up a little bit faster.
The ppc64 pxe-test now only takes 27 seconds on my laptop
instead of 33 seconds.
The "-nodefaults" flag seems to work fine for the x86 tests,
too, so it is added here unconditionally here (though there
is no speed-up on x86 by using this flag).

Suggested-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Laurent Vivier <lvivier@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2 years agospapr: fix check of cpu alias name in spapr_get_cpu_core_type()
Greg Kurz [Mon, 3 Oct 2016 12:13:20 +0000 (14:13 +0200)] 
spapr: fix check of cpu alias name in spapr_get_cpu_core_type()

If the user passes an alias name and a property to -cpu, QEMU fails to
find the CPU definition and exits.

$ qemu-system-ppc64 -cpu POWER8E,compat=power7
qemu-system-ppc64: Unable to find sPAPR CPU Core definition

This happens because spapr_get_cpu_core_type() passes the full string from
the command line (i.e. "POWER8E,compat=power7") to ppc_cpu_lookup_alias(),
instead of the alias name piece only (i.e. "POWER8E").

The fix is to pass model_pieces[0] to ppc_cpu_lookup_alias().

Signed-off-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2 years agotests: enable ohci/uhci/xhci tests on PPC64
Laurent Vivier [Thu, 29 Sep 2016 10:32:47 +0000 (12:32 +0200)] 
tests: enable ohci/uhci/xhci tests on PPC64

Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2 years agolibqos: use generic qtest_shutdown()
Laurent Vivier [Thu, 29 Sep 2016 10:32:46 +0000 (12:32 +0200)] 
libqos: use generic qtest_shutdown()

Machine specific shutdown function can be registered by
the machine specific qtest_XXX_boot() if needed.

So we will not have to test twice the architecture (on boot and on
shutdown) if the test can be run on several architectures.

Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2 years agolibqos: add PCI management in qtest_vboot()/qtest_shutdown()
Laurent Vivier [Thu, 29 Sep 2016 10:32:45 +0000 (12:32 +0200)] 
libqos: add PCI management in qtest_vboot()/qtest_shutdown()

Signed-off-by: Laurent Vivier <lvivier@redhat.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2 years agolibqos: add PPC64 PCI support
Laurent Vivier [Thu, 29 Sep 2016 10:32:44 +0000 (12:32 +0200)] 
libqos: add PPC64 PCI support

Signed-off-by: Laurent Vivier <lvivier@redhat.com>
[dwg: Fixed build problem on 32-bit hosts]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2 years agotarget-ppc: fix vmx instruction type/type2
Nikunj A Dadhania [Thu, 29 Sep 2016 10:22:37 +0000 (15:52 +0530)] 
target-ppc: fix vmx instruction type/type2

A few of the new instructions added inadvertently changed the type of
old instruction(PPC_ALTIVEC) to PPC2_ALTIVEC_207 in the dual form
declaration.

commit: b5d569a1 (target-ppc: add vector extract instructions)
commit: e7b1e06f (target-ppc: add vector insert instructions)
commit: 3aa56a19 (target-ppc: add vector compare not equal instructions)

New ISA 3.0 instructions added:
    vextractub     PPC_NONE     PPC2_ISA300
    vextractuh     PPC_NONE     PPC2_ISA300
    vextractuw     PPC_NONE     PPC2_ISA300
    vinsertb       PPC_NONE     PPC2_ISA300
    vinserth       PPC_NONE     PPC2_ISA300
    vinsertw       PPC_NONE     PPC2_ISA300
    vcmpneb        PPC_NONE     PPC2_ISA300
    vcmpneh        PPC_NONE     PPC2_ISA300
    vcmpnew        PPC_NONE     PPC2_ISA300

Affected older instructions:
    vspltb         PPC_ALTIVEC  PPC_NONE
    vsplth         PPC_ALTIVEC  PPC_NONE
    vspltw         PPC_ALTIVEC  PPC_NONE
    vspltisb       PPC_ALTIVEC  PPC_NONE
    vspltish       PPC_ALTIVEC  PPC_NONE
    vspltisw       PPC_ALTIVEC  PPC_NONE
    vcmpequb       PPC_ALTIVEC  PPC_NONE
    vcmpequh       PPC_ALTIVEC  PPC_NONE
    vcmpequw       PPC_ALTIVEC  PPC_NONE

Change the instruction type/type2 for the older instructions back to
what it was(PPC_ALTIVEC).

CC: Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com>
Reported-by: Bharata B Rao <bharata@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2 years agotarget-ppc/kvm: Enable transactional memory on POWER8 with KVM-HV, too
Thomas Huth [Thu, 29 Sep 2016 10:48:07 +0000 (12:48 +0200)] 
target-ppc/kvm: Enable transactional memory on POWER8 with KVM-HV, too

Transactional memory is also supported on POWER8 KVM-HV if the
KVM_CAP_PPC_HTM is not available in the kernel yet, so add a hack
to allow TM here, too.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2 years agotarget-ppc/kvm: Add a wrapper function to check for KVM-PR
Thomas Huth [Thu, 29 Sep 2016 10:48:06 +0000 (12:48 +0200)] 
target-ppc/kvm: Add a wrapper function to check for KVM-PR

It makes more sense if we have a proper function to check
for KVM-PR than to check for the GET_PVINFO extension all
over the place.

Signed-off-by: Thomas Huth <thuth@redhat.com>
[dwg: Expanded a comment to discourage overuse of this function]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2 years agoMAINTAINERS: Add two more ppc related files
Thomas Huth [Thu, 29 Sep 2016 07:40:33 +0000 (09:40 +0200)] 
MAINTAINERS: Add two more ppc related files

The file hw/intc/heathrow_pic.c belongs to the Old World Mac
machine, and pc-bios/ppc_rom.bin belongs to the PReP machine.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2 years agotarget-ppc: Implement mtvsrws instruction
Ravi Bangoria [Thu, 29 Sep 2016 03:52:17 +0000 (09:22 +0530)] 
target-ppc: Implement mtvsrws instruction

mtvsrws: Move To VSR Word & Splat

Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2 years agotarget-ppc: add vclzlsbb/vctzlsbb instructions
Rajalakshmi Srinivasaraghavan [Wed, 28 Sep 2016 05:45:18 +0000 (11:15 +0530)] 
target-ppc: add vclzlsbb/vctzlsbb instructions

The following vector instructions are added from ISA 3.0.

vclzlsbb - Vector Count Leading Zero Least-Significant Bits Byte
vctzlsbb - Vector Count Trailing Zero Least-Significant Bits Byte

Signed-off-by: Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2 years agotarget-ppc: add vector compare not equal instructions
Rajalakshmi Srinivasaraghavan [Wed, 28 Sep 2016 05:45:17 +0000 (11:15 +0530)] 
target-ppc: add vector compare not equal instructions

The following vector compare not equal instructions are added from ISA 3.0.

vcmpneb - Vector Compare Not Equal Byte
vcmpneh - Vector Compare Not Equal Halfword
vcmpnew - Vector Compare Not Equal Word

Signed-off-by: Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2 years agotarget-ppc: fix invalid mask - cmpl, bctar
Avinesh Kumar [Wed, 28 Sep 2016 05:45:16 +0000 (11:15 +0530)] 
target-ppc: fix invalid mask - cmpl, bctar

cmpl:  invalid bit mask should be 0x00400001
bctar: invalid bit mask should be 0x0000E000

Signed-off-by: Avinesh Kumar <avinesku@linux.vnet.ibm.com>
Signed-off-by: Rajalakshmi Srinivasaraghavan <raji@linux.vnet.ibm.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2 years agotarget-ppc: add stxvb16x instruction
Nikunj A Dadhania [Wed, 28 Sep 2016 18:42:00 +0000 (00:12 +0530)] 
target-ppc: add stxvb16x instruction

stxvb16x: Store VSX Vector Byte*16

Vector (8-bit elements):
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
|F0|F1|F2|F3|F4|F5|F6|F7|E0|E1|E2|E3|E4|E5|E6|E7|
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+

Store results in following:

Little/Big-endian Storage
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
|F0|F1|F2|F3|F4|F5|F6|F7|E0|E1|E2|E3|E4|E5|E6|E7|
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2 years agotarget-ppc: add lxvb16x instruction
Nikunj A Dadhania [Wed, 28 Sep 2016 18:41:59 +0000 (00:11 +0530)] 
target-ppc: add lxvb16x instruction

lxvb16x: Load VSX Vector Byte*16

Little/Big-endian Storage
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
|F0|F1|F2|F3|F4|F5|F6|F7|E0|E1|E2|E3|E4|E5|E6|E7|
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+

Vector load results in (8-bit elements):
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+
|F0|F1|F2|F3|F4|F5|F6|F7|E0|E1|E2|E3|E4|E5|E6|E7|
+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2 years agotarget-ppc: add stxvh8x instruction
Nikunj A Dadhania [Wed, 28 Sep 2016 18:41:58 +0000 (00:11 +0530)] 
target-ppc: add stxvh8x instruction

stxvh8x:  Store VSX Vector Halfword*8

Vector (16-bit elements):
+------+------+------+------+------+------+------+------+
| 0001 | 1011 | 2021 | 3031 | 4041 | 5051 | 6061 | 7071 |
+------+------+------+------+------+------+------+------+

Store results in following:

Big-Endian Storage
+-------+-------+-------+-------+-------+-------+-------+-------+
| 00 01 | 10 11 | 20 21 | 30 31 | 40 41 | 50 51 | 60 61 | 70 71 |
+-------+-------+-------+-------+-------+-------+-------+-------+

Little-Endian Storage
+-------+-------+-------+-------+-------+-------+-------+-------+
| 01 00 | 11 10 | 21 20 | 31 30 | 41 40 | 51 50 | 61 60 | 71 70 |
+-------+-------+-------+-------+-------+-------+-------+-------+

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
[dwg: Tweak commit description]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2 years agotarget-ppc: add lxvh8x instruction
Nikunj A Dadhania [Wed, 28 Sep 2016 18:41:57 +0000 (00:11 +0530)] 
target-ppc: add lxvh8x instruction

lxvh8x:  Load VSX Vector Halfword*8

Big-Endian Storage
+-------+-------+-------+-------+-------+-------+-------+-------+
| 00 01 | 10 11 | 20 21 | 30 31 | 40 41 | 50 51 | 60 61 | 70 71 |
+-------+-------+-------+-------+-------+-------+-------+-------+

Little-Endian Storage
+-------+-------+-------+-------+-------+-------+-------+-------+
| 01 00 | 11 10 | 21 20 | 31 30 | 41 40 | 51 50 | 61 60 | 71 70 |
+-------+-------+-------+-------+-------+-------+-------+-------+

Vector load results in (16-bit elements):
+------+------+------+------+------+------+------+------+
| 0001 | 1011 | 2021 | 3031 | 4041 | 5051 | 6061 | 7071 |
+------+------+------+------+------+------+------+------+

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
[dwg: Tweak to commit description]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2 years agotarget-ppc: improve stxvw4x implementation
Nikunj A Dadhania [Wed, 28 Sep 2016 18:41:56 +0000 (00:11 +0530)] 
target-ppc: improve stxvw4x implementation

Manipulate data and store 8bytes instead of 4bytes.

Vector (32-bit elements):
+----------+----------+----------+----------+
00112233 | 44556677 | 8899AABB | CCDDEEFF |
+----------+----------+----------+----------+

Store results in following:

Big-Endian Storage
+-------------+-------------+-------------+-------------+
| 00 11 22 33 | 44 55 66 77 | 88 99 AA BB | CC DD EE FF |
+-------------+-------------+-------------+-------------+

Little-Endian Storage
+-------------+-------------+-------------+-------------+
| 33 22 11 00 | 77 66 55 44 | BB AA 99 88 | FF EE DD CC |
+-------------+-------------+-------------+-------------+

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2 years agotarget-ppc: improve lxvw4x implementation
Nikunj A Dadhania [Wed, 28 Sep 2016 18:41:55 +0000 (00:11 +0530)] 
target-ppc: improve lxvw4x implementation

Load 8byte at a time and manipulate.

Big-Endian Storage
+-------------+-------------+-------------+-------------+
| 00 11 22 33 | 44 55 66 77 | 88 99 AA BB | CC DD EE FF |
+-------------+-------------+-------------+-------------+

Little-Endian Storage
+-------------+-------------+-------------+-------------+
| 33 22 11 00 | 77 66 55 44 | BB AA 99 88 | FF EE DD CC |
+-------------+-------------+-------------+-------------+

Vector load results in (32-bit elements):
+----------+----------+----------+----------+
00112233 | 44556677 | 8899AABB | CCDDEEFF |
+----------+----------+----------+----------+

Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
[dwg: Slight tweak to commit description]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2 years agotarget-ppc: Implement mtvsrdd instruction
Ravi Bangoria [Wed, 28 Sep 2016 18:41:53 +0000 (00:11 +0530)] 
target-ppc: Implement mtvsrdd instruction

mtvsrdd: Move To VSR Double Doubleword

Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2 years agotarget-ppc: Implement mfvsrld instruction
Ravi Bangoria [Wed, 28 Sep 2016 18:41:52 +0000 (00:11 +0530)] 
target-ppc: Implement mfvsrld instruction

mfvsrld: Move From VSR Lower Doubleword

Signed-off-by: Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2 years agoppc: Check the availability of transactional memory
Thomas Huth [Wed, 28 Sep 2016 11:16:30 +0000 (13:16 +0200)] 
ppc: Check the availability of transactional memory

KVM-PR currently does not support transactional memory, and the
implementation in TCG is just a fake. We should not announce TM
support in the ibm,pa-features property when running on such a
system, so disable it by default and only enable it if the KVM
implementation supports it (i.e. recent versions of KVM-HV).
These changes are based on some earlier work from Anton Blanchard
(thanks!).

Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2 years agohw/ppc/spapr: Fix the selection of the processor features
Thomas Huth [Wed, 28 Sep 2016 11:16:29 +0000 (13:16 +0200)] 
hw/ppc/spapr: Fix the selection of the processor features

The current code uses pa_features_206 for POWERPC_MMU_2_06, and
for everything else, it uses pa_features_207. This is bad in some
cases because there is also a "degraded" MMU version of ISA 2.06,
called POWERPC_MMU_2_06a, which should of course use the flags for
2.06 instead. And there is also the possibility that the user runs
the pseries machine with a POWER5+ or even 970 processor. In that
case we certainly do not want to set the flags for 2.07, and rather
simply skip the setting of the pa-features property instead.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2 years agohw/ppc/spapr: Move code related to "ibm,pa-features" to a separate function
Thomas Huth [Wed, 28 Sep 2016 11:16:28 +0000 (13:16 +0200)] 
hw/ppc/spapr: Move code related to "ibm,pa-features" to a separate function

The function spapr_populate_cpu_dt() has become quite big
already, and since we likely have to extend the pa-features
property for every new processor generation, it is nicer
if we put the related code into a separate function.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2 years agopseries: Add 2.8 machine type, set up compatibility macros
David Gibson [Wed, 28 Sep 2016 04:31:55 +0000 (14:31 +1000)] 
pseries: Add 2.8 machine type, set up compatibility macros

Now that 2.7 is released, create the pseries-2.8 machine type and add the
boilerplate compatiblity macro stuff.  There's nothing new to put into the
2.7 compatiliby properties yet, but we'll need something eventually, so
we might as well get it ready now.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2 years agotests: Test IPv6 and ppc64 in the PXE tester
Thomas Huth [Mon, 26 Sep 2016 20:17:46 +0000 (22:17 +0200)] 
tests: Test IPv6 and ppc64 in the PXE tester

The firmware of the pseries machine, SLOF, is able to load files via
IPv6 networking, too. So to test both, network bootloading on ppc64
and IPv6 (via Slirp) , let's add some PXE tests for this environment,
too. Since we can not use the normal x86 boot sector for network boot
loading, we use a simple Forth script on ppc64 instead.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2 years agospapr_vscsi: fix build error introduced by f19661c8
Felipe Franciosi [Mon, 26 Sep 2016 14:17:44 +0000 (15:17 +0100)] 
spapr_vscsi: fix build error introduced by f19661c8

A typo introduced in f19661c8 prevents qemu from building when configured
with --enable-trace-backend=dtrace.

Signed-off-by: Felipe Franciosi <felipe@nutanix.com>
Reviewed-by: Laurent Vivier <lvivier@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2 years agoMerge remote-tracking branch 'remotes/dgilbert/tags/pull-hmp-20161004' into staging
Peter Maydell [Tue, 4 Oct 2016 17:57:12 +0000 (18:57 +0100)] 
Merge remote-tracking branch 'remotes/dgilbert/tags/pull-hmp-20161004' into staging

HMP pull

Just Wanpeng's pull request this time, but
this pull is as much about me checking out my
process.

# gpg: Signature made Tue 04 Oct 2016 18:24:10 BST
# gpg:                using RSA key 0x0516331EBC5BFDE7
# gpg: Good signature from "Dr. David Alan Gilbert (RH2) <dgilbert@redhat.com>"
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg:          It is not certain that the signature belongs to the owner.
# Primary key fingerprint: 45F5 C71B 4A0C B7FB 977A  9FA9 0516 331E BC5B FDE7

* remotes/dgilbert/tags/pull-hmp-20161004:
  hmp: fix qemu crash due to ioapic state dump w/ split irqchip

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohmp: fix qemu crash due to ioapic state dump w/ split irqchip
Wanpeng Li [Fri, 23 Sep 2016 03:47:36 +0000 (11:47 +0800)] 
hmp: fix qemu crash due to ioapic state dump w/ split irqchip

The qemu will crash when info ioapic through hmp if irqchip
is split. Below message is splat:

KVM_GET_IRQCHIP failed: Unknown error -6

This patch fix it by dumping the ioapic state from the qemu
emulated ioapic if irqchip is split.

Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Richard Henderson <rth@twiddle.net>
Cc: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Wanpeng Li <wanpeng.li@hotmail.com>
Message-Id: <1474602456-3232-1-git-send-email-wanpeng.li@hotmail.com>
Reviewed-by: Peter Xu <peterx@redhat.com>
Message-ID: <20160923090824.GF15411@pxdev.xzpeter.org>
Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
2 years agoMerge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging
Peter Maydell [Tue, 4 Oct 2016 13:25:08 +0000 (14:25 +0100)] 
Merge remote-tracking branch 'remotes/kevin/tags/for-upstream' into staging

Block layer patches

# gpg: Signature made Thu 29 Sep 2016 14:11:30 BST
# gpg:                using RSA key 0x7F09B272C88F2FD6
# gpg: Good signature from "Kevin Wolf <kwolf@redhat.com>"
# Primary key fingerprint: DC3D EB15 9A9A F95D 3D74  56FE 7F09 B272 C88F 2FD6

* remotes/kevin/tags/for-upstream:
  oslib-posix: add a configure switch to debug stack usage
  coroutine-sigaltstack: use helper for allocating stack memory
  coroutine-ucontext: use helper for allocating stack memory
  coroutine: add a macro for the coroutine stack size
  coroutine-sigaltstack: rename coroutine struct appropriately
  oslib-posix: add helpers for stack alloc and free
  block: Remove qemu_root_bds_opts
  block: Move 'discard' option to bdrv_open_common()
  block: Use 'detect-zeroes' option for 'blockdev-change-medium'
  block: Parse 'detect-zeroes' in bdrv_open_common()
  block/qapi: Move 'aio' option to file driver
  block/qapi: Use separate options type for curl driver
  block: Drop aio/cache consistency check from qmp_blockdev_add()
  block: Fix error path in qmp_blockdev_change_medium()
  block-backend: remove blk_flush_all
  qemu: use bdrv_flush_all for vm_stop et al
  block: reintroduce bdrv_flush_all

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoMerge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20161004' into...
Peter Maydell [Tue, 4 Oct 2016 12:48:25 +0000 (13:48 +0100)] 
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20161004' into staging

target-arm queue:
 * Netduino 2 improvements (SPI, ADC devices)
 * fix some Mainstone key mappings
 * vmstateify tsc210x, tsc2005
 * virt: add 2.8 machine type
 * virt: support in-kernel GICv3 ITS
 * generic-loader device
 * A64: fix iss_sf decoding in disas_ld_lit
 * correctly handle 'sub pc, pc, 1' for ARMv6

# gpg: Signature made Tue 04 Oct 2016 13:41:34 BST
# gpg:                using RSA key 0x3C2525ED14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
# gpg:                 aka "Peter Maydell <pmaydell@gmail.com>"
# gpg:                 aka "Peter Maydell <pmaydell@chiark.greenend.org.uk>"
# Primary key fingerprint: E1A5 C593 CD41 9DE2 8E83  15CF 3C25 25ED 1436 0CDE

* remotes/pmaydell/tags/pull-target-arm-20161004: (27 commits)
  target-arm: Correctly handle 'sub pc, pc, 1' for ARMv6
  target-arm: A64: Fix decoding of iss_sf in disas_ld_lit
  cadence_gem: Fix priority queue out of bounds access
  docs: Add a generic loader explanation document
  generic-loader: Add a generic loader
  ARM: Virt: ACPI: Add GIC ITS description in ACPI MADT table
  ACPI: Add GIC Interrupt Translation Service Structure definition
  arm/virt: Add ITS to the virt board
  hw/intc/arm_gicv3_its: Implement support for in-kernel ITS emulation
  kvm-all: Pass requester ID to MSI routing functions
  target-arm: move gicv3_class_name from machine to kvm_arm.h
  hw/intc/arm_gicv3_its: Implement ITS base class
  hw/intc/arm_gic(v3)_kvm: Initialize gsi routing
  hw/arm/virt: add 2.8 machine type
  vmstateify tsc210x
  vmstateify tsc2005
  hw/arm: Fix Integrator/CM initialization
  mainstone: Add mapping for dot, slash and backspace.
  mainstone: Fix incorrect key mapping for Enter key.
  MAINTAINERS: Add Alistair to the maintainers list
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agotarget-arm: Correctly handle 'sub pc, pc, 1' for ARMv6
Peter Maydell [Tue, 4 Oct 2016 12:28:10 +0000 (13:28 +0100)] 
target-arm: Correctly handle 'sub pc, pc, 1' for ARMv6

In the ARM v6 architecture, 'sub pc, pc, 1' is not an interworking
branch, so the computed new value is written to r15 as a normal
value. The architecture says that in this case, bits [1:0] of
the value written must be ignored if we are in ARM mode (or
bit [0] ignored if in Thumb mode); this is a change from the
ARMv4/v5 specification that behaviour is UNPREDICTABLE.
Use the correct mask on the PC value when doing a non-interworking
store to PC.

A popular library used on RaspberryPi uses this instruction
as part of a trick to determine whether it is running on
ARMv6 or ARMv7, and we were mishandling the sequence.

Fixes bug: https://bugs.launchpad.net/bugs/1625295

Reported-by: <stu.axon@gmail.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1474380941-4730-1-git-send-email-peter.maydell@linaro.org

2 years agotarget-arm: A64: Fix decoding of iss_sf in disas_ld_lit
Edgar E. Iglesias [Tue, 4 Oct 2016 12:28:10 +0000 (13:28 +0100)] 
target-arm: A64: Fix decoding of iss_sf in disas_ld_lit

Fix the decoding of iss_sf in disas_ld_lit.
The SF (Sixty-Four) field in the ISS (Instruction Specific Syndrome)
is a bit that specifies the width of the register that the
instruction loads to.

If cleared it specifies 32 bits.
If set it specifies 64 bits.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-id: 1475230780-8669-1-git-send-email-edgar.iglesias@gmail.com
[PMM: tweaked phrasing per on-list discussion]
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agocadence_gem: Fix priority queue out of bounds access
Alistair Francis [Tue, 4 Oct 2016 12:28:09 +0000 (13:28 +0100)] 
cadence_gem: Fix priority queue out of bounds access

There was an error with some of the register implementation assuming
there are 16 priority queues supported when the IP only supports 8. This
patch corrects the registers to only support 8 queues.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reported-by: Paolo Bonzini <pbonzini@redhat.com>
Message-id: 33bf2d28326d22875602234b8b15cf56fb678333.1474911607.git.alistair.francis@xilinx.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agodocs: Add a generic loader explanation document
Alistair Francis [Tue, 4 Oct 2016 12:28:09 +0000 (13:28 +0100)] 
docs: Add a generic loader explanation document

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 9d991a2df990cf55e2630410a5a03ea48930af5d.1475195078.git.alistair.francis@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agogeneric-loader: Add a generic loader
Alistair Francis [Tue, 4 Oct 2016 12:28:09 +0000 (13:28 +0100)] 
generic-loader: Add a generic loader

Add a generic loader to QEMU which can be used to load images or set
memory values.

Internally inside QEMU this is a device. It is a strange device that
provides no hardware interface but allows QEMU to monkey patch memory
specified when it is created. To be able to do this it has a reset
callback that does the memory operations.

This device allows the user to monkey patch memory. To be able to do
this it needs a backend to manage the datas, the same as other
memory-related devices. In this case as the backend is so trivial we
have merged it with the frontend instead of creating and maintaining a
seperate backend.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Markus Armbruster <armbru@redhat.com>
Message-id: 10f2a9dce5e5e11b6c6d959415b0ad6ee22bcba5.1475195078.git.alistair.francis@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoARM: Virt: ACPI: Add GIC ITS description in ACPI MADT table
Shannon Zhao [Tue, 4 Oct 2016 12:28:09 +0000 (13:28 +0100)] 
ARM: Virt: ACPI: Add GIC ITS description in ACPI MADT table

If GIC ITS is supported, add description in ACPI MADT table, then guest
could use ITS when booting with ACPI.

Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1474616617-366-9-git-send-email-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoACPI: Add GIC Interrupt Translation Service Structure definition
Shannon Zhao [Tue, 4 Oct 2016 12:28:09 +0000 (13:28 +0100)] 
ACPI: Add GIC Interrupt Translation Service Structure definition

ACPI Spec 6.0 introduces GIC Interrupt Translation Service Structure.
Here we add the definition of the Structure.

Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1474616617-366-8-git-send-email-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoarm/virt: Add ITS to the virt board
Pavel Fedin [Tue, 4 Oct 2016 12:28:09 +0000 (13:28 +0100)] 
arm/virt: Add ITS to the virt board

If supported by the configuration, ITS will be added automatically.

This patch also renames v2m_phandle to msi_phandle because it's now used
by both MSI implementations.

Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1474616617-366-7-git-send-email-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/intc/arm_gicv3_its: Implement support for in-kernel ITS emulation
Pavel Fedin [Tue, 4 Oct 2016 12:28:09 +0000 (13:28 +0100)] 
hw/intc/arm_gicv3_its: Implement support for in-kernel ITS emulation

The ITS control frame is in-kernel emulated while accesses to the
GITS_TRANSLATER are mediated through the KVM_SIGNAL_MSI ioctl (MSI
direct MSI injection advertised by the CAP_SIGNAL_MSI capability)

the kvm_gsi_direct_mapping is explicitly set to false to emphasize the
difference with GICv2M. Direct mapping cannot work with ITS since
the content of the MSI data is not the target interrupt ID but an
eventd id.

GSI routing is advertised (kvm_gsi_routing_allowed) as well as
msi/irqfd signaling (kvm_msi_via_irqfd_allowed).

The MSI frame (GITS_TRANSLATER) absolute GPA is computed on first
kvm_its_send_msi() call. It is then passed through KVM_SIGNAL_MSI
ioctl.

Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1474616617-366-6-git-send-email-eric.auger@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agokvm-all: Pass requester ID to MSI routing functions
Pavel Fedin [Tue, 4 Oct 2016 12:28:09 +0000 (13:28 +0100)] 
kvm-all: Pass requester ID to MSI routing functions

Introduce global kvm_msi_use_devid flag plus associated
kvm_msi_devid_required() macro. Passes the device ID,
if needed, while building the MSI route entry. Device IDs are
required by the ARM GICv3 ITS (IRQ remapping function is based on
this information).

Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1474616617-366-5-git-send-email-eric.auger@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agotarget-arm: move gicv3_class_name from machine to kvm_arm.h
Eric Auger [Tue, 4 Oct 2016 12:28:08 +0000 (13:28 +0100)] 
target-arm: move gicv3_class_name from machine to kvm_arm.h

Machine.c contains code related to migration. Let's move
gicv3_class_name to kvm_arm.h instead.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1474616617-366-4-git-send-email-eric.auger@redhat.com
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/intc/arm_gicv3_its: Implement ITS base class
Pavel Fedin [Tue, 4 Oct 2016 12:28:08 +0000 (13:28 +0100)] 
hw/intc/arm_gicv3_its: Implement ITS base class

This is the basic skeleton for both KVM and software-emulated ITS.
Since we already prepare status structure, we also introduce complete
VMState description. But, because we currently have no migratable
implementations, we also set unmigratable flag.

Signed-off-by: Pavel Fedin <p.fedin@samsung.com>
Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1474616617-366-3-git-send-email-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/intc/arm_gic(v3)_kvm: Initialize gsi routing
Eric Auger [Tue, 4 Oct 2016 12:28:08 +0000 (13:28 +0100)] 
hw/intc/arm_gic(v3)_kvm: Initialize gsi routing

Advertise gsi routing and set up irqchip routing entries for
GIC SPIs.

This is not mandated as long as MSI routing is not used
(because the kernel sets a default irqchip routing table).
However once MSI routing gets used (for VIRTIO-PCI vhost for
example), the first call to KVM_SET_GSI_ROUTING overrides the
kernel default irqchip table.

If no routing entry exists for the GSI, any IRQFD signaling for
this GSI will fail.

Signed-off-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1474616617-366-2-git-send-email-eric.auger@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/arm/virt: add 2.8 machine type
Andrew Jones [Tue, 4 Oct 2016 12:28:08 +0000 (13:28 +0100)] 
hw/arm/virt: add 2.8 machine type

Signed-off-by: Andrew Jones <drjones@redhat.com>
Message-id: 1474641676-25017-1-git-send-email-drjones@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agovmstateify tsc210x
Dr. David Alan Gilbert [Tue, 4 Oct 2016 12:28:08 +0000 (13:28 +0100)] 
vmstateify tsc210x

I'm now saving all 3 of the pll entries; only 2 were saved before.
There are a couple of times that were previously stored as offsets
from 'now' calculated before saving;  with vmstate it's easier
to store the 'now' and fix it up on reload.

Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Message-id: 1474977735-10156-3-git-send-email-dgilbert@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agovmstateify tsc2005
Dr. David Alan Gilbert [Tue, 4 Oct 2016 12:28:08 +0000 (13:28 +0100)] 
vmstateify tsc2005

I've converted the fields in it's main data structure
to fixed size types in ways that look sane.

Signed-off-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Message-id: 1474977735-10156-2-git-send-email-dgilbert@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agohw/arm: Fix Integrator/CM initialization
Jakub Jermar [Tue, 4 Oct 2016 12:28:08 +0000 (13:28 +0100)] 
hw/arm: Fix Integrator/CM initialization

Initialization of a class instance cannot depend on its own properties
as these are not yet set.  Move parts of integratorcm_init() that depend
on the "memsz" property to the newly added integratorcm_realize().

This fixes: https://bugs.launchpad.net/qemu/+bug/1624726

Signed-off-by: Jakub Jermar <jakub@jermar.eu>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agomainstone: Add mapping for dot, slash and backspace.
Vijay Kumar B [Tue, 4 Oct 2016 12:28:08 +0000 (13:28 +0100)] 
mainstone: Add mapping for dot, slash and backspace.

Add missed out mappings. These mappings are from the "Intel PXA27x
Processor Developer's Kit User Guide".

Signed-off-by: Vijay Kumar B. <vijaykumar@zilogic.com>
Reviewed-by: Deepak S. <deepak@zilogic.com>
Message-id: 1475063033-8176-3-git-send-email-vijaykumar@zilogic.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agomainstone: Fix incorrect key mapping for Enter key.
Vijay Kumar B [Tue, 4 Oct 2016 12:28:07 +0000 (13:28 +0100)] 
mainstone: Fix incorrect key mapping for Enter key.

According to the manual the (5, 5) corresponds to backspace key, and
not Enter key. Linux kernel maps (5, 4) to the enter key. Fixing it up
to match the mapping in the Linux kernel.

Signed-off-by: Vijay Kumar B. <vijaykumar@zilogic.com>
Reviewed-by: Deepak S. <deepak@zilogic.com>
Message-id: 1475063033-8176-2-git-send-email-vijaykumar@zilogic.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoMAINTAINERS: Add Alistair to the maintainers list
Alistair Francis [Tue, 4 Oct 2016 12:28:07 +0000 (13:28 +0100)] 
MAINTAINERS: Add Alistair to the maintainers list

Add Alistair Francis as the maintainer for the Netduino 2
and SMM32F205 SoC.

Signed-off-by: Alistair Francis <alistair@alistair23.me>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: 5a46ccf398b050a41cc3b3d0e94bcff4ce2d85e0.1474742262.git.alistair@alistair23.me
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoSTM32F205: Connect the SPI devices
Alistair Francis [Tue, 4 Oct 2016 12:28:07 +0000 (13:28 +0100)] 
STM32F205: Connect the SPI devices

Connect the SPI devices to the STM32F205 SoC.

Signed-off-by: Alistair Francis <alistair@alistair23.me>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: d05849120420f8db0d9aa053bd23134c33cd9180.1474742262.git.alistair@alistair23.me
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoSTM32F205: Connect the ADC devices
Alistair Francis [Tue, 4 Oct 2016 12:28:07 +0000 (13:28 +0100)] 
STM32F205: Connect the ADC devices

Connect the ADC devices to the STM32F205 SoC.

Signed-off-by: Alistair Francis <alistair@alistair23.me>
Message-id: 6214eda399da7b47014f6f895be25323d52dbc9e.1474742262.git.alistair@alistair23.me
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoirq: Add a new irq device that allows the ORing of lines
Alistair Francis [Tue, 4 Oct 2016 12:28:07 +0000 (13:28 +0100)] 
irq: Add a new irq device that allows the ORing of lines

Signed-off-by: Alistair Francis <alistair@alistair23.me>
Message-id: 52e5d361e3b5a0ea8554aca73ee65ae2b586112e.1474742262.git.alistair@alistair23.me
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoSTM32F2xx: Add the SPI device
Alistair Francis [Tue, 4 Oct 2016 12:28:07 +0000 (13:28 +0100)] 
STM32F2xx: Add the SPI device

Add the STM32F2xx SPI device.

Signed-off-by: Alistair Francis <alistair@alistair23.me>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 8197811d5c94f814fa67c6a33ca2f7fd0aa97432.1474742262.git.alistair@alistair23.me
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoSTM32F2xx: Add the ADC device
Alistair Francis [Tue, 4 Oct 2016 12:28:07 +0000 (13:28 +0100)] 
STM32F2xx: Add the ADC device

Add the STM32F2xx ADC device. This device randomly
generates values on each read.

This also includes creating a hw/adc directory.

Signed-off-by: Alistair Francis <alistair@alistair23.me>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 3240e660adaf537f55a63ce06096e844aece8cda.1474742262.git.alistair@alistair23.me
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoSTM32F2xx: Display PWM duty cycle from timer
Alistair Francis [Tue, 4 Oct 2016 12:28:07 +0000 (13:28 +0100)] 
STM32F2xx: Display PWM duty cycle from timer

If correctly configured allow the STM32F2xx timer to print
out the PWM duty cycle information.

Signed-off-by: Alistair Francis <alistair@alistair23.me>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: cdb59039a25e061615713a94b40797baa12ea9f9.1474742262.git.alistair@alistair23.me
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoSTM32F205: Remove the individual device variables
Alistair Francis [Tue, 4 Oct 2016 12:28:06 +0000 (13:28 +0100)] 
STM32F205: Remove the individual device variables

Cleanup the individual DeviceState and SysBusDevice
variables to re-use the same variable for each
device.

Signed-off-by: Alistair Francis <alistair@alistair23.me>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: fc5d75a57d320b69704df2c1146ff0fd482e4a88.1474742262.git.alistair@alistair23.me
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoMerge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into staging
Peter Maydell [Tue, 4 Oct 2016 10:28:30 +0000 (11:28 +0100)] 
Merge remote-tracking branch 'remotes/ehabkost/tags/x86-pull-request' into staging

x86 bug fixes

Fix for a XSAVE regression when using "-cpu host", and a fix on
the Opteron_G3 CPU model.

# gpg: Signature made Mon 03 Oct 2016 20:08:13 BST
# gpg:                using RSA key 0x2807936F984DC5A6
# gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>"
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF  D1AA 2807 936F 984D C5A6

* remotes/ehabkost/tags/x86-pull-request:
  target-i386: Correct family/model/stepping for Opteron_G3
  target-i386: Report known CPUID[EAX=0xD,ECX=0]:EAX bits as migratable

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoMerge remote-tracking branch 'remotes/famz/tags/for-upstream' into staging
Peter Maydell [Tue, 4 Oct 2016 10:01:39 +0000 (11:01 +0100)] 
Merge remote-tracking branch 'remotes/famz/tags/for-upstream' into staging

# gpg: Signature made Sun 02 Oct 2016 02:49:58 BST
# gpg:                using RSA key 0xCA35624C6A9171C6
# gpg: Good signature from "Fam Zheng <famz@redhat.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 5003 7CB7 9706 0F76 F021  AD56 CA35 624C 6A91 71C6

* remotes/famz/tags/for-upstream:
  docker: Build in a clean directory
  smbios: fix uuid copy
  xenpv: Fix qemu_uuid compiling error

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agotarget-i386: Correct family/model/stepping for Opteron_G3
Evgeny Yakovlev [Mon, 3 Oct 2016 11:50:02 +0000 (14:50 +0300)] 
target-i386: Correct family/model/stepping for Opteron_G3

Current CPU definition for AMD Opteron third generation includes
features like SSE4a and LAHF_LM support in emulated CPUID. These
features are present in K8 rev.E or K10 CPUs and later. However,
current G3 family and model describe 2nd generation K8 cores instead.

This is incorrect but was considered harmless until our tests found a
problem with linux kernels >= 3.10 (and maybe earlier) which specifically
check for Opteron K8 model when parsing CPUID leaf 0x80000001:
http://lxr.free-electrons.com/source/arch/x86/kernel/cpu/amd.c?v=3.16#L552
This code will disable LAHF_LM feature in /proc/cpuinfo if model number
is inconsistent.

This change sets Opteron_G3 family/model/stepping to 16/2/3 which is
a proper Opteron 3rd generation 2350 CPU.

Signed-off-by: Evgeny Yakovlev <eyakovlev@virtuozzo.com>
Signed-off-by: Denis V. Lunev <den@openvz.org>
CC: Paolo Bonzini <pbonzini@redhat.com>
CC: Richard Henderson <rth@twiddle.net>
CC: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2 years agotarget-i386: Report known CPUID[EAX=0xD,ECX=0]:EAX bits as migratable
Eduardo Habkost [Wed, 28 Sep 2016 15:00:29 +0000 (12:00 -0300)] 
target-i386: Report known CPUID[EAX=0xD,ECX=0]:EAX bits as migratable

A regression was introduced by commit 96193c22a "target-i386:
Move xsave component mask to features array": all
CPUID[EAX=0xD,ECX=0]:EAX bits were being reported as unmigratable
because they don't have feature names defined. This broke
"-cpu host" because it enables only migratable features by
default.

This adds a new field to FeatureWordInfo: migratable_flags, which
will make those features be reported as migratable even if they
don't have a property name defined.

Reported-by: Wanpeng Li <wanpeng.li@hotmail.com>
Cc: Paolo Bonzini <bonzini@gnu.org>
Reviewed-by: Wanpeng Li <wanpeng.li@hotmail.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2 years agodocker: Build in a clean directory
Fam Zheng [Wed, 28 Sep 2016 07:31:32 +0000 (15:31 +0800)] 
docker: Build in a clean directory

Currently we configure and build under "$QEMU_SRC/tests/docker" which is
dubious. Create a fixed directory (to be friendly to ccache) and change
to there before calling build_qemu.

Signed-off-by: Fam Zheng <famz@redhat.com>
Message-Id: <1475047892-11955-1-git-send-email-famz@redhat.com>

2 years agoMerge remote-tracking branch 'remotes/borntraeger/tags/s390x-20160927' into staging
Peter Maydell [Fri, 30 Sep 2016 22:45:56 +0000 (23:45 +0100)] 
Merge remote-tracking branch 'remotes/borntraeger/tags/s390x-20160927' into staging

Couple of s390x patches:
- some PCI cleanups
- fix build error due to uuid rework
- fix potential deadlock in sigp handling
- enable ccw devices in BIOS and enforce checking in QEMU

# gpg: Signature made Wed 28 Sep 2016 12:27:03 BST
# gpg:                using RSA key 0x117BBC80B5A61C7C
# gpg: Good signature from "Christian Borntraeger (IBM) <borntraeger@de.ibm.com>"
# Primary key fingerprint: F922 9381 A334 08F9 DBAB  FBCA 117B BC80 B5A6 1C7C

* remotes/borntraeger/tags/s390x-20160927:
  s390x/kvm: fix build against qemu_uuid
  s390x/css: {c,h,t,r,x}sch: require enable AND device number valid
  pc-bios/s390-ccw.img: rebuild image
  pc-bios/s390-ccw: enable subchannel for IPL I/O devices
  s390x/kvm: Fix potential deadlock in sigp handling
  s390x/pci: code cleanup
  s390x/pci: assign msix io region for each pci device
  s390x/pci: re-arrange variable declarations

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoMerge remote-tracking branch 'remotes/yongbok/tags/mips-20160929' into staging
Peter Maydell [Fri, 30 Sep 2016 22:14:39 +0000 (23:14 +0100)] 
Merge remote-tracking branch 'remotes/yongbok/tags/mips-20160929' into staging

MIPS patches 2016-09-29

Changes:
* MIPS Maintainer update
* vmstateify rc4030

# gpg: Signature made Thu 29 Sep 2016 13:09:09 BST
# gpg:                using RSA key 0x2238EB86D5F797C2
# gpg: Good signature from "Yongbok Kim <yongbok.kim@imgtec.com>"
# gpg: WARNING: This key is not certified with sufficiently trusted signatures!
# gpg:          It is not certain that the signature belongs to the owner.
# Primary key fingerprint: 8600 4CF5 3415 A5D9 4CFA  2B5C 2238 EB86 D5F7 97C2

* remotes/yongbok/tags/mips-20160929:
  hw/dma: vmstateify rc4030
  MAINTAINERS: update target-mips maintainers

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoMerge remote-tracking branch 'remotes/jnsnow/tags/ide-pull-request' into staging
Peter Maydell [Thu, 29 Sep 2016 23:42:08 +0000 (00:42 +0100)] 
Merge remote-tracking branch 'remotes/jnsnow/tags/ide-pull-request' into staging

# gpg: Signature made Thu 29 Sep 2016 21:13:46 BST
# gpg:                using RSA key 0x7DEF8106AAFC390E
# gpg: Good signature from "John Snow (John Huston) <jsnow@redhat.com>"
# Primary key fingerprint: FAEB 9711 A12C F475 812F  18F2 88A9 064D 1835 61EB
#      Subkey fingerprint: F9B7 ABDB BCAC DF95 BE76  CBD0 7DEF 8106 AAFC 390E

* remotes/jnsnow/tags/ide-pull-request:
  ide: Fix memory leak in ide_register_restart_cb()
  MAINTAINERS: Add some more headers to the IDE section
  ahci: clear aiocb in ncq_cb
  ide: fix DMA register transitions

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoide: Fix memory leak in ide_register_restart_cb()
Ashijeet Acharya [Tue, 27 Sep 2016 16:53:32 +0000 (22:23 +0530)] 
ide: Fix memory leak in ide_register_restart_cb()

Fix a memory leak in ide_register_restart_cb() in hw/ide/core.c and add
idebus_unrealize() in hw/ide/qdev.c to have calls to
qemu_del_vm_change_state_handler() to deal with the dangling change
state handler during hot-unplugging ide devices which might lead to a
crash.

Signed-off-by: Ashijeet Acharya <ashijeetacharya@gmail.com>
Reviewed-by: John Snow <jsnow@redhat.com>
Message-id: 1474995212-10580-1-git-send-email-ashijeetacharya@gmail.com
[Minor whitespace fix --js]
Signed-off-by: John Snow <jsnow@redhat.com>
2 years agoMAINTAINERS: Add some more headers to the IDE section
Thomas Huth [Fri, 23 Sep 2016 16:09:56 +0000 (18:09 +0200)] 
MAINTAINERS: Add some more headers to the IDE section

The folder include/hw/ide/ belongs to the IDE section.

Signed-off-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: John Snow <jsnow@redhat.com>
Message-id: 1474646996-30421-1-git-send-email-thuth@redhat.com
Signed-off-by: John Snow <jsnow@redhat.com>
2 years agoahci: clear aiocb in ncq_cb
John Snow [Mon, 26 Sep 2016 18:33:37 +0000 (14:33 -0400)] 
ahci: clear aiocb in ncq_cb

Similar to existing fixes for IDE (87ac25fd) and ATAPI (7f951b2d), the
AIOCB must be cleared in the callback. Otherwise, we may accidentally
try to reset a dangling pointer in bdrv_aio_cancel() from a port reset.

Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-id: 1474575040-32079-2-git-send-email-jsnow@redhat.com
Signed-off-by: John Snow <jsnow@redhat.com>
2 years agoide: fix DMA register transitions
John Snow [Thu, 29 Sep 2016 18:46:15 +0000 (14:46 -0400)] 
ide: fix DMA register transitions

ATA8-APT defines the state transitions for both a host controller and
for the hardware device during the lifecycle of a DMA transfer, in
section 9.7 "DMA command protocol."

One of the interesting tidbits here is that when a device transitions
from DDMA0 ("Prepare state") to DDMA1 ("Data_Transfer State"), it can
choose to set either BSY or DRQ to signal this transition, but not both.

as ide_sector_dma_start is the last point in our preparation process
before we begin the real data transfer process (for either AHCI or BMDMA),
this is the correct transition point for DDMA0 to DDMA1.

I have chosen !BSY && DRQ for QEMU to make the transition from DDMA0 the
most obvious.

Reported-by: Benjamin David Lunt <fys@fysnet.net>
Signed-off-by: John Snow <jsnow@redhat.com>
Reviewed-by: Kevin Wolf <kwolf@redhat.com>
Tested-by: Stefan Weil <sw@weilnetz.de>
Message-id: 1470175541-19344-1-git-send-email-jsnow@redhat.com
Signed-off-by: John Snow <jsnow@redhat.com>
2 years agooslib-posix: add a configure switch to debug stack usage
Peter Lieven [Tue, 27 Sep 2016 09:58:45 +0000 (11:58 +0200)] 
oslib-posix: add a configure switch to debug stack usage

this adds a knob to track the maximum stack usage of stacks
created by qemu_alloc_stack.

Signed-off-by: Peter Lieven <pl@kamp.de>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2 years agocoroutine-sigaltstack: use helper for allocating stack memory
Peter Lieven [Tue, 27 Sep 2016 09:58:44 +0000 (11:58 +0200)] 
coroutine-sigaltstack: use helper for allocating stack memory

Signed-off-by: Peter Lieven <pl@kamp.de>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2 years agocoroutine-ucontext: use helper for allocating stack memory
Peter Lieven [Tue, 27 Sep 2016 09:58:43 +0000 (11:58 +0200)] 
coroutine-ucontext: use helper for allocating stack memory

Signed-off-by: Peter Lieven <pl@kamp.de>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2 years agocoroutine: add a macro for the coroutine stack size
Peter Lieven [Tue, 27 Sep 2016 09:58:42 +0000 (11:58 +0200)] 
coroutine: add a macro for the coroutine stack size

Signed-off-by: Peter Lieven <pl@kamp.de>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2 years agocoroutine-sigaltstack: rename coroutine struct appropriately
Peter Lieven [Tue, 27 Sep 2016 09:58:41 +0000 (11:58 +0200)] 
coroutine-sigaltstack: rename coroutine struct appropriately

The name of the sigaltstack coroutine struct was misleading.

Signed-off-by: Peter Lieven <pl@kamp.de>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2 years agooslib-posix: add helpers for stack alloc and free
Peter Lieven [Tue, 27 Sep 2016 09:58:40 +0000 (11:58 +0200)] 
oslib-posix: add helpers for stack alloc and free

the allocated stack will be adjusted to the minimum supported stack size
by the OS and rounded up to be a multiple of the system pagesize.
Additionally an architecture dependent guard page is added to the stack
to catch stack overflows.

Signed-off-by: Peter Lieven <pl@kamp.de>
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
2 years agoblock: Remove qemu_root_bds_opts
Kevin Wolf [Tue, 20 Sep 2016 18:48:52 +0000 (20:48 +0200)] 
block: Remove qemu_root_bds_opts

The remaining options in qemu_root_bds_opts (aio and copy-on-read)
aren't used any more, the QAPI schema doesn't contain them. Therefore
all the code processing qemu_root_bds_opts options is dead and can be
removed.

Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
2 years agoblock: Move 'discard' option to bdrv_open_common()
Kevin Wolf [Mon, 12 Sep 2016 16:03:18 +0000 (18:03 +0200)] 
block: Move 'discard' option to bdrv_open_common()

This enables its use for nested child nodes. The compatibility
between the 'discard' and 'detect-zeroes' setting is checked in
bdrv_open_common() now as the former setting isn't available before
calling bdrv_open() any more.

Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Eric Blake <eblake@redhat.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>