qemu.git
2 years agoqcow2: skip writing zero buffers to empty COW areas
Anton Nefedov [Thu, 16 May 2019 14:27:49 +0000 (17:27 +0300)] 
qcow2: skip writing zero buffers to empty COW areas

If COW areas of the newly allocated clusters are zeroes on the backing
image, efficient bdrv_write_zeroes(flags=BDRV_REQ_NO_FALLBACK) can be
used on the whole cluster instead of writing explicit zero buffers later
in perform_cow().

iotest 060:
write to the discarded cluster does not trigger COW anymore.
Use a backing image instead.

Signed-off-by: Anton Nefedov <anton.nefedov@virtuozzo.com>
Message-id: 20190516142749.81019-2-anton.nefedov@virtuozzo.com
Reviewed-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Reviewed-by: Alberto Garcia <berto@igalia.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
2 years agoqemu-img: rebase: Reuse in-chain BlockDriverState
Sam Eiderman [Thu, 23 May 2019 16:33:37 +0000 (19:33 +0300)] 
qemu-img: rebase: Reuse in-chain BlockDriverState

If a chain was detected, don't open a new BlockBackend from the target
backing file which will create a new BlockDriverState. Instead, create
an empty BlockBackend and attach the already open BlockDriverState.

Permissions for blk_new() were copied from blk_new_open() when
flags = 0.

Reviewed-by: Karl Heubaum <karl.heubaum@oracle.com>
Reviewed-by: Eyal Moscovici <eyal.moscovici@oracle.com>
Signed-off-by: Sagi Amit <sagi.amit@oracle.com>
Co-developed-by: Sagi Amit <sagi.amit@oracle.com>
Signed-off-by: Sam Eiderman <shmuel.eiderman@oracle.com>
Message-id: 20190523163337.4497-4-shmuel.eiderman@oracle.com
Signed-off-by: Max Reitz <mreitz@redhat.com>
2 years agoqemu-img: rebase: Reduce reads on in-chain rebase
Sam Eiderman [Thu, 23 May 2019 16:33:36 +0000 (19:33 +0300)] 
qemu-img: rebase: Reduce reads on in-chain rebase

In the following case:

(base) A <- B <- C (tip)

when running:

    qemu-img rebase -b A C

QEMU would read all sectors not allocated in the file being rebased (C)
and compare them to the new base image (A), regardless of whether they
were changed or even allocated anywhere along the chain between the new
base and the top image (B). This causes many unneeded reads when
rebasing an image which represents a small diff of a large disk, as it
would read most of the disk's sectors.

Instead, use bdrv_is_allocated_above() to reduce the number of
unnecessary reads.

Reviewed-by: Karl Heubaum <karl.heubaum@oracle.com>
Signed-off-by: Sam Eiderman <shmuel.eiderman@oracle.com>
Signed-off-by: Eyal Moscovici <eyal.moscovici@oracle.com>
Message-id: 20190523163337.4497-3-shmuel.eiderman@oracle.com
Signed-off-by: Max Reitz <mreitz@redhat.com>
2 years agoqemu-img: rebase: Reuse parent BlockDriverState
Sam Eiderman [Thu, 23 May 2019 16:33:35 +0000 (19:33 +0300)] 
qemu-img: rebase: Reuse parent BlockDriverState

In safe mode we open the entire chain, including the parent backing
file of the rebased file.
Do not open a new BlockBackend for the parent backing file, which
saves opening the rest of the chain twice, which for long chains
saves many "pricy" bdrv_open() calls.

Permissions for blk_new() were copied from blk_new_open() when
flags = 0.

Reviewed-by: Karl Heubaum <karl.heubaum@oracle.com>
Reviewed-by: Eyal Moscovici <eyal.moscovici@oracle.com>
Signed-off-by: Sagi Amit <sagi.amit@oracle.com>
Co-developed-by: Sagi Amit <sagi.amit@oracle.com>
Signed-off-by: Sam Eiderman <shmuel.eiderman@oracle.com>
Message-id: 20190523163337.4497-2-shmuel.eiderman@oracle.com
Signed-off-by: Max Reitz <mreitz@redhat.com>
2 years agoblock: Make bdrv_root_attach_child() unref child_bs on failure
Alberto Garcia [Mon, 13 May 2019 13:46:18 +0000 (16:46 +0300)] 
block: Make bdrv_root_attach_child() unref child_bs on failure

A consequence of the previous patch is that bdrv_attach_child()
transfers the reference to child_bs from the caller to parent_bs,
which will drop it on bdrv_close() or when someone calls
bdrv_unref_child().

But this only happens when bdrv_attach_child() succeeds. If it fails
then the caller is responsible for dropping the reference to child_bs.

This patch makes bdrv_attach_child() take the reference also when
there is an error, freeing the caller for having to do it.

A similar situation happens with bdrv_root_attach_child(), so the
changes on this patch affect both functions.

Signed-off-by: Alberto Garcia <berto@igalia.com>
Message-id: 20dfb3d9ccec559cdd1a9690146abad5d204a186.1557754872.git.berto@igalia.com
[mreitz: Removed now superfluous BdrvChild * variable in
         bdrv_open_child()]
Signed-off-by: Max Reitz <mreitz@redhat.com>
2 years agoblock: Use bdrv_unref_child() for all children in bdrv_close()
Alberto Garcia [Mon, 13 May 2019 13:46:17 +0000 (16:46 +0300)] 
block: Use bdrv_unref_child() for all children in bdrv_close()

bdrv_unref_child() does the following things:

  - Updates the child->bs->inherits_from pointer.
  - Calls bdrv_detach_child() to remove the BdrvChild from bs->children.
  - Calls bdrv_unref() to unref the child BlockDriverState.

When bdrv_unref_child() was introduced in commit 33a604075c it was not
used in bdrv_close() because the drivers that had additional children
(like quorum or blkverify) had already called bdrv_unref() on their
children during their own close functions.

This was changed later (in 0bd6e91a7e for quorum, in 3e586be0b2 for
blkverify) so there's no reason not to use bdrv_unref_child() in
bdrv_close() anymore.

After this there's also no need to remove bs->backing and bs->file
separately from the rest of the children, so bdrv_close() can be
simplified.

Now bdrv_close() unrefs all children (before this patch it was only
bs->file and bs->backing). As a result, none of the callers of
brvd_attach_child() should remove their reference to child_bs (because
this function effectively steals that reference). This patch updates a
couple of tests that were doing their own bdrv_unref().

Signed-off-by: Alberto Garcia <berto@igalia.com>
Message-id: 6d1d5feaa53aa1ab127adb73d605dc4503e3abd5.1557754872.git.berto@igalia.com
[mreitz: s/where/were/]
Signed-off-by: Max Reitz <mreitz@redhat.com>
2 years agoblock/backup: refactor: split out backup_calculate_cluster_size
Vladimir Sementsov-Ogievskiy [Mon, 29 Apr 2019 09:08:42 +0000 (12:08 +0300)] 
block/backup: refactor: split out backup_calculate_cluster_size

Split out cluster_size calculation. Move copy-bitmap creation above
block-job creation, as we are going to share it with upcoming
backup-top filter, which also should be created before actual block job
creation.

Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-id: 20190429090842.57910-6-vsementsov@virtuozzo.com
[mreitz: Dropped a paragraph from the commit message that was left over
         from a previous version]
Signed-off-by: Max Reitz <mreitz@redhat.com>
2 years agoblock/backup: unify different modes code path
Vladimir Sementsov-Ogievskiy [Mon, 29 Apr 2019 09:08:41 +0000 (12:08 +0300)] 
block/backup: unify different modes code path

Do full, top and incremental mode copying all in one place. This
unifies the code path and helps further improvements.

Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Message-id: 20190429090842.57910-5-vsementsov@virtuozzo.com
Signed-off-by: Max Reitz <mreitz@redhat.com>
2 years agoblock/backup: refactor and tolerate unallocated cluster skipping
Vladimir Sementsov-Ogievskiy [Mon, 29 Apr 2019 09:08:40 +0000 (12:08 +0300)] 
block/backup: refactor and tolerate unallocated cluster skipping

Split allocation checking to separate function and reduce nesting.
Consider bdrv_is_allocated() fail as allocated area, as copying more
than needed is not wrong (and we do it anyway) and seems better than
fail the whole job. And, most probably we will fail on the next read,
if there are real problem with source.

Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Message-id: 20190429090842.57910-4-vsementsov@virtuozzo.com
Signed-off-by: Max Reitz <mreitz@redhat.com>
2 years agoblock/backup: move to copy_bitmap with granularity
Vladimir Sementsov-Ogievskiy [Mon, 29 Apr 2019 09:08:39 +0000 (12:08 +0300)] 
block/backup: move to copy_bitmap with granularity

We are going to share this bitmap between backup and backup-top filter
driver, so let's share something more meaningful. It also simplifies
some calculations.

Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Message-id: 20190429090842.57910-3-vsementsov@virtuozzo.com
Signed-off-by: Max Reitz <mreitz@redhat.com>
2 years agoblock/backup: simplify backup_incremental_init_copy_bitmap
Vladimir Sementsov-Ogievskiy [Mon, 29 Apr 2019 09:08:38 +0000 (12:08 +0300)] 
block/backup: simplify backup_incremental_init_copy_bitmap

Simplify backup_incremental_init_copy_bitmap using the function
bdrv_dirty_bitmap_next_dirty_area.

Note: move to job->len instead of bitmap size: it should not matter but
less code.

Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Message-id: 20190429090842.57910-2-vsementsov@virtuozzo.com
Signed-off-by: Max Reitz <mreitz@redhat.com>
2 years agoqcow2: do encryption in threads
Vladimir Sementsov-Ogievskiy [Mon, 6 May 2019 14:27:41 +0000 (17:27 +0300)] 
qcow2: do encryption in threads

Do encryption/decryption in threads, like it is already done for
compression. This improves asynchronous encrypted io.

Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Reviewed-by: Alberto Garcia <berto@igalia.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Message-id: 20190506142741.41731-9-vsementsov@virtuozzo.com
Signed-off-by: Max Reitz <mreitz@redhat.com>
2 years agoqcow2: bdrv_co_pwritev: move encryption code out of the lock
Vladimir Sementsov-Ogievskiy [Mon, 6 May 2019 14:27:40 +0000 (17:27 +0300)] 
qcow2: bdrv_co_pwritev: move encryption code out of the lock

Encryption will be done in threads, to take benefit of it, we should
move it out of the lock first.

Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Reviewed-by: Alberto Garcia <berto@igalia.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Message-id: 20190506142741.41731-8-vsementsov@virtuozzo.com
Signed-off-by: Max Reitz <mreitz@redhat.com>
2 years agoqcow2: qcow2_co_preadv: improve locking
Vladimir Sementsov-Ogievskiy [Mon, 6 May 2019 14:27:39 +0000 (17:27 +0300)] 
qcow2: qcow2_co_preadv: improve locking

Background: decryption will be done in threads, to take benefit of it,
we should move it out of the lock first.

But let's go further: it turns out, that only
qcow2_get_cluster_offset() needs locking, so reduce locking to it.

Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Message-id: 20190506142741.41731-7-vsementsov@virtuozzo.com
Reviewed-by: Alberto Garcia <berto@igalia.com>
Signed-off-by: Max Reitz <mreitz@redhat.com>
2 years agoqcow2-threads: split out generic path
Vladimir Sementsov-Ogievskiy [Mon, 6 May 2019 14:27:38 +0000 (17:27 +0300)] 
qcow2-threads: split out generic path

Move generic part out of qcow2_co_do_compress, to reuse it for
encryption and rename things that would be shared with encryption path.

Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Reviewed-by: Alberto Garcia <berto@igalia.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Message-id: 20190506142741.41731-6-vsementsov@virtuozzo.com
Signed-off-by: Max Reitz <mreitz@redhat.com>
2 years agoqcow2-threads: qcow2_co_do_compress: protect queuing by mutex
Vladimir Sementsov-Ogievskiy [Mon, 6 May 2019 14:27:37 +0000 (17:27 +0300)] 
qcow2-threads: qcow2_co_do_compress: protect queuing by mutex

Drop dependence on AioContext lock.

Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Reviewed-by: Alberto Garcia <berto@igalia.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Message-id: 20190506142741.41731-5-vsementsov@virtuozzo.com
Signed-off-by: Max Reitz <mreitz@redhat.com>
2 years agoqcow2-threads: use thread_pool_submit_co
Vladimir Sementsov-Ogievskiy [Mon, 6 May 2019 14:27:36 +0000 (17:27 +0300)] 
qcow2-threads: use thread_pool_submit_co

Use thread_pool_submit_co, instead of reinventing it here. Note, that
thread_pool_submit_aio() never returns NULL, so checking it was an
extra thing.

Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Reviewed-by: Alberto Garcia <berto@igalia.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Message-id: 20190506142741.41731-4-vsementsov@virtuozzo.com
Signed-off-by: Max Reitz <mreitz@redhat.com>
2 years agoqcow2: add separate file for threaded data processing functions
Vladimir Sementsov-Ogievskiy [Mon, 6 May 2019 14:27:35 +0000 (17:27 +0300)] 
qcow2: add separate file for threaded data processing functions

Move compression-on-threads to separate file. Encryption will be in it
too.

Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Reviewed-by: Alberto Garcia <berto@igalia.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Message-id: 20190506142741.41731-3-vsementsov@virtuozzo.com
Signed-off-by: Max Reitz <mreitz@redhat.com>
2 years agoqcow2.h: add missing include
Vladimir Sementsov-Ogievskiy [Mon, 6 May 2019 14:27:34 +0000 (17:27 +0300)] 
qcow2.h: add missing include

qcow2.h depends on block_int.h. Compilation isn't broken currently only
due to block_int.h always included before qcow2.h. Though, it seems
better to directly include block_int.h in qcow2.h.

Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@virtuozzo.com>
Reviewed-by: Alberto Garcia <berto@igalia.com>
Reviewed-by: Max Reitz <mreitz@redhat.com>
Message-id: 20190506142741.41731-2-vsementsov@virtuozzo.com
Signed-off-by: Max Reitz <mreitz@redhat.com>
2 years agoMerge remote-tracking branch 'remotes/stsquad/tags/pull-testing-next-280519-2' into...
Peter Maydell [Tue, 28 May 2019 16:38:32 +0000 (17:38 +0100)] 
Merge remote-tracking branch 'remotes/stsquad/tags/pull-testing-next-280519-2' into staging

Various testing updates

  - semihosting re-factor (used in system tests)
  - aarch64 and alpha system tests
  - editorconfig tweak for .S
  - some docker image updates
  - iotests clean-up (without make check inclusion)

# gpg: Signature made Tue 28 May 2019 17:26:34 BST
# gpg:                using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44
# gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [full]
# Primary key fingerprint: 6685 AE99 E751 67BC AFC8  DF35 FBD0 DB09 5A9E 2A44

* remotes/stsquad/tags/pull-testing-next-280519-2: (27 commits)
  tests/qemu-iotests: re-format output to for make check-block
  tests/qemu-iotests/group: Re-use the "auto" group for tests that can always run
  Makefile.target: support per-target coverage reports
  Makefile: include per-target build directories in coverage report
  Makefile: fix coverage-report reference to BUILD_DIR
  .travis.yml: enable aarch64-softmmu and alpha-softmmu tcg tests
  tests/tcg/alpha: add system boot.S
  tests/tcg/multiarch: expand system memory test to cover more
  tests/tcg/minilib: support %c format char
  tests/tcg/multiarch: move the system memory test
  tests/tcg/aarch64: add system boot.S
  editorconfig: add settings for .s/.S files
  tests/tcg/multiarch: add hello world system test
  tests/tcg/multiarch: add support for multiarch system tests
  tests/docker: Test more components on the Fedora default image
  tests/docker: add ubuntu 18.04
  MAINTAINERS: update for semihostings new home
  target/mips: convert UHI_plog to use common semihosting code
  target/mips: only build mips-semi for softmmu
  target/arm: correct return values for WRITE/READ in arm-semi
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoMerge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-may-19-2019-v3' into...
Peter Maydell [Tue, 28 May 2019 11:25:20 +0000 (12:25 +0100)] 
Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-may-19-2019-v3' into staging

MIPS queue for May 19th, 2019 - v3

# gpg: Signature made Sun 26 May 2019 17:07:07 BST
# gpg:                using RSA key D4972A8967F75A65
# gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01  DD75 D497 2A89 67F7 5A65

* remotes/amarkovic/tags/mips-queue-may-19-2019-v3:
  BootLinuxSshTest: Test some userspace commands on Malta
  target/mips: realign comments to fix checkpatch warnings
  target/mips: add or remove space to fix checkpatch errors
  linux-user: fix __NR_semtimedop undeclared error
  mips: Decide to map PAGE_EXEC in map_address
  target/mips: Refactor and fix INSERT.<B|H|W|D> instructions
  target/mips: Refactor and fix COPY_U.<B|H|W> instructions
  target/mips: Refactor and fix COPY_S.<B|H|W|D> instructions
  target/mips: Fix MSA instructions ST.<B|H|W|D> on big endian host
  target/mips: Fix MSA instructions LD.<B|H|W|D> on big endian host
  target/mips: Make the results of MOD_<U|S>.<B|H|W|D> the same as on hardware
  target/mips: Make the results of DIV_<U|S>.<B|H|W|D> the same as on hardware

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoMerge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.1-sf0' into...
Peter Maydell [Tue, 28 May 2019 10:52:53 +0000 (11:52 +0100)] 
Merge remote-tracking branch 'remotes/palmer/tags/riscv-for-master-4.1-sf0' into staging

RISC-V Patches for the 4.1 Soft Freeze, Part 1

This tag contains a handful of patches that I'd like to target for 4.1:

* An emulation for SiFive's GPIO device.
* A fix to disallow sfence.vma from userspace.
* Additional decodetree cleanups that should have no functional impact.
* C extension emulation fidelity fixes that were noticed as part of that
  cleanup process.
* A new "spike" target, along with the deprecation of a handful of old
  targets and CPUs.
* Some initial infastructure related to the hypervisor extension.
* An emulation fidelity fix that prevents prevents arbitrary bits in the
  SIP CSR from being set.
* A small performance improvement that avoids excessive TLB flushing
  when the ASID does not change.

This time I've used a new testing workflow: I've tested on both 32-bit
and 64-bit builds of OpenEmbedded, via the default OpenSBI-based boot
flow.

# gpg: Signature made Sat 25 May 2019 01:05:57 BST
# gpg:                using RSA key 00CE76D1834960DFCE886DF8EF4CA1502CCBAB41
# gpg:                issuer "palmer@dabbelt.com"
# gpg: Good signature from "Palmer Dabbelt <palmer@dabbelt.com>" [unknown]
# gpg:                 aka "Palmer Dabbelt <palmer@sifive.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 00CE 76D1 8349 60DF CE88  6DF8 EF4C A150 2CCB AB41

* remotes/palmer/tags/riscv-for-master-4.1-sf0: (29 commits)
  target/riscv: Only flush TLB if SATP.ASID changes
  target/riscv: More accurate handling of `sip` CSR
  target/riscv: Add checks for several RVC reserved operands
  target/riscv: Add the HGATP register masks
  target/riscv: Add the HSTATUS register masks
  target/riscv: Add Hypervisor CSR macros
  target/riscv: Allow setting mstatus virtulisation bits
  target/riscv: Add the MPV and MTL mstatus bits
  target/riscv: Improve the scause logic
  target/riscv: Trigger interrupt on MIP update asynchronously
  target/riscv: Mark privilege level 2 as reserved
  riscv: spike: Add a generic spike machine
  target/riscv: Deprecate the generic no MMU CPUs
  target/riscv: Add a base 32 and 64 bit CPU
  target/riscv: Create settable CPU properties
  riscv: virt: Allow specifying a CPU via commandline
  linux-user/riscv: Add the CPU type as a comment
  target/riscv: Remove unused include of riscv_htif.h for virt board riscv
  target/riscv: Remove spaces from register names
  target/riscv: Split gen_arith_imm into functional and temp
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agoMerge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request' into...
Peter Maydell [Tue, 28 May 2019 09:50:09 +0000 (10:50 +0100)] 
Merge remote-tracking branch 'remotes/ehabkost/tags/machine-next-pull-request' into staging

Machine Core queue, 2019-05-24

* Display more helpful message when an object type is missing
  (Philippe Mathieu-Daudé)
* Use object_initialize_child for correct reference counting
  (Philippe Mathieu-Daudé)

# gpg: Signature made Fri 24 May 2019 19:31:06 BST
# gpg:                using RSA key 2807936F984DC5A6
# gpg: Good signature from "Eduardo Habkost <ehabkost@redhat.com>" [full]
# Primary key fingerprint: 5A32 2FD5 ABC4 D3DB ACCF  D1AA 2807 936F 984D C5A6

* remotes/ehabkost/tags/machine-next-pull-request:
  hw/intc/nvic: Use object_initialize_child for correct reference counting
  hw/arm/mps2: Use object_initialize_child for correct reference counting
  hw/microblaze/zynqmp: Use object_initialize_child for correct ref. counting
  hw/microblaze/zynqmp: Use object_initialize_child for correct ref. counting
  hw/microblaze/zynqmp: Let the SoC manage the IPI devices
  hw/microblaze/zynqmp: Move the IPI state into the PMUSoC state
  hw/mips: Use object_initialize_child for correct reference counting
  hw/mips: Use object_initialize() on MIPSCPSState
  hw/arm: Use object_initialize_child for correct reference counting
  hw/arm/aspeed: Use object_initialize_child for correct ref. counting
  hw/arm/bcm2835: Use object_initialize_child for correct ref. counting
  hw/arm/bcm2835: Use object_initialize() on PL011State
  hw/arm/bcm2835: Use TYPE_PL011 instead of hardcoded string
  hw/virtio: Use object_initialize_child for correct reference counting
  hw/misc/macio: Use object_initialize_child for correct ref. counting
  hw/ppc/pnv: Use object_initialize_child for correct reference counting
  qom/object: Display more helpful message when an object type is missing

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2 years agotests/qemu-iotests: re-format output to for make check-block
Alex Bennée [Fri, 3 May 2019 14:39:04 +0000 (15:39 +0100)] 
tests/qemu-iotests: re-format output to for make check-block

This attempts to clean-up the output to better match the output of the
rest of the QEMU check system when called with -makecheck. This includes:

  - formatting as "  TEST    iotest-FMT: nnn"
  - only dumping config on failure (when -makecheck enabled)

The non-make check output has been cleaned up as well:

  - line re-displayed (\r) at the end
  - fancy colours for pass/fail/skip
  - timestamps always printed (option removed)

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20190503143904.31211-1-alex.bennee@linaro.org>
Tested-by: Thomas Huth <thuth@redhat.com>
2 years agotests/qemu-iotests/group: Re-use the "auto" group for tests that can always run
Thomas Huth [Thu, 2 May 2019 08:45:05 +0000 (10:45 +0200)] 
tests/qemu-iotests/group: Re-use the "auto" group for tests that can always run

Currently, all tests are in the "auto" group. This is a little bit pointless.
OTOH, we need a group for the tests that we can automatically run during
"make check" each time, too. Tests in this new group are supposed to run
with every possible QEMU configuration, for example they must run with every
QEMU binary (also non-x86), without failing when an optional features is
missing (but reporting "skip" is ok), and be able to run on all kind of host
filesystems and users (i.e. also as "nobody" or "root").
So let's use the "auto" group for this class of tests now. The initial
list has been determined by running the iotests with non-x86 QEMU targets
and with our CI pipelines on Gitlab, Cirrus-CI and Travis (i.e. including
macOS and FreeBSD).

Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20190502084506.8009-7-thuth@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2 years agoMakefile.target: support per-target coverage reports
Alex Bennée [Tue, 30 Apr 2019 13:44:10 +0000 (14:44 +0100)] 
Makefile.target: support per-target coverage reports

Add support for generating a single targets coverage report. Execute:

  make coverage-report

In the target build directory. This coverage report only cares about
target specific blobs so only searches the target build subdirectory.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2 years agoMakefile: include per-target build directories in coverage report
Alex Bennée [Tue, 30 Apr 2019 15:59:48 +0000 (16:59 +0100)] 
Makefile: include per-target build directories in coverage report

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2 years agoMakefile: fix coverage-report reference to BUILD_DIR
Alex Bennée [Tue, 30 Apr 2019 13:42:35 +0000 (14:42 +0100)] 
Makefile: fix coverage-report reference to BUILD_DIR

Commit 337f2311f actually claimed to do this in the commit log but
didn't actually. Oops.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2 years ago.travis.yml: enable aarch64-softmmu and alpha-softmmu tcg tests
Alex Bennée [Thu, 9 May 2019 15:38:40 +0000 (16:38 +0100)] 
.travis.yml: enable aarch64-softmmu and alpha-softmmu tcg tests

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2 years agotests/tcg/alpha: add system boot.S
Richard Henderson [Wed, 1 May 2019 18:43:06 +0000 (11:43 -0700)] 
tests/tcg/alpha: add system boot.S

This provides the bootstrap and low level helper functions for an
alpha kernel.  We use direct access to the DP264 serial port for
test output, and hard machine halt to exit the emulation.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20190501184306.15208-1-richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2 years agotests/tcg/multiarch: expand system memory test to cover more
Alex Bennée [Mon, 29 Apr 2019 15:55:59 +0000 (16:55 +0100)] 
tests/tcg/multiarch: expand system memory test to cover more

Expand the memory test to cover move of the softmmu code. Specifically
we:

  - improve commentary
  - add some helpers (for later BE support)
  - reduce boiler plate into helpers
  - add signed reads at various sizes/offsets
  - required -DCHECK_UNALIGNED

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2 years agotests/tcg/minilib: support %c format char
Alex Bennée [Tue, 30 Apr 2019 12:04:51 +0000 (13:04 +0100)] 
tests/tcg/minilib: support %c format char

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2 years agotests/tcg/multiarch: move the system memory test
Alex Bennée [Fri, 26 Apr 2019 08:28:15 +0000 (09:28 +0100)] 
tests/tcg/multiarch: move the system memory test

There is nothing inherently architecture specific about the memory
test although we may have to manage different restrictions of
unaligned access across architectures.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2 years agotests/tcg/aarch64: add system boot.S
Alex Bennée [Fri, 26 Apr 2019 16:21:00 +0000 (17:21 +0100)] 
tests/tcg/aarch64: add system boot.S

This provides the bootstrap and low level helper functions for an
aarch64 kernel. We use semihosting to handle test output and exiting
the emulation. semihosting's parameter passing is a little funky so we
end up using the stack and pointing to that as the parameter block.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2 years agoeditorconfig: add settings for .s/.S files
Alex Bennée [Wed, 8 May 2019 13:42:51 +0000 (14:42 +0100)] 
editorconfig: add settings for .s/.S files

We are starting to add assembler foe tests/tcg so lets make sure we
get the mode right.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2 years agotests/tcg/multiarch: add hello world system test
Alex Bennée [Mon, 29 Apr 2019 14:41:46 +0000 (15:41 +0100)] 
tests/tcg/multiarch: add hello world system test

This is not really i386 only, we can have the same test for all
architectures supporting system tests.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2 years agotests/tcg/multiarch: add support for multiarch system tests
Alex Bennée [Mon, 29 Apr 2019 14:38:44 +0000 (15:38 +0100)] 
tests/tcg/multiarch: add support for multiarch system tests

We can certainly support some common tests for system emulation that
make use of our minimal defined boot.S support. It will still be up to
individual architectures to ensure they build so we provide a
MULTIARCH_TESTS variable that they can tack onto TESTS themselves.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2 years agotests/docker: Test more components on the Fedora default image
Philippe Mathieu-Daudé [Sat, 4 May 2019 05:54:40 +0000 (07:54 +0200)] 
tests/docker: Test more components on the Fedora default image

Install optional dependencies of QEMU to get better coverage.

The following components are now enabled:

  $ ./configure
  ...
  Multipath support yes
  VNC SASL support  yes
  RDMA support      yes
  PVRDMA support    yes
  libiscsi support  yes
  seccomp support   yes
  libpmem support   yes
  libudev           yes

Note: The udev-devel package is provided by systemd-devel.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20190504055440.20406-1-philmd@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Acked-by: Marcel Apfelbaum<marcel.apfelbaum@gmail.com>
2 years agotests/docker: add ubuntu 18.04
Gerd Hoffmann [Fri, 3 May 2019 07:02:41 +0000 (09:02 +0200)] 
tests/docker: add ubuntu 18.04

Based on the ubuntu.docker file.
Used to reproduce the build failure Peter was seeing.
Others might find this useful too ;)

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Message-Id: <20190503070241.24786-1-kraxel@redhat.com>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2 years agoMAINTAINERS: update for semihostings new home
Alex Bennée [Mon, 13 May 2019 14:32:56 +0000 (15:32 +0100)] 
MAINTAINERS: update for semihostings new home

Seeing as I touched it I should at least keep an eye on it.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2 years agotarget/mips: convert UHI_plog to use common semihosting code
Alex Bennée [Tue, 14 May 2019 12:52:30 +0000 (13:52 +0100)] 
target/mips: convert UHI_plog to use common semihosting code

Rather than printing directly to stdout lets use our common
semihosting code. There is one minor difference in that the output
currently defaults to stderr instead of stdout however this can be
controlled by connecting semihosting to a chardev.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
2 years agotarget/mips: only build mips-semi for softmmu
Alex Bennée [Tue, 14 May 2019 12:50:45 +0000 (13:50 +0100)] 
target/mips: only build mips-semi for softmmu

The is_uhi gates all semihosting calls and always returns false for
CONFIG_USER_ONLY builds. There is no reason to build and link
mips-semi for these builds so lets fix that.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2 years agotarget/arm: correct return values for WRITE/READ in arm-semi
Alex Bennée [Tue, 14 May 2019 11:21:45 +0000 (12:21 +0100)] 
target/arm: correct return values for WRITE/READ in arm-semi

The documentation says the write should return the number of bytes not
written on an error (0 means everything was written). Read provides a
buffer length and the return value should be the buffer length - bytes
actually read. Remove the incorrect FIXME's and return the correct
values.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2 years agotarget/arm: add LOG_UNIMP messages to arm-semi
Alex Bennée [Tue, 14 May 2019 11:15:38 +0000 (12:15 +0100)] 
target/arm: add LOG_UNIMP messages to arm-semi

Clean-up our unimplemented bits with a proper message.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2 years agotarget/arm: use the common interface for WRITE0/WRITEC in arm-semi
Alex Bennée [Tue, 14 May 2019 10:07:15 +0000 (11:07 +0100)] 
target/arm: use the common interface for WRITE0/WRITEC in arm-semi

Now we have a common semihosting console interface use that for our
string output. However ARM is currently unique in also supporting
semihosting for linux-user so we need to replicate the API in
linux-user. If other architectures gain this support we can move the
file later.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2 years agotarget/arm: fixup some of the commentary for arm-semi
Alex Bennée [Tue, 14 May 2019 11:08:39 +0000 (12:08 +0100)] 
target/arm: fixup some of the commentary for arm-semi

This cleans up a number of the block comments to fit the proper style.
While we are at it we also reference the official specification and
document what the return register value can be.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
2 years agosemihosting: enable chardev backed output for console
Alex Bennée [Tue, 14 May 2019 14:30:14 +0000 (15:30 +0100)] 
semihosting: enable chardev backed output for console

It will be useful for a number of use-cases to be able to re-direct
output to a file like we do with serial output. This does the wiring
to allow us to treat then semihosting console like just another
character output device.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2 years agosemihosting: implement a semihosting console
Alex Bennée [Mon, 13 May 2019 20:49:43 +0000 (21:49 +0100)] 
semihosting: implement a semihosting console

This provides two functions for handling console output that handle
the common backend behaviour for semihosting.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
2 years agosemihosting: introduce CONFIG_SEMIHOSTING
Alex Bennée [Mon, 13 May 2019 14:25:27 +0000 (15:25 +0100)] 
semihosting: introduce CONFIG_SEMIHOSTING

There isn't much point building semihosting for platforms that don't
support it. Introduce a new symbol and enable it only for the softmmu
targets that need it.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2 years agosemihosting: move semihosting configuration into its own directory
Alex Bennée [Mon, 13 May 2019 13:43:57 +0000 (14:43 +0100)] 
semihosting: move semihosting configuration into its own directory

In preparation for having some more common semihosting code let's
excise the current config magic from vl.c into its own file. We shall
later add more conditionals to the build configurations so we can
avoid building this if we don't need it.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
2 years agoBootLinuxSshTest: Test some userspace commands on Malta
Philippe Mathieu-Daudé [Thu, 23 May 2019 16:18:32 +0000 (18:18 +0200)] 
BootLinuxSshTest: Test some userspace commands on Malta

This tests boot a full VM and check the serial console until
the SSH daemon is running, then start a SSH session and run
some commands.

This test can be run using:

  $ avocado --show=ssh run -t arch:mips tests/acceptance/linux_ssh_mips_malta.py
  ssh: Entering interactive session.
  ssh: # uname -a
  ssh: Linux debian-mips 3.2.0-4-4kc-malta #1 Debian 3.2.51-1 mips GNU/Linux
  ssh: # lspci -d 11ab:4620
  ssh: 00:00.0 Host bridge: Marvell Technology Group Ltd. GT-64120/64120A/64121A System Controller (rev 10)
  ssh: # cat /sys/bus/i2c/devices/i2c-0/name
  ssh: SMBus PIIX4 adapter at 1100
  ssh: # cat /proc/mtd
  ssh: dev:    size   erasesize  name
  ssh: mtd0: 00100000 00010000 "YAMON"
  ssh: mtd1: 002e0000 00010000 "User FS"
  ssh: mtd2: 00020000 00010000 "Board Config"
  ssh: # md5sum /dev/mtd2ro
  ssh: 0dfbe8aa4c20b52e1b8bf3cb6cbdf193  /dev/mtd2ro
  ssh: # poweroff

Acked-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
Message-Id: <20190523161832.22490-5-f4bug@amsat.org>

2 years agotarget/mips: realign comments to fix checkpatch warnings
Jules Irenge [Sat, 13 Apr 2019 20:28:18 +0000 (21:28 +0100)] 
target/mips: realign comments to fix checkpatch warnings

Realign comments to fix warnings issued by checkpatc.pl tool
 "WARNING: Block comments use a leading /* on a separate line"
within "target/mips/cpu.h" file.

Signed-off-by: Jules Irenge <jbi.octave@gmail.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <20190413202818.13622-3-jbi.octave@gmail.com>

2 years agotarget/mips: add or remove space to fix checkpatch errors
Jules Irenge [Sat, 13 Apr 2019 20:28:17 +0000 (21:28 +0100)] 
target/mips: add or remove space to fix checkpatch errors

Add or remove space to fix errors issued by checkpatch.pl tool
"ERROR: spaces required around that..."
"ERROR: space required after that..."
"ERROR: space required before the open parenthesis"
"ERROR: space required after that..."
"ERROR: space prohibited between function name and open parenthesis"
"ERROR: code indent should never use tabs"
"ERROR: line over 90 characters"
within "target/mips/cpu.h" file.

Signed-off-by: Jules Irenge <jbi.octave@gmail.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <20190413202818.13622-2-jbi.octave@gmail.com>

2 years agolinux-user: fix __NR_semtimedop undeclared error
Laurent Vivier [Thu, 23 May 2019 17:54:13 +0000 (19:54 +0200)] 
linux-user: fix __NR_semtimedop undeclared error

In current code, __NR_msgrcv and__NR_semtimedop are supposed to be
defined if __NR_msgsnd is defined.

But linux headers 5.2-rc1 for MIPS define __NR_msgsnd without defining
__NR_semtimedop and it breaks the QEMU build.

__NR_semtimedop is defined in asm-mips/unistd_n64.h and asm-mips/unistd_n32.h
but not in asm-mips/unistd_o32.h.

Commit d9cb4336159a ("linux headers: update against Linux 5.2-rc1") has
updated asm-mips/unistd_o32.h and added __NR_msgsnd but not __NR_semtimedop.
It introduces __NR_semtimedop_time64 instead.

This patch fixes the problem by checking for each __NR_XXX symbol
before defining the corresponding syscall.

Fixes: d9cb4336159a ("linux headers: update against Linux 5.2-rc1")
Reported-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Reviewed-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Tested-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20190523175413.14448-1-laurent@vivier.eu>

2 years agomips: Decide to map PAGE_EXEC in map_address
Jakub Jermář [Fri, 17 May 2019 12:35:33 +0000 (14:35 +0200)] 
mips: Decide to map PAGE_EXEC in map_address

This commit addresses QEMU Bug #1825311:

  mips_cpu_handle_mmu_fault renders all accessed pages executable

It allows finer-grained control over whether the accessed page should
be executable by moving the decision to the underlying map_address
function, which has more information for this.

As a result, pages that have the XI bit set in the TLB and are accessed
for read/write, don't suddenly end up being executable.

Fixes: https://bugs.launchpad.net/qemu/+bug/1825311
Fixes: 2fb58b73746e ('target-mips: add RI and XI fields to TLB entry')

Signed-off-by: Jakub Jermář <jakub.jermar@kernkonzept.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20190517123533.868479-1-jakub.jermar@kernkonzept.com>

2 years agotarget/mips: Refactor and fix INSERT.<B|H|W|D> instructions
Mateja Marjanovic [Tue, 2 Apr 2019 13:43:25 +0000 (15:43 +0200)] 
target/mips: Refactor and fix INSERT.<B|H|W|D> instructions

The old version of the helper for the INSERT.<B|H|W|D> MSA instructions
has been replaced with four helpers that don't use switch, and change
the endianness of the given index, when executed on a big endian host.

Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1554212605-16457-6-git-send-email-mateja.marjanovic@rt-rk.com>

2 years agotarget/mips: Refactor and fix COPY_U.<B|H|W> instructions
Mateja Marjanovic [Tue, 2 Apr 2019 13:43:24 +0000 (15:43 +0200)] 
target/mips: Refactor and fix COPY_U.<B|H|W> instructions

The old version of the helper for the COPY_U.<B|H|W> MSA instructions
has been replaced with four helpers that don't use switch, and change
the endianness of the given index, when executed on a big endian host.

Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1554212605-16457-5-git-send-email-mateja.marjanovic@rt-rk.com>

2 years agotarget/mips: Refactor and fix COPY_S.<B|H|W|D> instructions
Mateja Marjanovic [Tue, 2 Apr 2019 13:43:23 +0000 (15:43 +0200)] 
target/mips: Refactor and fix COPY_S.<B|H|W|D> instructions

The old version of the helper for the COPY_S.<B|H|W|D> MSA instructions
has been replaced with four helpers that don't use switch, and change
the endianness of the given index, when executed on a big endian host.

Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1554212605-16457-4-git-send-email-mateja.marjanovic@rt-rk.com>

2 years agotarget/mips: Fix MSA instructions ST.<B|H|W|D> on big endian host
Mateja Marjanovic [Tue, 2 Apr 2019 13:43:22 +0000 (15:43 +0200)] 
target/mips: Fix MSA instructions ST.<B|H|W|D> on big endian host

Fix the case when the host is a big endian machine, and change
the approach toward ST.<B|H|W|D> instruction helpers.

Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1554212605-16457-3-git-send-email-mateja.marjanovic@rt-rk.com>

2 years agotarget/mips: Fix MSA instructions LD.<B|H|W|D> on big endian host
Mateja Marjanovic [Tue, 2 Apr 2019 13:43:21 +0000 (15:43 +0200)] 
target/mips: Fix MSA instructions LD.<B|H|W|D> on big endian host

Fix the case when the host is a big endian machine, and change
the approach toward LD.<B|H|W|D> instruction helpers.

Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1554212605-16457-2-git-send-email-mateja.marjanovic@rt-rk.com>

2 years agotarget/mips: Make the results of MOD_<U|S>.<B|H|W|D> the same as on hardware
Mateja Marjanovic [Tue, 2 Apr 2019 12:11:50 +0000 (14:11 +0200)] 
target/mips: Make the results of MOD_<U|S>.<B|H|W|D> the same as on hardware

MSA instructions MOD_<U|S>.<B|H|W|D> when dividing by zero,
didn't return the same value when executed on a referent hardware
(FPGA MIPS 64 r6, little endian) and when executed on QEMU, which
is not a real bug, because the result when dividing by zero is
UNPREDICTABLE [1] (page 255, 256).

[1] MIPS Architecture for Programmers
    Volume IV-j: The MIPS64 SIMD
    Architecture Module, Revision 1.12

Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1554207110-9113-3-git-send-email-mateja.marjanovic@rt-rk.com>

2 years agotarget/mips: Make the results of DIV_<U|S>.<B|H|W|D> the same as on hardware
Mateja Marjanovic [Tue, 2 Apr 2019 12:11:49 +0000 (14:11 +0200)] 
target/mips: Make the results of DIV_<U|S>.<B|H|W|D> the same as on hardware

MSA instructions DIV_<U|S>.<B|H|W|D> when dividing by zero,
didn't return the same value when executed on a referent hardware
(FPGA MIPS 64 r6, little endian) and when executed on QEMU, which
is not a real bug, because the result when dividing by zero is
UNPREDICTABLE [1] (page 141, 142).

[1] MIPS Architecture for Programmers
    Volume IV-j: The MIPS64 SIMD
    Architecture Module, Revision 1.12

Signed-off-by: Mateja Marjanovic <mateja.marjanovic@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Message-Id: <1554207110-9113-2-git-send-email-mateja.marjanovic@rt-rk.com>

2 years agotarget/riscv: Only flush TLB if SATP.ASID changes
Jonathan Behrens [Wed, 8 May 2019 17:38:35 +0000 (13:38 -0400)] 
target/riscv: Only flush TLB if SATP.ASID changes

There is an analogous change for ARM here:
https://patchwork.kernel.org/patch/10649857

Signed-off-by: Jonathan Behrens <jonathan@fintelia.io>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2 years agotarget/riscv: More accurate handling of `sip` CSR
Jonathan Behrens [Tue, 7 May 2019 22:36:46 +0000 (18:36 -0400)] 
target/riscv: More accurate handling of `sip` CSR

According to the spec, "All bits besides SSIP, USIP, and UEIP in the sip
register are read-only." Further, if an interrupt is not delegated to mode x,
then "the corresponding bits in xip [...] should appear to be hardwired to
zero. This patch implements both of those requirements.

Signed-off-by: Jonathan Behrens <jonathan@fintelia.io>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2 years agotarget/riscv: Add checks for several RVC reserved operands
Richard Henderson [Thu, 25 Apr 2019 17:26:36 +0000 (10:26 -0700)] 
target/riscv: Add checks for several RVC reserved operands

C.ADDI16SP, C.LWSP, C.JR, C.ADDIW, C.LDSP all have reserved
operands that were not diagnosed.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2 years agotarget/riscv: Add the HGATP register masks
Alistair Francis [Sat, 20 Apr 2019 02:27:43 +0000 (02:27 +0000)] 
target/riscv: Add the HGATP register masks

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2 years agotarget/riscv: Add the HSTATUS register masks
Alistair Francis [Sat, 20 Apr 2019 02:27:35 +0000 (02:27 +0000)] 
target/riscv: Add the HSTATUS register masks

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviwed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2 years agotarget/riscv: Add Hypervisor CSR macros
Alistair Francis [Sat, 20 Apr 2019 02:27:26 +0000 (02:27 +0000)] 
target/riscv: Add Hypervisor CSR macros

Add the 1.10.1 Hypervisor CSRs and remove the 1.9.1 spec versions.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2 years agotarget/riscv: Allow setting mstatus virtulisation bits
Alistair Francis [Sat, 20 Apr 2019 02:27:18 +0000 (02:27 +0000)] 
target/riscv: Allow setting mstatus virtulisation bits

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Revieweb-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2 years agotarget/riscv: Add the MPV and MTL mstatus bits
Alistair Francis [Sat, 20 Apr 2019 02:27:10 +0000 (02:27 +0000)] 
target/riscv: Add the MPV and MTL mstatus bits

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2 years agotarget/riscv: Improve the scause logic
Alistair Francis [Sat, 20 Apr 2019 02:27:02 +0000 (02:27 +0000)] 
target/riscv: Improve the scause logic

No functional change, just making the code easier to read.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2 years agotarget/riscv: Trigger interrupt on MIP update asynchronously
Alistair Francis [Sat, 20 Apr 2019 02:26:54 +0000 (02:26 +0000)] 
target/riscv: Trigger interrupt on MIP update asynchronously

The requirement of holding the iothread_mutex is burdersome when
swapping the background and foreground registers in the Hypervisor
extension. To avoid the requrirement let's set the interrupt
asynchronously.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2 years agotarget/riscv: Mark privilege level 2 as reserved
Alistair Francis [Sat, 20 Apr 2019 02:26:45 +0000 (02:26 +0000)] 
target/riscv: Mark privilege level 2 as reserved

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2 years agoriscv: spike: Add a generic spike machine
Alistair Francis [Sat, 20 Apr 2019 02:24:26 +0000 (02:24 +0000)] 
riscv: spike: Add a generic spike machine

Add a generic spike machine (not tied to a version) and deprecate the
spike mahines that are tied to a specific version. As we can now specify
the CPU via the command line we no londer need specific versions of the
spike machines.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Acked-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2 years agotarget/riscv: Deprecate the generic no MMU CPUs
Alistair Francis [Sat, 20 Apr 2019 02:24:18 +0000 (02:24 +0000)] 
target/riscv: Deprecate the generic no MMU CPUs

These can now be specified via the command line so we no longer need
these.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2 years agotarget/riscv: Add a base 32 and 64 bit CPU
Alistair Francis [Sat, 20 Apr 2019 02:24:09 +0000 (02:24 +0000)] 
target/riscv: Add a base 32 and 64 bit CPU

At the same time deprecate the ISA string CPUs.

It is dobtful anyone specifies the CPUs, but we are keeping them for the
Spike machine (which is about to be depreated) so we may as well just
mark them as deprecated.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2 years agotarget/riscv: Create settable CPU properties
Alistair Francis [Sat, 20 Apr 2019 02:24:01 +0000 (02:24 +0000)] 
target/riscv: Create settable CPU properties

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2 years agoriscv: virt: Allow specifying a CPU via commandline
Alistair Francis [Sat, 20 Apr 2019 02:23:53 +0000 (02:23 +0000)] 
riscv: virt: Allow specifying a CPU via commandline

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Igor Mammedov <imammedo@redhat.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2 years agolinux-user/riscv: Add the CPU type as a comment
Alistair Francis [Sat, 20 Apr 2019 02:23:44 +0000 (02:23 +0000)] 
linux-user/riscv: Add the CPU type as a comment

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2 years agotarget/riscv: Remove unused include of riscv_htif.h for virt board riscv
Jonathan Behrens [Thu, 11 Apr 2019 15:08:57 +0000 (11:08 -0400)] 
target/riscv: Remove unused include of riscv_htif.h for virt board riscv

Signed-off-by: Jonathan Behrens <fintelia@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2 years agotarget/riscv: Remove spaces from register names
Richard Henderson [Mon, 1 Apr 2019 03:11:55 +0000 (10:11 +0700)] 
target/riscv: Remove spaces from register names

These extra spaces make the "-d op" dump look weird.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2 years agotarget/riscv: Split gen_arith_imm into functional and temp
Richard Henderson [Mon, 1 Apr 2019 03:11:54 +0000 (10:11 +0700)] 
target/riscv: Split gen_arith_imm into functional and temp

The tcg_gen_fooi_tl functions have some immediate constant
folding built in, which match up with some of the riscv asm
builtin macros, like mv and not.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2 years agotarget/riscv: Split RVC32 and RVC64 insns into separate files
Richard Henderson [Mon, 1 Apr 2019 03:11:53 +0000 (10:11 +0700)] 
target/riscv: Split RVC32 and RVC64 insns into separate files

This eliminates all functions in insn_trans/trans_rvc.inc.c,
so the entire file can be removed.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2 years agotarget/riscv: Use pattern groups in insn16.decode
Richard Henderson [Mon, 1 Apr 2019 03:11:52 +0000 (10:11 +0700)] 
target/riscv: Use pattern groups in insn16.decode

This eliminates about half of the complicated decode
bits within insn_trans/trans_rvc.inc.c.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2 years agotarget/riscv: Merge argument decode for RVC shifti
Richard Henderson [Mon, 1 Apr 2019 03:11:51 +0000 (10:11 +0700)] 
target/riscv: Merge argument decode for RVC shifti

Special handling for IMM==0 is the only difference between
RVC shifti and RVI shifti.  This can be handled with !function.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2 years agotarget/riscv: Merge argument sets for insn32 and insn16
Richard Henderson [Mon, 1 Apr 2019 03:11:50 +0000 (10:11 +0700)] 
target/riscv: Merge argument sets for insn32 and insn16

In some cases this allows us to directly use the insn32
translator function.  In some cases we still need a shim.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2 years agotarget/riscv: Use --static-decode for decodetree
Richard Henderson [Mon, 1 Apr 2019 03:11:49 +0000 (10:11 +0700)] 
target/riscv: Use --static-decode for decodetree

The generated functions are only used within translate.c
and do not need to be global, or declared.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2 years agotarget/riscv: Name the argument sets for all of insn32 formats
Richard Henderson [Mon, 1 Apr 2019 03:11:48 +0000 (10:11 +0700)] 
target/riscv: Name the argument sets for all of insn32 formats

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2 years agoRISC-V: fix single stepping over ret and other branching instructions
Fabien Chouteau [Mon, 25 Mar 2019 11:45:54 +0000 (12:45 +0100)] 
RISC-V: fix single stepping over ret and other branching instructions

This patch introduces wrappers around the tcg_gen_exit_tb() and
tcg_gen_lookup_and_goto_ptr() functions that handle single stepping,
i.e. call gen_exception_debug() when single stepping is enabled.

Theses functions are then used instead of the originals, bringing single
stepping handling in places where it was previously ignored such as jalr
and system branch instructions (ecall, mret, sret, etc.).

Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2 years agotarget/riscv: Do not allow sfence.vma from user mode
Jonathan Behrens [Mon, 1 Apr 2019 19:12:07 +0000 (15:12 -0400)] 
target/riscv: Do not allow sfence.vma from user mode

The 'sfence.vma' instruction is privileged, and should only ever be allowed
when executing in supervisor mode or higher.

Signed-off-by: Jonathan Behrens <fintelia@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2 years agoSiFive RISC-V GPIO Device
Fabien Chouteau [Tue, 12 Feb 2019 17:38:39 +0000 (18:38 +0100)] 
SiFive RISC-V GPIO Device

QEMU model of the GPIO device on the SiFive E300 series SOCs.

The pins are not used by a board definition yet, however this
implementation can already be used to trigger GPIO interrupts from the
software by configuring a pin as both output and input.

Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2 years agohw/intc/nvic: Use object_initialize_child for correct reference counting
Philippe Mathieu-Daudé [Tue, 7 May 2019 16:34:16 +0000 (18:34 +0200)] 
hw/intc/nvic: Use object_initialize_child for correct reference counting

As explained in commit aff39be0ed97:

  Both functions, object_initialize() and object_property_add_child()
  increase the reference counter of the new object, so one of the
  references has to be dropped afterwards to get the reference
  counting right. Otherwise the child object will not be properly
  cleaned up when the parent gets destroyed.
  Thus let's use now object_initialize_child() instead to get the
  reference counting here right.

This patch was generated using the following Coccinelle script:

 @use_sysbus_init_child_obj_missing_parent@
 expression child_ptr;
 expression child_type;
 expression child_size;
 @@
 -   object_initialize(child_ptr, child_size, child_type);
     ...
 -   qdev_set_parent_bus(DEVICE(child_ptr), sysbus_get_default());
     ...
 ?-  object_unref(OBJECT(child_ptr));
 +   sysbus_init_child_obj(OBJECT(PARENT_OBJ), "CHILD_NAME", child_ptr,
 +                         child_size, child_type);

We let NVIC adopt the SysTick timer.

While the object_initialize() function doesn't take an
'Error *errp' argument, the object_initialize_child() does.
Since this code is used when a machine is created (and is not
yet running), we deliberately choose to use the &error_abort
argument instead of ignoring errors if an object creation failed.
This choice also matches when using sysbus_init_child_obj(),
since its code is:

  void sysbus_init_child_obj(Object *parent,
                             const char *childname, void *child,
                             size_t childsize, const char *childtype)
  {
      object_initialize_child(parent, childname, child, childsize,
                              childtype, &error_abort, NULL);

      qdev_set_parent_bus(DEVICE(child), sysbus_get_default());
  }

Suggested-by: Eduardo Habkost <ehabkost@redhat.com>
Inspired-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20190507163416.24647-17-philmd@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2 years agohw/arm/mps2: Use object_initialize_child for correct reference counting
Philippe Mathieu-Daudé [Tue, 7 May 2019 16:34:15 +0000 (18:34 +0200)] 
hw/arm/mps2: Use object_initialize_child for correct reference counting

As explained in commit aff39be0ed97:

  Both functions, object_initialize() and object_property_add_child()
  increase the reference counter of the new object, so one of the
  references has to be dropped afterwards to get the reference
  counting right. Otherwise the child object will not be properly
  cleaned up when the parent gets destroyed.
  Thus let's use now object_initialize_child() instead to get the
  reference counting here right.

This patch was generated using the following Coccinelle script:

 @use_sysbus_init_child_obj_missing_parent@
 expression child_ptr;
 expression child_type;
 expression child_size;
 @@
 -   object_initialize(child_ptr, child_size, child_type);
     ...
 -   qdev_set_parent_bus(DEVICE(child_ptr), sysbus_get_default());
     ...
 ?-  object_unref(OBJECT(child_ptr));
 +   sysbus_init_child_obj(OBJECT(PARENT_OBJ), "CHILD_NAME", child_ptr,
 +                         child_size, child_type);

We let the MPS2 boards adopt the cpu core, the FPGA and the SCC children.

While the object_initialize() function doesn't take an
'Error *errp' argument, the object_initialize_child() does.
Since this code is used when a machine is created (and is not
yet running), we deliberately choose to use the &error_abort
argument instead of ignoring errors if an object creation failed.
This choice also matches when using sysbus_init_child_obj(),
since its code is:

  void sysbus_init_child_obj(Object *parent,
                             const char *childname, void *child,
                             size_t childsize, const char *childtype)
  {
      object_initialize_child(parent, childname, child, childsize,
                              childtype, &error_abort, NULL);

      qdev_set_parent_bus(DEVICE(child), sysbus_get_default());
  }

Suggested-by: Eduardo Habkost <ehabkost@redhat.com>
Inspired-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20190507163416.24647-16-philmd@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2 years agohw/microblaze/zynqmp: Use object_initialize_child for correct ref. counting
Philippe Mathieu-Daudé [Tue, 7 May 2019 16:34:14 +0000 (18:34 +0200)] 
hw/microblaze/zynqmp: Use object_initialize_child for correct ref. counting

As explained in commit aff39be0ed97:

  Both functions, object_initialize() and object_property_add_child()
  increase the reference counter of the new object, so one of the
  references has to be dropped afterwards to get the reference
  counting right. Otherwise the child object will not be properly
  cleaned up when the parent gets destroyed.
  Thus let's use now object_initialize_child() instead to get the
  reference counting here right.

This patch was generated using the following Coccinelle script
(with a bit of manual fix-up for overly long lines):

 @use_object_initialize_child@
 expression parent_obj;
 expression child_ptr;
 expression child_name;
 expression child_type;
 expression child_size;
 expression errp;
 @@
 (
 -   object_initialize(child_ptr, child_size, child_type);
 +   object_initialize_child(parent_obj, child_name,  child_ptr, child_size,
 +                           child_type, &error_abort, NULL);
     ... when != parent_obj
 -   object_property_add_child(parent_obj, child_name, OBJECT(child_ptr), NULL);
     ...
?-   object_unref(OBJECT(child_ptr));
 |
 -   object_initialize(child_ptr, child_size, child_type);
 +   object_initialize_child(parent_obj, child_name,  child_ptr, child_size,
 +                            child_type, errp, NULL);
     ... when != parent_obj
 -   object_property_add_child(parent_obj, child_name, OBJECT(child_ptr), errp);
     ...
?-   object_unref(OBJECT(child_ptr));
 )

While the object_initialize() function doesn't take an
'Error *errp' argument, the object_initialize_child() does.
Since this code is used when a machine is created (and is not
yet running), we deliberately choose to use the &error_abort
argument instead of ignoring errors if an object creation failed.

Suggested-by: Eduardo Habkost <ehabkost@redhat.com>
Inspired-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20190507163416.24647-15-philmd@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2 years agohw/microblaze/zynqmp: Use object_initialize_child for correct ref. counting
Philippe Mathieu-Daudé [Tue, 7 May 2019 16:34:13 +0000 (18:34 +0200)] 
hw/microblaze/zynqmp: Use object_initialize_child for correct ref. counting

As explained in commit aff39be0ed97:

  Both functions, object_initialize() and object_property_add_child()
  increase the reference counter of the new object, so one of the
  references has to be dropped afterwards to get the reference
  counting right. Otherwise the child object will not be properly
  cleaned up when the parent gets destroyed.
  Thus let's use now object_initialize_child() instead to get the
  reference counting here right.

This patch was generated using the following Coccinelle script
(then manually modified to use numbered IPI name)

 @use_sysbus_init_child_obj_missing_parent@
 expression child_ptr;
 expression child_type;
 expression child_size;
 @@
 -   object_initialize(child_ptr, child_size, child_type);
     ...
 -   qdev_set_parent_bus(DEVICE(child_ptr), sysbus_get_default());
     ...
 ?-  object_unref(OBJECT(child_ptr));
 +   sysbus_init_child_obj(OBJECT(PARENT_OBJ), "CHILD_NAME", child_ptr,
 +                         child_size, child_type);

We let the SoC adopt the IPI children.

While the object_initialize() function doesn't take an
'Error *errp' argument, the object_initialize_child() does.
Since this code is used when a machine is created (and is not
yet running), we deliberately choose to use the &error_abort
argument instead of ignoring errors if an object creation failed.
This choice also matches when using sysbus_init_child_obj(),
since its code is:

  void sysbus_init_child_obj(Object *parent,
                             const char *childname, void *child,
                             size_t childsize, const char *childtype)
  {
      object_initialize_child(parent, childname, child, childsize,
                              childtype, &error_abort, NULL);

      qdev_set_parent_bus(DEVICE(child), sysbus_get_default());
  }

Suggested-by: Eduardo Habkost <ehabkost@redhat.com>
Inspired-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20190507163416.24647-14-philmd@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2 years agohw/microblaze/zynqmp: Let the SoC manage the IPI devices
Philippe Mathieu-Daudé [Tue, 7 May 2019 16:34:12 +0000 (18:34 +0200)] 
hw/microblaze/zynqmp: Let the SoC manage the IPI devices

The Inter Processor Interrupt is a block part of the SoC, not the
"machine" (See Zynq UltraScale+ Device TRM UG1085, "Platform
Management Unit", Power Domains and Islands).

Move the IPI management from the machine to the SoC.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20190507163416.24647-13-philmd@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2 years agohw/microblaze/zynqmp: Move the IPI state into the PMUSoC state
Philippe Mathieu-Daudé [Tue, 7 May 2019 16:34:11 +0000 (18:34 +0200)] 
hw/microblaze/zynqmp: Move the IPI state into the PMUSoC state

The Inter Processor Interrupt is a block part of the SoC, not the
"machine" (talking about machine is borderline with the PMU, since
it is embedded into the ZynqMP SoC, but currentl QEMU doesn't
support multi-arch cores).

Move the IPI state to the SoC state, this will simplify the review
of the next patch.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20190507163416.24647-12-philmd@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2 years agohw/mips: Use object_initialize_child for correct reference counting
Philippe Mathieu-Daudé [Tue, 7 May 2019 16:34:10 +0000 (18:34 +0200)] 
hw/mips: Use object_initialize_child for correct reference counting

As explained in commit aff39be0ed97:

  Both functions, object_initialize() and object_property_add_child()
  increase the reference counter of the new object, so one of the
  references has to be dropped afterwards to get the reference
  counting right. Otherwise the child object will not be properly
  cleaned up when the parent gets destroyed.
  Thus let's use now object_initialize_child() instead to get the
  reference counting here right.

This patch was generated using the following Coccinelle script:

 @use_sysbus_init_child_obj_missing_parent@
 expression child_ptr;
 expression child_type;
 expression child_size;
 @@
 -   object_initialize(child_ptr, child_size, child_type);
     ...
 -   qdev_set_parent_bus(DEVICE(child_ptr), sysbus_get_default());
     ...
 ?-  object_unref(OBJECT(child_ptr));
 +   sysbus_init_child_obj(OBJECT(PARENT_OBJ), "CHILD_NAME", child_ptr,
 +                         child_size, child_type);

We let the Malta/Boston machines adopt the CPS child, and similarly
the CPS adopts the ITU/CPC/GIC/GCR children.

While the object_initialize() function doesn't take an
'Error *errp' argument, the object_initialize_child() does.
Since this code is used when a machine is created (and is not
yet running), we deliberately choose to use the &error_abort
argument instead of ignoring errors if an object creation failed.
This choice also matches when using sysbus_init_child_obj(),
since its code is:

  void sysbus_init_child_obj(Object *parent,
                             const char *childname, void *child,
                             size_t childsize, const char *childtype)
  {
      object_initialize_child(parent, childname, child, childsize,
                              childtype, &error_abort, NULL);

      qdev_set_parent_bus(DEVICE(child), sysbus_get_default());
  }

Suggested-by: Eduardo Habkost <ehabkost@redhat.com>
Inspired-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20190507163416.24647-11-philmd@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2 years agohw/mips: Use object_initialize() on MIPSCPSState
Philippe Mathieu-Daudé [Tue, 7 May 2019 16:34:09 +0000 (18:34 +0200)] 
hw/mips: Use object_initialize() on MIPSCPSState

Initialize the MIPSCPSState with object_initialize() instead of
object_new(). This will allow us to add it as children of the
machine container.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20190507163416.24647-10-philmd@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
2 years agohw/arm: Use object_initialize_child for correct reference counting
Philippe Mathieu-Daudé [Tue, 7 May 2019 16:34:08 +0000 (18:34 +0200)] 
hw/arm: Use object_initialize_child for correct reference counting

As explained in commit aff39be0ed97:

  Both functions, object_initialize() and object_property_add_child()
  increase the reference counter of the new object, so one of the
  references has to be dropped afterwards to get the reference
  counting right. Otherwise the child object will not be properly
  cleaned up when the parent gets destroyed.
  Thus let's use now object_initialize_child() instead to get the
  reference counting here right.

This patch was generated using the following Coccinelle script
(with a bit of manual fix-up for overly long lines):

 @use_object_initialize_child@
 expression parent_obj;
 expression child_ptr;
 expression child_name;
 expression child_type;
 expression child_size;
 expression errp;
 @@
 (
 -   object_initialize(child_ptr, child_size, child_type);
 +   object_initialize_child(parent_obj, child_name,  child_ptr, child_size,
 +                           child_type, &error_abort, NULL);
     ... when != parent_obj
 -   object_property_add_child(parent_obj, child_name, OBJECT(child_ptr), NULL);
     ...
 ?-  object_unref(OBJECT(child_ptr));
 |
 -   object_initialize(child_ptr, child_size, child_type);
 +   object_initialize_child(parent_obj, child_name,  child_ptr, child_size,
 +                            child_type, errp, NULL);
     ... when != parent_obj
 -   object_property_add_child(parent_obj, child_name, OBJECT(child_ptr), errp);
     ...
 ?-  object_unref(OBJECT(child_ptr));
 )

 @use_sysbus_init_child_obj@
 expression parent_obj;
 expression dev;
 expression child_ptr;
 expression child_name;
 expression child_type;
 expression child_size;
 expression errp;
 @@
 (
 -   object_initialize_child(parent_obj, child_name, child_ptr, child_size,
 -                           child_type, errp, NULL);
 +   sysbus_init_child_obj(parent_obj, child_name, child_ptr, child_size,
 +                         child_type);
     ...
 -   qdev_set_parent_bus(DEVICE(child_ptr), sysbus_get_default());
 |
 -   object_initialize_child(parent_obj, child_name, child_ptr, child_size,
 -                           child_type, errp, NULL);
 +   sysbus_init_child_obj(parent_obj, child_name, child_ptr, child_size,
 +                         child_type);
 -   dev = DEVICE(child_ptr);
 -   qdev_set_parent_bus(dev, sysbus_get_default());
 )

While the object_initialize() function doesn't take an
'Error *errp' argument, the object_initialize_child() does.
Since this code is used when a machine is created (and is not
yet running), we deliberately choose to use the &error_abort
argument instead of ignoring errors if an object creation failed.
This choice also matches when using sysbus_init_child_obj(),
since its code is:

  void sysbus_init_child_obj(Object *parent,
                             const char *childname, void *child,
                             size_t childsize, const char *childtype)
  {
      object_initialize_child(parent, childname, child, childsize,
                              childtype, &error_abort, NULL);

      qdev_set_parent_bus(DEVICE(child), sysbus_get_default());
  }

Suggested-by: Eduardo Habkost <ehabkost@redhat.com>
Inspired-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Message-Id: <20190507163416.24647-9-philmd@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>