skiboot.git
5 days agoxscom: Parse P10 ec revision master
Joel Stanley [Tue, 17 May 2022 08:46:22 +0000 (18:16 +0930)] 
xscom: Parse P10 ec revision

Use a look up table to support the p9, p10dd1 and p10dd2 conversions.

Running on a Rainier:

> [  268.267370706,6] CPU: P10 generation processor (max 4 threads/core)
> [  268.267372501,7] CPU: Boot CPU PIR is 0x0460 PVR is 0x00801200

> [  268.284420384,5] CHIP: Chip ID 0000 type: P10 DD2.02
> [  268.284464084,5] CHIP: Chip ID 0002 type: P10 DD2.02
> [  268.284500468,5] CHIP: Chip ID 0004 type: P10 DD2.02
> [  268.284538166,5] CHIP: Chip ID 0006 type: P10 DD2.02
> [  268.286317879,5] PLAT: Detected Rainier platform

Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Dan Horák <dan@danny.cz>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
5 days agoxscom: Move p9 ec level parsing to a function
Joel Stanley [Tue, 17 May 2022 08:46:21 +0000 (18:16 +0930)] 
xscom: Move p9 ec level parsing to a function

In preparation for adding p10 logic. No functional change.

Reviewed-by: Dan Horák <dan@danny.cz>
Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2 weeks agoCI: Clean up and re-enable testing on Fedora rawhide
Frederic Barrat [Fri, 6 May 2022 14:48:07 +0000 (16:48 +0200)] 
CI: Clean up and re-enable testing on Fedora rawhide

Testing on rawhide somehow vanished when we converted to github
actions. This patch cleans up the related CI files and re-enables it.

Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2 weeks agoCI: Add testing on Ubuntu 22.04 LTS
Frederic Barrat [Fri, 6 May 2022 14:48:06 +0000 (16:48 +0200)] 
CI: Add testing on Ubuntu 22.04 LTS

New LTS release from Canonical. So let's split it from ubuntu-rolling,
which will keep tracking the latest.

Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2 weeks agoCI: Update python dependency on Ubuntu rolling
Frederic Barrat [Fri, 6 May 2022 14:48:05 +0000 (16:48 +0200)] 
CI: Update python dependency on Ubuntu rolling

Package 'python' no longer exists. Replace it with 'python3'

Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
4 weeks agoflash: Make PNOR partition encoding size 64 bit safe.
Aneesh Kumar K.V [Tue, 19 Apr 2022 16:54:57 +0000 (22:24 +0530)] 
flash: Make PNOR partition encoding size 64 bit safe.

Similar to commit: c043065cf923 ("flash: Make size 64 bit safe")
update the encoding for PNOR partition which is the partition that is mapping
the full disk 64 bit safe.

Without this mambo disk larger than 4G fails to mount with the below error:
[    2.075170] EXT4-fs (mtdblock0): bad geometry: block count 7864320 exceeds size of device (524288 blocks)

Fixes: 27fcf2fa8350 ("Expose PNOR Flash partitions to host MTD driver via devicetree")
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2 months agogithub: Run update before installing packages
Joel Stanley [Wed, 16 Mar 2022 12:32:23 +0000 (23:02 +1030)] 
github: Run update before installing packages

The Github CI runners sometimes need to update their apt cache, or
packages fail to install:

 E: Failed to fetch http://security.ubuntu.com/ubuntu/pool/main/g/gcc-9-cross/gcc-9-powerpc64le-linux-gnu_9.3.0-17ubuntu1~20.04cross2_amd64.deb  404  Not Found [IP: 40.81.13.82 80]
 E: Unable to fetch some archives, maybe run apt-get update or try with --fix-missing?
 Error: Process completed with exit code 100.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2 months agolibstb/create-container: avoid using deprecated APIs when compiling with OpenSSL 3.0
Eric Richter [Wed, 19 Jan 2022 20:16:12 +0000 (14:16 -0600)] 
libstb/create-container: avoid using deprecated APIs when compiling with OpenSSL 3.0

OpenSSL 3.0 has deprecated functions that operate on raw key data, however the
closest replacement function are not available in OpenSSL 1.x. This patch
attempts to maintain compatibility with both 3.0 and 1.x versions.

Avoids using the following deprecated functions when compiling with 3.0:
 - EC_KEY_get0_group
 - EC_KEY_get0_public_key
 - EC_POINT_point2bn
 - EC_KEY_free

Signed-off-by: Eric Richter <erichte@linux.ibm.com>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2 months agogithub: Add workflow to build and deploy docs
Joel Stanley [Tue, 8 Mar 2022 01:45:43 +0000 (12:15 +1030)] 
github: Add workflow to build and deploy docs

This builds the gcov coverage report and the skiboot docs on the Github
hosted runner, without using a container.

Remove the CROSS= definition from build-docs.sh to allow the makefile
detect which cross compiler is installed, instead of hardcoding the
non-le variant.

This is a simplification from the previous docs build, which used the
containers. However the containers have since been re-worked and no
longer leave the build artifacts on the host system.

The github action used for deploying seems to be the most commonly used:

 https://github.com/JamesIves/github-pages-deploy-action

Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2 months agoMakefile: Fix detection of cross compiler
Joel Stanley [Tue, 8 Mar 2022 01:45:42 +0000 (12:15 +1030)] 
Makefile: Fix detection of cross compiler

The Fedora containers don't have 'which' installed. This means the
detection of the cross compiler gives false negatives, leaving CROSS
undefined.

Instead use command -v, which outputs the path of the executable if it
exists.

Fixes: 9cd556ca1e5f ("Makefile: Search for distro-provided cross-compiler")
Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2 months agoci: remove Fedora 33
Dan Horák [Mon, 7 Mar 2022 14:59:20 +0000 (15:59 +0100)] 
ci: remove Fedora 33

Fedora 33 has been EOL since the end of 2021, so remove it from the CI
setup.

Signed-off-by: Dan Horák <dan@danny.cz>
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
2 months agodoc: Remove docutils version pin
Joel Stanley [Mon, 7 Mar 2022 03:05:58 +0000 (13:35 +1030)] 
doc: Remove docutils version pin

The current release is 0.18.1, so as long as the systems has greater
than 0.15 we should be okay. Obviously when installing from pip the
build will be fine.

 Ubuntu 18.04: 0.14
 Ubuntu 20.04: 0.16
 Fedora 33: 0.16

Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Dan Horák <dan@danny.cz>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2 months agoci: Remove Centos 8
Joel Stanley [Mon, 7 Mar 2022 02:24:21 +0000 (12:54 +1030)] 
ci: Remove Centos 8

With Centos 8 gone "EOL", the Centos 8 repositories have been moved(!)
causing the build to fail:

 Step 2/14 : RUN yum -y update && yum clean all
  ---> Running in 49e78cad4cda
 CentOS Linux 8 - AppStream                      424  B/s |  38  B     00:00
 Error: Failed to download metadata for repo 'appstream': Cannot prepare
 internal mirrorlist: No URLs in mirrorlist

Remove the build from CI as it no longer works.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Dan Horák <dan@danny.cz>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
3 months agoexternal/mambo: Handle greater than 16 CPUs
Michael Neuling [Fri, 4 Feb 2022 07:01:08 +0000 (18:01 +1100)] 
external/mambo: Handle greater than 16 CPUs

In OF mambo pads zeros in the CPU node names. So if you have more than
16 CPUs, the first core will be at /cpus/PowerPC@00. Currently we
always look for /cpus/PowerPC@0.

Fix by zero padding based on the max CPU count. This also converts to
hex since that's what's actually needed.

This fix should handle any topology. I've tested upto 128 threads (16
cores * 8 threads) but past that the mambo I have starts throwing
internal errors.

Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
3 months agoFix compilation waning "Missing #interrupt-cells"
Abhishek Singh Tomar [Wed, 2 Feb 2022 17:48:28 +0000 (23:18 +0530)] 
Fix compilation waning "Missing #interrupt-cells"

Resolve : "Missing #interrupt-cells" warning duriing dts(device tree source) compilation
hdata/test/p81-811.spira.dts:1434.37-1442.4: Warning (interrupt_provider): /interrupt-controller@3ffff80030000: Missing #interrupt-cells in interrupt provider

An #interrupt-cells added to both reference dts for testing and source code to generate dtb from hdata.

Signed-off-by: Abhishek Singh Tomar <abhishek@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
3 months agoFix array-bound compilation warnings
Abhishek Singh Tomar [Mon, 24 Jan 2022 13:56:12 +0000 (19:26 +0530)] 
Fix array-bound compilation warnings

Resolves : the warray bounds warning during compilation

/build/libc/include/string.h:34:16: warning: '__builtin_memset' offset [0, 2097151] is out of the bounds [0, 0] [-Warray-bounds]
34 | #define memset __builtin_memset
hw/fsp/fsp.c:1855:9: note: in expansion of macro 'memset'
1855 | memset(fsp_tce_table, 0, PSI_TCE_TABLE_SIZE);

use volatile pointer to avoid optimization introduced with gcc-11 on constant
address assignment to pointer.

Signed-off-by: Abhishek Singh Tomar <abhishek@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
4 months agoplatforms: put P8 platforms behind CONFIG_P8
Stewart Smith [Mon, 20 Dec 2021 12:22:52 +0000 (22:22 +1000)] 
platforms: put P8 platforms behind CONFIG_P8

Shaves an additional 4kb off skiboot.lid.xz.

Reviewed-by: Dan Horák <dan@danny.cz>
Signed-off-by: Stewart Smith <stewart@flamingspork.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
4 months agonpu: Move npu.o and npu-hw-procedules.o under CONIFG_P8
Stewart Smith [Mon, 20 Dec 2021 12:22:51 +0000 (22:22 +1000)] 
npu: Move npu.o and npu-hw-procedules.o under CONIFG_P8

Make the P8 NPU code depend on CONFIG_P8. This requires converting
a low level function to a no-op because the HMI NPU handling is not
so cleanly layered.

This saves an extra 6kb of skiboot.lid.xz.

Reviewed-by: Dan Horák <dan@danny.cz>
Signed-off-by: Stewart Smith <stewart@flamingspork.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
4 months agohwprobe: convert vas_init(), nx_init()
Stewart Smith [Mon, 20 Dec 2021 12:22:50 +0000 (22:22 +1000)] 
hwprobe: convert vas_init(), nx_init()

Convert VAS and NX to use the hwprobe facility for init.

Reviewed-by: Dan Horák <dan@danny.cz>
[npiggin: remove imc_init because it moved later in boot (fbcbd4e47c)]
Signed-off-by: Stewart Smith <stewart@flamingspork.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
4 months agohw/slw: split P8 specific code into its own file
Nicholas Piggin [Mon, 20 Dec 2021 12:22:49 +0000 (22:22 +1000)] 
hw/slw: split P8 specific code into its own file

POWER8 support is large and significantly different than P9/10 code.
This change prepares to make P8 support configurable.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
[ clg: Removed commented headers in slw.c ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
4 months agohw/slw: Move P8 bits behind CONFIG_P8
Nicholas Piggin [Mon, 20 Dec 2021 12:22:48 +0000 (22:22 +1000)] 
hw/slw: Move P8 bits behind CONFIG_P8

This saves about 10kB from skiboot.lid.xz

Reviewed-by: Dan Horák <dan@danny.cz>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
4 months agoSBE: create processor-independent timer APIs
Nicholas Piggin [Mon, 20 Dec 2021 12:22:47 +0000 (22:22 +1000)] 
SBE: create processor-independent timer APIs

Rather than have code call processor-specific SBE routines depending
on version, hide those details in SBE APIs.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
[ clg: Fixed run-timer test ]
Signed-off-by: Cédric Le Goater <clg@kaod.org>
4 months agoAdd CONFIG_P8 with PHB3 behind it
Stewart Smith [Mon, 20 Dec 2021 12:22:46 +0000 (22:22 +1000)] 
Add CONFIG_P8 with PHB3 behind it

We can use a base CPU of POWER9 if we don't have P8.
We can also hide PHB3 code behind this,
and shave 12kb off skiboot.lid.xz

Reviewed-by: Dan Horák <dan@danny.cz>
[npiggin: add cpp define, fail gracefully on P8]
Signed-off-by: Stewart Smith <stewart@flamingspork.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
4 months agohwprobe: convert PHB, NPU, PAU subsystems to hwprobe
Stewart Smith [Mon, 20 Dec 2021 12:22:45 +0000 (22:22 +1000)] 
hwprobe: convert PHB, NPU, PAU subsystems to hwprobe

Reviewed-by: Dan Horák <dan@danny.cz>
[npiggin: split out from initial hwprobe pach]
Signed-off-by: Stewart Smith <stewart@flamingspork.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
4 months agoIntroduce hwprobe facility to avoid hard-coding probe functions
Stewart Smith [Mon, 20 Dec 2021 12:22:44 +0000 (22:22 +1000)] 
Introduce hwprobe facility to avoid hard-coding probe functions

hwprobe is a little system to have different hardware probing modules
run in the dependency order they choose rather than hard coding
that order in core/init.c.

Reviewed-by: Dan Horák <dan@danny.cz>
Signed-off-by: Stewart Smith <stewart@flamingspork.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
4 months agofast-reboot: fix TLB cleanup after fast reboot
Nicholas Piggin [Mon, 20 Dec 2021 11:08:52 +0000 (21:08 +1000)] 
fast-reboot: fix TLB cleanup after fast reboot

POWER9/10 are missing TLB flushing after fast reboot. Add it back to
cpu_fast_reboot_complete(), which is where fast-reboot code thinks it
should be.

Suggested-by: Cédric Le Goater <clg@fr.ibm.com>
Fixes: 53ef0db6e2 ("asm/head.S: set POWER9 radix HID bit at entry")
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
5 months agocore/cpu: move sleep/wake synchronisation out from low level code
Nicholas Piggin [Fri, 17 Dec 2021 02:17:24 +0000 (12:17 +1000)] 
core/cpu: move sleep/wake synchronisation out from low level code

The sleep/wake synchronisation involes the waker setting a wake
condition then testing if the target needs to be woken, vs setting
a wake-required flag then testing the wake condition. The low level
sleep state call comes after that.

This patch moves the synchronisation out from the low level sleep
functions and consolidates both copies into one place.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
5 months agocore/cpu: make cpu idle states simpler
Nicholas Piggin [Fri, 17 Dec 2021 02:17:23 +0000 (12:17 +1000)] 
core/cpu: make cpu idle states simpler

Rework the CPU idle state code:

* in_idle is true for any kind of idle including spinning. This is not
  used anywhere except for state assertions for now.

* in_sleep is true for idle that requires an IPI to wake up.

* in_job_sleep is true for in_sleep idle which is also cpu_wake_on_job.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
5 months agocore/cpu: move cpu_wake out of job_lock
Nicholas Piggin [Fri, 17 Dec 2021 02:17:22 +0000 (12:17 +1000)] 
core/cpu: move cpu_wake out of job_lock

There is no need to send the IPI while holding the job_lock. If the
target does wake after the job is queued and before we send the IPI,
it will check for new jobs anyway.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
5 months agocore/cpu: refactor IPI sending
Nicholas Piggin [Fri, 17 Dec 2021 02:17:21 +0000 (12:17 +1000)] 
core/cpu: refactor IPI sending

Pull the IPI sending code into its own function where it is used in
two places.

cpu_wake() already checks in_idle, so its caller does not need to
check pm_enabled.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
5 months agocore/cpu: remove POWER8 IPI loop
Nicholas Piggin [Fri, 17 Dec 2021 02:17:20 +0000 (12:17 +1000)] 
core/cpu: remove POWER8 IPI loop

POWER8 does not have to loop sending IPIs until the destination wakes
up. cpu_wake() only sends IPI so that should be enough here too.

This will help the next patch make a common IPI sending function.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
5 months agocore/cpu: rewrite idle synchronisation
Nicholas Piggin [Fri, 17 Dec 2021 02:17:19 +0000 (12:17 +1000)] 
core/cpu: rewrite idle synchronisation

Idle reconfiguration is difficult to follow and verify as correct
because it can occur while CPUs are in low-level idle routines. For
example pm_enabled can change while CPUs are idle. If nothing else, this
can result in "cpu_idle_p9 called pm disabled" messages.

This changes the idle reconfiuration to always kick all other CPUs out
of idle code first whenever idle settings (pm_enabled, IPIs, sreset,
etc.) are to be changed.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
5 months agochiptod: properly zero TB SPR when cleaning up for invalid TB
Nicholas Piggin [Fri, 17 Dec 2021 02:24:39 +0000 (12:24 +1000)] 
chiptod: properly zero TB SPR when cleaning up for invalid TB

The existing sequence writes TBU twice and leaves TBL unchanged. This
may not really matter if it's being resynced from the chiptod soon, but
it's possible it could clear a parity error.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
5 months agosecvar/pkcs7: fix a wrong sizeof()
Daniel Axtens [Mon, 21 Jun 2021 08:26:41 +0000 (18:26 +1000)] 
secvar/pkcs7: fix a wrong sizeof()

This code isn't directly used by skiboot, but it is wrong and potentially
insecure so I'm fixing it in case it's used in the future.

We pass sizeof(hash) into mbedtls_pk_verify(). However, hash is a pointer,
not an array, so rather than passing the length of the hash to verify we'll
pass in 8, and only compare the first 8 bytes of the hash rather than all 32.

Pass in 0 instead. That tells mbedtls to work out the length based on the
hash type. We allocated enough memory for whatever hash type the PKCS#7
message declared so this will be safe.

Signed-off-by: Daniel Axtens <dja@axtens.net>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
5 months agolibfdt: sync to upstream dtc.git commit 45f3d1a095dd
Nicholas Piggin [Wed, 8 Dec 2021 08:18:43 +0000 (18:18 +1000)] 
libfdt: sync to upstream dtc.git commit 45f3d1a095dd

sync to upstream dtc.git commit 45f3d1a095dd ("libfdt: overlay: make
overlay_get_target() public") from previous upstream sync commit 243176c
("Fix bogus error on rebuild"). This mainly updates license headers,
fixes one or two small bugs, sign mismatches, integer overflow, and
cases of undefined behaviour, compile warnings for newer compilers, and
introduces some checking options (which might be useful to speed up fdt
operations on awan).

The recipe for this patch is:

  $ cp ../dtc/libfdt/* libfdt/
  $ git add libfdt/fdt_check.c
  $ rm libfdt/meson.build

  Then add the INT32_MAX define to libc/include/limits.h, and update
  libfdt/Makefile.inc and libfdt/README.skiboot.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
5 months agoccan: sync to upstream ccan.git commit ca7c5a9e04f3
Nicholas Piggin [Wed, 8 Dec 2021 14:15:58 +0000 (00:15 +1000)] 
ccan: sync to upstream ccan.git commit ca7c5a9e04f3

sync to upstream ccan.git commit ca7c5a9e04f3 ("ccan: make tal_dump()
format more regular.").

The recipe used to sync upstream is:

 $ cd ccan
 $ ./tools/create-ccan-tree -b make tmp \
     array_size check_type container_of heap \
     short_types build_assert endian list str
 $ # replace directories in skiboot/ccan/ with those in tmp/ccan/
 $ cd ../skiboot
 $ patch -p1 < ccan/skiboot.patch

This also adds a README.skiboot to help with future updates.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
5 months agohw/lpc: fix compilation error
Nicholas Piggin [Wed, 8 Dec 2021 14:15:57 +0000 (00:15 +1000)] 
hw/lpc: fix compilation error

Compilation can fail when building tests if the opal-api.h include
is not pulled in via headers. Include it directly.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
5 months agoccan: switch list_add_before/after arguments to match upstream
Nicholas Piggin [Wed, 8 Dec 2021 14:15:56 +0000 (00:15 +1000)] 
ccan: switch list_add_before/after arguments to match upstream

Upstream ccan uses (list, existing entry, new entry) parameter ordering
rather than (list, new entry, existing entry) ordering.

Switch these to make syncing with upstream simpler.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
6 months agohdata: add mmu-pid-bits and mmu-lpid-bits for POWER10 CPUs
Nicholas Piggin [Tue, 9 Nov 2021 07:59:32 +0000 (17:59 +1000)] 
hdata: add mmu-pid-bits and mmu-lpid-bits for POWER10 CPUs

This adds ibm,mmu-pid-bits and a new ibm,mmu-lpid-bits to POWER10 CPUs.
POWER9 Linux has some workarounds for processors bugs that means it's
probably safer to not add the entries there.

Linux already hard codes these values correctly on these processors, but
this allows more flexibility to change things.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
6 months agotest/qemu: Add PCI devices
Cédric Le Goater [Mon, 8 Nov 2021 17:45:44 +0000 (18:45 +0100)] 
test/qemu: Add PCI devices

This defines a PCI layout close to an OpenPOWER system and adds an
optional disk to boot from. Fix verbose runs while we are at it.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
6 months agoCI: Update runs with P10 mambo
Cédric Le Goater [Mon, 8 Nov 2021 17:45:43 +0000 (18:45 +0100)] 
CI: Update runs with P10 mambo

Signed-off-by: Cédric Le Goater <clg@kaod.org>
6 months agoCI: Update centos8 runs with P8 and P9 mambo
Cédric Le Goater [Mon, 8 Nov 2021 17:45:42 +0000 (18:45 +0100)] 
CI: Update centos8 runs with P8 and P9 mambo

Signed-off-by: Cédric Le Goater <clg@kaod.org>
6 months agoCI: Remove travis config file
Frederic Barrat [Fri, 5 Nov 2021 17:26:20 +0000 (18:26 +0100)] 
CI: Remove travis config file

travis.org is dead. Using travis-ci.com has some money implication and
we won't be able to check whether the config is still valid and the
tests passing. We migrated most of the existing CI on travis to github
actions.
So this can only bit-rot so let's remove it.

Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
6 months agoCI: Clean up some Docker files
Frederic Barrat [Fri, 5 Nov 2021 17:26:19 +0000 (18:26 +0100)] 
CI: Clean up some Docker files

Miscellaneous cleanup in the Docker files, mostly removing unneeded packages.

Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
6 months agoCI: Small cleanup in the github actions workflow file
Frederic Barrat [Fri, 5 Nov 2021 17:26:18 +0000 (18:26 +0100)] 
CI: Small cleanup in the github actions workflow file

Strengthen the container security settings, since we don't seem to
need more. The rest of the patch is cosmectic.

Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
6 months agoCI: Rename ubuntu-latest to ubuntu-rolling
Frederic Barrat [Fri, 5 Nov 2021 17:26:17 +0000 (18:26 +0100)] 
CI: Rename ubuntu-latest to ubuntu-rolling

In the docker world, ubuntu-latest is the latest LTS release, 20.04 as
of this writing. ubuntu-rolling is the latest (non-devel) release,
which is 21.10 as of this writing. So rename our CI files accordingly
to avoid confusion.

Also ubuntu 21.10 ships with a recent enough qemu-system-ppc package
so we can now run a simple qemu boot test for powernv. The Docker file
fetches a kernel image from the op-build repo on github.

Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
6 months agoCI: Add Fedora 35 to github actions
Frederic Barrat [Fri, 5 Nov 2021 17:26:16 +0000 (18:26 +0100)] 
CI: Add Fedora 35 to github actions

The only change with Fedora 34 is that since the qemu-system-ppc
package is recent, we can now run the qemu boot test.

Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
6 months agotest/qemu: Fix test
Frederic Barrat [Fri, 5 Nov 2021 17:26:15 +0000 (18:26 +0100)] 
test/qemu: Fix test

Fix a syntax error in the expect script.

Add -nographic when starting qemu to avoid problems on systems where
gtk is installed.

Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
6 months agoREADME: Update path to fetch a kernel image
Frederic Barrat [Fri, 5 Nov 2021 17:26:14 +0000 (18:26 +0100)] 
README: Update path to fetch a kernel image

openpower.xyz no longer exists but op-build now exports artifacts on
github.

Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
6 months agosecvar/edk2: store timestamp variable in protected storage
Eric Richter [Thu, 4 Nov 2021 17:03:06 +0000 (12:03 -0500)] 
secvar/edk2: store timestamp variable in protected storage

Each signed variable update contains a timestamp -- this timestamp is checked
against the previous timestamp seen for that particular variable (if any), and
the update is rejected if the timestamp is not a later time than the previous.

This timestamp check is intended to prevent re-use of signed update files.
Currently, the code stores the timestamps in the TS variable, which is then
stored in regular variable storage (typically PNOR). This patch promotes the
variable to "protected storage" (typically TPM NV), so avoid this variable
being accidentally cleared.

This change should only come into effect when either:
 - initializing secvar for the first time (i.e. first boot, or
    after a key-clear-request)
 - processing any variable update

Systems that already have a TS variable in PNOR will not be affected until
either of the above actions are taken.

Signed-off-by: Eric Richter <erichte@linux.ibm.com>
Tested-by: Nick Child <nick.child@ibm.com>
Reviewed-by: Daniel Axtens <dja@axtens.net>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
6 months agosecvar/secboot_tpm: unify behavior for bank hash check and secboot header check
Eric Richter [Thu, 4 Nov 2021 17:03:05 +0000 (12:03 -0500)] 
secvar/secboot_tpm: unify behavior for bank hash check and secboot header check

As the PNOR variable space cannot be locked, the data must be integrity
checked when loaded to ensure it has not beeen modified by an unauthorized
party. In the event that a modification has been detected (i.e. hash mismatch),
we must not load in data that could potentially be compromised.

However, the previous code was a bit overzealous with its reaction to detecting
a compromised SECBOOT partition, and also had some inconsistencies in behavior.

Case 1: SECBOOT partition cleared.
.init() checks the header for the magic number and version. As neither matches,
will reformat the entire partition. Now, .load_bank() will pass, as the data
was just freshly reformatted (note: this also could trigger the bug addressed
in the previous patch). Only variables in the TPM will be loaded by
.load_bank() as the data in SECBOOT is now empty.

Case 2: Bank hash mismatch.
.load_bank() panics and returns an error code, causing secvar_main() to jump
to the error scenario, which prevents the secvar API from being exposed.
os-secure-enforcing is set unconditionally, and the user will have no API to
manage or attempt to fix their system without issuing a key clear request.

This patch unifies the behavior of both of these cases. Now, .init() handles
checking the header AND comparing the bank hash. If either check fails, the
SECBOOT partition will be reformatted. Variables in the TPM will still be
loaded in the .load_bank() step, and provided the backend stores its
secure boot state in the TPM, secure boot state can be preserved.

Signed-off-by: Eric Richter <erichte@linux.ibm.com>
Tested-by: Nick Child <nick.child@ibm.com>
Reviewed-by: Daniel Axtens <dja@axtens.net>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
6 months agosecvar/secboot_tpm: correctly reset the control index on secboot format
Eric Richter [Thu, 4 Nov 2021 17:03:04 +0000 (12:03 -0500)] 
secvar/secboot_tpm: correctly reset the control index on secboot format

When the SECBOOT partition is formatted, the bank hash stored in the
control TPM NV index must be updated to match, or else we will immediately
fail to load the freshly formatted data at the .load_bank() step.

However, while the secboot_format() function does calculate and update the
bank hash, it only writes the new hash for bank 0. It does not update the
value for bank 1, or set the current active bank. This works as expected if
the active bank bit happens to be set to 0. On the other hand, if the active
bit is set to 1, the freshly formatted bank 1 will be compared against the
unchanged bank hash in bank 1 at the load step, therefore causing an error.

This patch fixes this issue by also setting the active bit to 0 to match
the freshly calculated hash.

Signed-off-by: Eric Richter <erichte@linux.ibm.com>
Tested-by: Nick Child <nick.child@ibm.com>
Reviewed-by: Daniel Axtens <dja@axtens.net>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
6 months agoskiboot.lds.S: add DWARF v5 sections
Cédric Le Goater [Wed, 3 Nov 2021 09:40:15 +0000 (10:40 +0100)] 
skiboot.lds.S: add DWARF v5 sections

This fixes "orphan section" warnings when linking skiboot.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
6 months agoCI: start using github actions
Frederic Barrat [Wed, 3 Nov 2021 09:40:15 +0000 (10:40 +0100)] 
CI: start using github actions

Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
7 months agoskiboot v7.0 release notes v7.0
Vasant Hegde [Mon, 25 Oct 2021 13:32:45 +0000 (19:02 +0530)] 
skiboot v7.0 release notes

Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
7 months agoopal-api: Drop diagnostics data type symbol for PHB5
Frederic Barrat [Mon, 25 Oct 2021 12:42:12 +0000 (14:42 +0200)] 
opal-api: Drop diagnostics data type symbol for PHB5

All PHB5 error registers read when getting the PHB diagnostics data
have the exact same definitions as on PHB4, so we don't need any new
type. OPAL_PHB_ERROR_DATA_TYPE_PHB5 is not used in skiboot. It's
never been imported on linux, so it is safe to remove the symbol.

Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
7 months agoskiboot v6.8.1 release notes
Vasant Hegde [Thu, 22 Jul 2021 06:43:21 +0000 (12:13 +0530)] 
skiboot v6.8.1 release notes

Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
7 months agoskiboot v6.6.6 release notes
Cédric Le Goater [Wed, 29 Sep 2021 10:06:39 +0000 (12:06 +0200)] 
skiboot v6.6.6 release notes

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
7 months agoskiboot v6.7.3 release notes
Vasant Hegde [Thu, 22 Jul 2021 06:28:48 +0000 (11:58 +0530)] 
skiboot v6.7.3 release notes

Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
7 months agoskiboot v6.0.24 release notes
Frederic Barrat [Wed, 29 Sep 2021 10:18:43 +0000 (12:18 +0200)] 
skiboot v6.0.24 release notes

Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
7 months agoxive/p10:: Declare xive2 DT node as an interrupt-controller
Frederic Barrat [Wed, 20 Oct 2021 10:28:26 +0000 (12:28 +0200)] 
xive/p10:: Declare xive2 DT node as an interrupt-controller

This patch fixes errors seen when linux looks for the interrupt to use
for a device LSI:

     pci X:Y:Z of_irq_parse_pci: failed with rc=-22

The of/irq parsing code requires those new properties to be able to
map the interrupt specifier correctly. It was not needed before
comitting cd12ea6d8e1 ("interrupts: Do not advertise XICS support on
P10"), because the LSI mapping code was defaulting to the XICS
interrupt controller node, which is now removed (and had those
properties).

Fixes: cd12ea6d8e1 ("interrupts: Do not advertise XICS support on P10")
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
7 months agopau: Add support for OpenCAPI Persistent Memory devices.
Christophe Lombard [Thu, 14 Oct 2021 15:57:04 +0000 (17:57 +0200)] 
pau: Add support for OpenCAPI Persistent Memory devices.

Lowest Point of Coherency (LPC) memory allows the host to access memory on
an OpenCAPI device.

When the P10 chip accesses memory addresses on the AFU, the Real Address
on the PowerBus must hit a BAR in the PAU such as GPU-Memory BAR. The BAR
defines the range of Real Addresses that represent AFU memory.

The two existing OPAL calls, OPAL_NPU_MEM_ALLOC and OPAL_NPU_MEM_RELEASE
are used to manage the AFU momory.

Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
7 months agopau: mmio invalidates
Christophe Lombard [Thu, 14 Oct 2021 15:57:03 +0000 (17:57 +0200)] 
pau: mmio invalidates

The remaining translation mode: OpenCAPI 5.0 with TLBI/SLBI Snooping, is
not used due to performance problems caused by the mismatch between the
ERAT and Bloom Filter sizes.

When the Address Translation Mode requires TLB and SLB Invalidate
operations to be initiated using MMIO registers, a set of registers like
the following is used:
• XTS MMIO ATSD0 LPARID register
• XTS MMIO ATSD0 AVA register
• XTS MMIO ATSD0 launch register, write access initiates a shoot down
• XTS MMIO ATSD0 status register

Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
7 months agopau: update current opal call functions
Christophe Lombard [Thu, 14 Oct 2021 15:57:02 +0000 (17:57 +0200)] 
pau: update current opal call functions

Update the content of three current OPAL API calls to support PAU.

  - OPAL_NPU_SPA_SETUP

    The Shared Process Area (SPA) is a table containing one entry (a
    "Process Element") per memory context which can be accessed by the
    OpenCAPI device.

  - OPAL_NPU_SPA_CLEAR_CACHE

    The PAU keeps a cache of recently accessed memory contexts. When a
    Process Element is removed from the SPA, the cache for the link must
    be cleared.

  - OPAL_NPU_TL_SET

    The Transaction Layer specification defines several templates for
    messages to be exchanged on the link. During link setup, the host
    and device must negotiate what templates are supported on both sides
    and at what rates those messages can be sent.

Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
7 months agopau: link training
Christophe Lombard [Thu, 14 Oct 2021 15:57:01 +0000 (17:57 +0200)] 
pau: link training

Add elementary functions to handle a phb complete, fundamental and
hot resets.
For the time being, specific creset and hreset are not supported.

A complete fundamental reset is based on the following steps, in this
order:
- Place all bricks into Fence state
- Disable BARs
- Reset ODL to Power-on Values
- Set the i2c reset pin in output mode
- Initialize PHY Lanes
- Deassert ODL reset
- Clear the the i2c reset pin
- Unfence bricks
- Enable BARs
- Enable ODL training mode

Link training is also set up.

Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
7 months agopau: phy init
Christophe Lombard [Thu, 14 Oct 2021 15:57:00 +0000 (17:57 +0200)] 
pau: phy init

Follow the Procedure IO_INIT_RESET_PON as described in the
P10 OPHY workbook document to reset and initialize the PHY lanes.

The memory mapped SRAM (64 bit aligned) has to be used to configure the
PHY, which is reachable the linked registers: address and data.
The different links can be configured at the same time, that implies using
a global lock to avoid conflicts.

Authored-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
7 months agopau: hmi scom dump
Christophe Lombard [Thu, 14 Oct 2021 15:56:59 +0000 (17:56 +0200)] 
pau: hmi scom dump

This patch add a new function to dump PAU registers when a HMI has been
raised and an OpenCAPI link has been hit by an error.

For each register, the scom address and the register value are printed.

The hmi.c has been redesigned in order to support the new PHB/PCIEX
type (PAU OpenCapi). Now, the *npu* functions support NPU and PAU units of
P8, P9 and P10 chips.

Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
7 months agopau: complete phb ops
Christophe Lombard [Thu, 14 Oct 2021 15:56:58 +0000 (17:56 +0200)] 
pau: complete phb ops

Add more PHB interfaces:
- to control pci error type in case of freeze.
- add the addresses of the registers needed by the OS to handle
translation failures.
- to detect the fence state of a specific brick
- to configure BDF (Bus Device Function) and PE (Partitionable Endpoint)
for context identification.

Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
7 months agopau: enable interrupt on error
Christophe Lombard [Thu, 14 Oct 2021 15:56:57 +0000 (17:56 +0200)] 
pau: enable interrupt on error

The default action for the errors (unexpected errors on the opencapi
link) reported in the PAU FIR2 registe is mostly set to system
checkstop.

This patch changes the default action of those errors so that the PAU
will raise an interrupt instead. Interrupt information are logged so
that the error can be debugged and linux can catch the event.

Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
7 months agopau: translation layer configuration
Christophe Lombard [Thu, 14 Oct 2021 15:56:56 +0000 (17:56 +0200)] 
pau: translation layer configuration

Next main part of the hypervisor PAU initialization.
The P10 PAU supports two OpenCAPI links.
The PAU provides various configuration selections for both of the OCAPI
Link Transaction Layer functions (OTLs). These include a link enable,
behavior controls, debug modes, and virtual channel credits to send to
the AFU. The OTL Configuration 0, OTL Configuration 1, OTL
Configuration 2, and TLX Credit Configuration registers are used to
control these functions.

This patch completes the PAU configuration following the
sections 17.1.3.4 to 17.1.3.10.2 of the workbook document.

Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
7 months agopau: enabling opencapi
Christophe Lombard [Thu, 14 Oct 2021 15:56:55 +0000 (17:56 +0200)] 
pau: enabling opencapi

Enable OpenCAPI mode for each brick which are connected to be used in
this mode. This is be done through 7 steps as described in the
P10 OCAPI 5.0 Processing Unit Workbook document, section:
17.1.3.1 Enabling OpenCAPI.
The following sequences must be performed:
1. Set Transport MUX controls to select OpenCAPI
2. Enable Clocks in XSL
3. Enable Clocks in MISC
4. Set NPCQ configuration
5. Enable XSL-XTS Interfaces
6. Enable State-machine allocation

Enabling the NTL/GENID BARS allows to access to the MMIO registers.

Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
7 months agopau: create phb
Christophe Lombard [Thu, 14 Oct 2021 15:56:54 +0000 (17:56 +0200)] 
pau: create phb

Implement the necessary operations for the OpenCAPI PHB type and
inform the device-tree properties associated.

The OpenCapi PCI config Addr/Data registers are reachable through
the Generation-ID Registers MMIO BARS.
The Config Address and Data registers are located at the following offsets
from the AFU Config BAR plus 320 KB.
• Config Address for Brick 0 – Offset 0
• Config Data for Brick 0 – Offsets:
◦ 128 – 4-byte config register

• Config Address for Brick 1 – Offset 256
• Config Data for Brick 1 – Offsets:
◦ 384 – 4-byte config register

Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
7 months agopau: assign bars
Christophe Lombard [Thu, 14 Oct 2021 15:56:53 +0000 (17:56 +0200)] 
pau: assign bars

Configure early PAU Global MMIO BAR registers to allow PAU MMIO
register accesses. This is done for each PAU. Enable the Powerbus
interface is mandatory for MMIO accesses.
For each OpenCAPI device, configure the bar registers to access to
the AFU MMIO and to the AFU Config Addr/Data registers.

AFU Config/Data registers = GENID_ADDR (from phy_map file) + 320K
(= 0x50000)

Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
7 months agorainier: detect pau devices
Christophe Lombard [Thu, 14 Oct 2021 15:56:52 +0000 (17:56 +0200)] 
rainier: detect pau devices

Update the platform_ocapi structure to store Rainier platform-specific
values for detecting and resetting OpenCAPI devices via the module
I2C (PCA9553)
The unique number I2C bus ID associated to each OpenCapi device
is get from the I2C port and engine.
(De)Assert a reset and detect an OpenCapi device is available through
the I2C bus id and address.

Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
7 months agopau: introduce support
Christophe Lombard [Thu, 14 Oct 2021 15:56:51 +0000 (17:56 +0200)] 
pau: introduce support

OpenCapi for P10 is included in the P10 chip. This requires OCAPI capable
PHYs, Datalink Layer Logic and Transaction Layer Logic to be included.
The PHYs are the physical connection to the OCAPI interconnect.
The Datalink Layer provides link training.
The Transaction Layer executes the cache coherent and data movement
commands on the P10 chip.
The PAU provides the Transaction Layer functionality for the OCAPI
link(s) on the P10 chip.

The P10 PAU supports two OCAPI links. Six accelerator units PAUs are
instantiated on the P10 chip for a total of twelve OCAPI links.

This patch adds PAU opencapi structure for supporting OpenCapi5.
hw/pau.c file contains main of PAU management functions.

Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
7 months agonpu2: move opal api
Christophe Lombard [Thu, 14 Oct 2021 15:56:50 +0000 (17:56 +0200)] 
npu2: move opal api

Move the OPAL entry points for npu2 opencapi to the common opal NPU
file. This prepares us to add same entries for PAU opencapi in this common
file.

No functional change.

Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
7 months agoAWAN simulator support for P10
Ryan Grimm [Wed, 8 Sep 2021 16:57:59 +0000 (11:57 -0500)] 
AWAN simulator support for P10

This patch enables Skiboot to initialize and Linux to boot to user space
on the AWAN core and chip models.

We need the distinction between core and chip models because the core
models do not have an XSCOM unit, CHIPTOD, nor RNG.  The chip
model does have them and they work.

So, add a device_type property to the awan node to distinguish core from
chip.  Sample DTS are provided for the core and chip models in
external/awan.

Just like Mambo, we need to return in slw_init before trying to
initialize SLW.  Without an XSCOM unit in the device tree for the core
model, the SLW code path eventually fails an assert due to lack of
chips.

This commit defines a QUIRK_AWAN where previously Mambo used
QUIRK_MAMBO_CALLOUTS so now Mambo and AWAN core both work.

Also, fix up chip quirks so the core model and chip model boot and
initialize the appropriate units.

Disable sreset and power management in a couple spots because the chip
model does not support stop with EC=1 and enter_p9_pm_state spins in the
branch-to-self after stop.

Provide an external/awan/README.md with a high-level view of booting in
the environment.

Signed-off-by: Ryan Grimm <grimm@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
7 months agoflash: AST BMC endian fixes
Nicholas Piggin [Sun, 3 Oct 2021 01:22:10 +0000 (11:22 +1000)] 
flash: AST BMC endian fixes

Fix endian for the 4-byte LPC copy similarly to other flash drivers.
This allows flash to be detected on POWER8 AST BMC systems with a LE
skiboot.

Fix incorrect comments in those other drivers while we're here.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
7 months agophb3: make endian-clean
Nicholas Piggin [Sun, 3 Oct 2021 01:22:09 +0000 (11:22 +1000)] 
phb3: make endian-clean

Convert phb3 dt construction and in-memory hardware tables to use
explicit endian conversions.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
7 months agoRemove support for POWER8 DD1
Nicholas Piggin [Sun, 3 Oct 2021 01:22:08 +0000 (11:22 +1000)] 
Remove support for POWER8 DD1

This significantly simplifies the SLW code.

HILE is now always supported.

Reviewed-by: Stewart Smith <stewart@flamingspork.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
7 months agophb4: annotate tbl_pest with endian types
Nicholas Piggin [Sun, 3 Oct 2021 01:22:07 +0000 (11:22 +1000)] 
phb4: annotate tbl_pest with endian types

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
7 months agoasm/head: Fix P10 HILE for little endian build
Nicholas Piggin [Sun, 3 Oct 2021 01:22:06 +0000 (11:22 +1000)] 
asm/head: Fix P10 HILE for little endian build

Fixes: 891ed8df67 ("Initial POWER10 enablement")
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
7 months agocpu: add debug check in cpu_relax
Nicholas Piggin [Sun, 3 Oct 2021 01:22:05 +0000 (11:22 +1000)] 
cpu: add debug check in cpu_relax

If cpu_relax() is called when not at medium SMT priority, it will lose
the prior priority and return at medium. Add a debug check to catch
this, which would have flagged the previous bug.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
7 months agocpu: cpu_idle_job SMT priority fix
Nicholas Piggin [Sun, 3 Oct 2021 01:22:04 +0000 (11:22 +1000)] 
cpu: cpu_idle_job SMT priority fix

Calling cpu_relax resets the SMT priority to medium, causing the idle
loop not to run with lowest priority. Just use barrier() instead, this
saves about 3 seconds on a SMT4 systemsim (mambo) boot.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
7 months agointerrupts: add_opal_interrupts avoid NULL dereference on P10 mambo
Nicholas Piggin [Sun, 3 Oct 2021 01:22:03 +0000 (11:22 +1000)] 
interrupts: add_opal_interrupts avoid NULL dereference on P10 mambo

On P10, get_ics_phandle() calls xive2_get_phandle() directly. This
results in a NULL dereference on mambo when xive2 is not set up.

This was caught with the virtual memory boot patch on P10 mambo.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
7 months agoHBRT: fix clobbered r16 when host services handlers are called
Nicholas Piggin [Tue, 12 Oct 2021 10:55:18 +0000 (20:55 +1000)] 
HBRT: fix clobbered r16 when host services handlers are called

Skiboot is using r16 as a fixed register containing this CPU pointer,
but we can be called back into from hostboot via the host services
interface, where r16 may have been set by hostboot. Switch this back to
skiboot's CPU pointer before running host services handlers, and then
restore it to the hostboot value before returning.

Fixes: 11ce9612b3aa ("move the __this_cpu register to r16, reserve r13-r15")
Reported-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
Tested-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
7 months agophb5: Remove obsolete capp-related properties
Frederic Barrat [Wed, 22 Sep 2021 14:14:44 +0000 (16:14 +0200)] 
phb5: Remove obsolete capp-related properties

This patch removes the following properties from PHB entries in the
device tree on P10, since there's no CAPP any more and the properties
no longer make sense:
ibm,phb-indications
ibm,capp-timebase-sync
ibm,capi-flags

It has no effect on linux: some were already ignored and others won't
even be read since the cxl driver (the only consumer) already fails
early on P10.

Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
7 months agoexternal/mambo: Add POWER10 small-core mode
Nicholas Piggin [Sat, 2 Oct 2021 02:26:43 +0000 (12:26 +1000)] 
external/mambo: Add POWER10 small-core mode

If the SMT configuration is not 8, set small-core mode in SIM_CTRL1
and PVR registers.

Also allow only 1, 2, 4, or 8 threads, and only allow 1 and 2 threads
if there is only one processor configured. This helps avoid strange
crashes due to thread/core enumeration problems with unexpected threads
per core.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
7 months agoexternal/mambo: Updates POWER9 SIM_CTRL1 to remove hardware atomic RC
Nicholas Piggin [Fri, 1 Oct 2021 10:46:48 +0000 (20:46 +1000)] 
external/mambo: Updates POWER9 SIM_CTRL1 to remove hardware atomic RC

Update SIM_CTRL1 bits to set ARC0/1, which disables atomic RC updates in
hardware which matches implementation.

Comment some remaining quirks with the P9 configuration.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
7 months agoexternal/mambo: Updates for POWER10 configuration for DD2.0
Nicholas Piggin [Fri, 1 Oct 2021 10:46:47 +0000 (20:46 +1000)] 
external/mambo: Updates for POWER10 configuration for DD2.0

Update PVR and mambo f000f bits:
- Set POWER10 to DD2.0

Update SIM_CTRL and SIM_CTRL1 bits:
- Set the LPAR-per-core mode bit. This is required for SMT KVM to work.
- Set ARC0/ARC1 bits which enable atomic RC update interrupts (not
  hardware updates), which matches implementation.
- Enable DEXCR, HAIL, ROP, BHRB disable, block BHRB writes in PR=0,
  and RFC02628 on POWER10.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
8 months agosecvar: Free md context on hash error
Nick Child [Wed, 11 Aug 2021 15:02:31 +0000 (11:02 -0400)] 
secvar: Free md context on hash error

There were a few instances in `get_hash_to_verify` where NULL is
returned before unallocating the md context. This commit ensures that
this memory is properly freed before returning.

Signed-off-by: Nick Child <nick.child@ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
8 months agonpu3: Remove GPU support on Swift
Frederic Barrat [Mon, 30 Aug 2021 12:06:33 +0000 (14:06 +0200)] 
npu3: Remove GPU support on Swift

npu3 was only used on the Swift platform to add support for
GPUs (nvlink). The Swift platform has never left the lab and support
for GPUs on it is pretty much dead. So let's remove it.

The patch removes all related code. Device tree entries are no
longer created and in the very unlikely case that someone is still
trying to boot it, the linux nvlink discovery code should be quiet.

Tested by booting on Swift with no GPU.

Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Reza Arbab <arbab@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
8 months agodocs: Add Swift, Mowgli & Rainier
Michael Ellerman [Tue, 31 Aug 2021 23:40:06 +0000 (09:40 +1000)] 
docs: Add Swift, Mowgli & Rainier

Signed-off-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
8 months agodoc: Make it clear all existing platforms use Power9N
Michael Ellerman [Tue, 31 Aug 2021 23:40:05 +0000 (09:40 +1000)] 
doc: Make it clear all existing platforms use Power9N

Update the table of platforms to make it clear which Power9 CPU each
uses, currently they all use Power9N.

Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
8 months agoexternal/mambo: Print more info when the kernel is too big
Michael Ellerman [Tue, 31 Aug 2021 23:06:17 +0000 (09:06 +1000)] 
external/mambo: Print more info when the kernel is too big

Make it a bit easier to boot large kernels by printing more info when
the kernel is too big, so the user has some idea how much they need to
adjust PAYLOAD_ADDR by.

Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
9 months agohello_world: Add p10 mambo tests
Vasant Hegde [Thu, 19 Aug 2021 15:40:39 +0000 (21:10 +0530)] 
hello_world: Add p10 mambo tests

Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
9 months agoci: Bump qemu version
Vasant Hegde [Thu, 19 Aug 2021 15:41:03 +0000 (21:11 +0530)] 
ci: Bump qemu version

Move to qemu version powernv-6.1.

Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
9 months agophb4/5: Escalate page-level TCE kills
Frederic Barrat [Wed, 25 Aug 2021 15:04:08 +0000 (17:04 +0200)] 
phb4/5: Escalate page-level TCE kills

An hw issue was found on P10 (HW560152) where a page-level TCE kill
can be dropped if there are enough TCE kill requests already being
processed. The net effect is that data integrity is not
guaranteed. The circumvention is to stay away from page-level kills
and escalate those to PE kills. Which hurts performance.
It also affects P9.

Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
9 months agointerrupts: Do not advertise XICS support on P10
Cédric Le Goater [Sat, 7 Aug 2021 07:38:21 +0000 (09:38 +0200)] 
interrupts: Do not advertise XICS support on P10

We only support the XIVE interface.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
9 months agoxive/p10: Fix mismatch errors when DEBUG=1
Cédric Le Goater [Sat, 7 Aug 2021 07:38:20 +0000 (09:38 +0200)] 
xive/p10: Fix mismatch errors when DEBUG=1

HW has some reserved fields which break the comparison when checking
END cache updates.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>